intel: updated header for contexts
authorBen Widawsky <ben@bwidawsk.net>
Wed, 27 Jun 2012 16:52:42 +0000 (09:52 -0700)
committerBen Widawsky <ben@bwidawsk.net>
Wed, 27 Jun 2012 16:57:16 +0000 (09:57 -0700)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-By: Kenneth Graunke <kenneth@whitecape.org>
include/drm/i915_drm.h

index 4931107c550ac8b179d1d07f7b787cd6a991a70c..5c8fabe0473b08b069ee0332178f02fda1d4c188 100644 (file)
@@ -193,6 +193,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GET_SPRITE_COLORKEY   0x2a
 #define DRM_I915_SET_SPRITE_COLORKEY   0x2b
 #define DRM_I915_GEM_WAIT      0x2c
+#define DRM_I915_GEM_CONTEXT_CREATE    0x2d
+#define DRM_I915_GEM_CONTEXT_DESTROY   0x2e
 
 #define DRM_IOCTL_I915_INIT            DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH           DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -237,6 +239,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT                DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY     DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -651,13 +655,19 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_CONSTANTS_ABSOLUTE   (1<<6)
 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
        __u64 flags;
-       __u64 rsvd1;
+       __u64 rsvd1; /* now used for context info */
        __u64 rsvd2;
 };
 
 /** Resets the SO write offset registers for transform feedback on gen7. */
 #define I915_EXEC_GEN7_SOL_RESET       (1<<8)
 
+#define I915_EXEC_CONTEXT_ID_MASK      (0xffffffff)
+#define i915_execbuffer2_set_context_id(eb2, context) \
+       (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
+#define i915_execbuffer2_get_context_id(eb2) \
+       ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
+
 struct drm_i915_gem_pin {
        /** Handle of the buffer to be pinned. */
        __u32 handle;
@@ -889,4 +899,15 @@ struct drm_i915_gem_wait {
        __s64 timeout_ns;
 };
 
+struct drm_i915_gem_context_create {
+       /*  output: id of new context*/
+       __u32 ctx_id;
+       __u32 pad;
+};
+
+struct drm_i915_gem_context_destroy {
+       __u32 ctx_id;
+       __u32 pad;
+};
+
 #endif                         /* _I915_DRM_H_ */