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raw | patch | inline | side by side (parent: a3c34f5)
raw | patch | inline | side by side (parent: a3c34f5)
author | Eugeni Dodonov <eugeni@dodonov.net> | |
Fri, 30 Mar 2012 00:03:29 +0000 (21:03 -0300) | ||
committer | Eugeni Dodonov <eugeni.dodonov@intel.com> | |
Sun, 1 Apr 2012 14:03:36 +0000 (11:03 -0300) |
We were missing this one and it is being used by Bromolow.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
intel/intel_chipset.h | patch | blob | history |
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 435d01a365dbe165fd365d8c55191f9030f22b9b..9c1abc863f17073776f814b12d9c311e5b0a14ef 100644 (file)
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
+#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
dev == PCI_CHIP_IVYBRIDGE_GT2 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- dev == PCI_CHIP_IVYBRIDGE_S)
+ dev == PCI_CHIP_IVYBRIDGE_S || \
+ dev == PCI_CHIP_IVYBRIDGE_S_GT2)
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
devid == PCI_CHIP_HASWELL_M_GT1)