a9cac28ba705fc6fa10e3ef8f51028f4269e0d16
[glsdk/meta-ti-glsdk.git] / recipes-bsp / linux / linux-omap-psp-2.6.32 / cam / 0041-MT9V113-Min-Max-clk-input-changed-as-per-the-spec.patch
1 From b174adfdb2836b01f8306f6112b7a8c36540f7d2 Mon Sep 17 00:00:00 2001
2 From: Vaibhav Hiremath <hvaibhav@ti.com>
3 Date: Tue, 13 Jul 2010 19:40:39 +0530
4 Subject: [PATCH 41/75] MT9V113: Min, Max clk input changed as per the spec
6 Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
7 ---
8 arch/arm/mach-omap2/board-omap3beagle-camera.c | 2 +-
9 drivers/media/video/isp/ispreg.h | 2 +-
10 include/media/mt9v113.h | 2 +-
11 3 files changed, 3 insertions(+), 3 deletions(-)
13 diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c
14 index be59040..8d4e5ab 100644
15 --- a/arch/arm/mach-omap2/board-omap3beagle-camera.c
16 +++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c
17 @@ -198,7 +198,7 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power)
18 mdelay(50);
20 /* Enable EXTCLK */
21 - isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN, CAM_USE_XCLKA);
22 + isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN*2, CAM_USE_XCLKA);
23 /*
24 * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN):
25 * ((1000000 * 70) / 6000000) = aprox 12 us.
26 diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h
27 index 1240e0e..098713e 100644
28 --- a/drivers/media/video/isp/ispreg.h
29 +++ b/drivers/media/video/isp/ispreg.h
30 @@ -116,7 +116,7 @@
31 #define ISP_32B_BOUNDARY_BUF 0xFFFFFFE0
32 #define ISP_32B_BOUNDARY_OFFSET 0x0000FFE0
34 -#define CM_CAM_MCLK_HZ 172800000 /* Hz */
35 +#define CM_CAM_MCLK_HZ 216000000 /* Hz */
37 /* ISP Submodules offset */
39 diff --git a/include/media/mt9v113.h b/include/media/mt9v113.h
40 index 0a30f4c..4504f26 100644
41 --- a/include/media/mt9v113.h
42 +++ b/include/media/mt9v113.h
43 @@ -76,7 +76,7 @@ struct mt9v113_platform_data {
44 #define MT9V113_VGA_30FPS (1130)
45 #define MT9V113_QVGA_30FPS (1131)
47 -#define MT9V113_CLK_MAX (54000000) /* 54MHz */
48 +#define MT9V113_CLK_MAX (48000000) /* 48MHz */
49 #define MT9V113_CLK_MIN (6000000) /* 6Mhz */
51 #endif /* ifndef _MT9V113_H */
52 --
53 1.6.6.1