linux-omap 2.6.37: sync with OE .dev
[glsdk/meta-ti-glsdk.git] / recipes-bsp / linux / linux-omap / media / 0023-v4l-Group-media-bus-pixel-codes-by-types-and-sort-th.patch
1 From 9a13751e47503b4c966538e194a5027e5e7d9c5d Mon Sep 17 00:00:00 2001
2 From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
3 Date: Wed, 1 Sep 2010 17:58:22 +0200
4 Subject: [PATCH 23/43] v4l: Group media bus pixel codes by types and sort them alphabetically
6 Adding new pixel codes at the end of the enumeration will soon create a
7 mess, so group the pixel codes by type and sort them by bus_width, bits
8 per component, samples per pixel and order of subsamples.
10 As the codes are part of the kernel ABI their value can't change when a
11 new code is inserted in the enumeration, so they are given an explicit
12 numerical value. When inserting a new pixel code developers must use and
13 update the next free value.
15 Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
16 ---
17  include/linux/v4l2-mediabus.h |   77 ++++++++++++++++++++++++----------------
18  1 files changed, 46 insertions(+), 31 deletions(-)
20 diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h
21 index dc1d5c0..cccfa34 100644
22 --- a/include/linux/v4l2-mediabus.h
23 +++ b/include/linux/v4l2-mediabus.h
24 @@ -24,39 +24,54 @@
25   * transferred first, "BE" means that the most significant bits are transferred
26   * first, and "PADHI" and "PADLO" define which bits - low or high, in the
27   * incomplete high byte, are filled with padding bits.
28 + *
29 + * The pixel codes are grouped by type, bus_width, bits per component, samples
30 + * per pixel and order of subsamples. Numerical values are sorted using generic
31 + * numerical sort order (8 thus comes before 10).
32 + *
33 + * As their value can't change when a new pixel code is inserted in the
34 + * enumeration, the pixel codes are explicitly given a numerical value. The next
35 + * free values for each category are listed below, update them when inserting
36 + * new pixel codes.
37   */
38  enum v4l2_mbus_pixelcode {
39 -       V4L2_MBUS_FMT_FIXED = 1,
40 -       V4L2_MBUS_FMT_YUYV8_2X8,
41 -       V4L2_MBUS_FMT_YVYU8_2X8,
42 -       V4L2_MBUS_FMT_UYVY8_2X8,
43 -       V4L2_MBUS_FMT_VYUY8_2X8,
44 -       V4L2_MBUS_FMT_YVYU10_2X10,
45 -       V4L2_MBUS_FMT_YUYV10_2X10,
46 -       V4L2_MBUS_FMT_YVYU10_1X20,
47 -       V4L2_MBUS_FMT_YUYV10_1X20,
48 -       V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
49 -       V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE,
50 -       V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
51 -       V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
52 -       V4L2_MBUS_FMT_RGB565_2X8_LE,
53 -       V4L2_MBUS_FMT_RGB565_2X8_BE,
54 -       V4L2_MBUS_FMT_BGR565_2X8_LE,
55 -       V4L2_MBUS_FMT_BGR565_2X8_BE,
56 -       V4L2_MBUS_FMT_SBGGR8_1X8,
57 -       V4L2_MBUS_FMT_SBGGR10_1X10,
58 -       V4L2_MBUS_FMT_Y8_1X8,
59 -       V4L2_MBUS_FMT_Y10_1X10,
60 -       V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE,
61 -       V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE,
62 -       V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE,
63 -       V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE,
64 -       V4L2_MBUS_FMT_SGRBG8_1X8,
65 -       V4L2_MBUS_FMT_SBGGR12_1X12,
66 -       V4L2_MBUS_FMT_YUYV8_1_5X8,
67 -       V4L2_MBUS_FMT_YVYU8_1_5X8,
68 -       V4L2_MBUS_FMT_UYVY8_1_5X8,
69 -       V4L2_MBUS_FMT_VYUY8_1_5X8,
70 +       V4L2_MBUS_FMT_FIXED = 0x0001,
71 +
72 +       /* RGB - next is 0x1009 */
73 +       V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE = 0x1001,
74 +       V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE = 0x1002,
75 +       V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE = 0x1003,
76 +       V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE = 0x1004,
77 +       V4L2_MBUS_FMT_BGR565_2X8_BE = 0x1005,
78 +       V4L2_MBUS_FMT_BGR565_2X8_LE = 0x1006,
79 +       V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
80 +       V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
81 +
82 +       /* YUV (including grey) - next is 0x200f */
83 +       V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
84 +       V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002,
85 +       V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003,
86 +       V4L2_MBUS_FMT_YUYV8_1_5X8 = 0x2004,
87 +       V4L2_MBUS_FMT_YVYU8_1_5X8 = 0x2005,
88 +       V4L2_MBUS_FMT_UYVY8_2X8 = 0x2006,
89 +       V4L2_MBUS_FMT_VYUY8_2X8 = 0x2007,
90 +       V4L2_MBUS_FMT_YUYV8_2X8 = 0x2008,
91 +       V4L2_MBUS_FMT_YVYU8_2X8 = 0x2009,
92 +       V4L2_MBUS_FMT_Y10_1X10 = 0x200a,
93 +       V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b,
94 +       V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c,
95 +       V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
96 +       V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
97 +
98 +       /* Bayer - next is 0x3009 */
99 +       V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
100 +       V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
101 +       V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003,
102 +       V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004,
103 +       V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005,
104 +       V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006,
105 +       V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007,
106 +       V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008,
107  };
108  
109  /**
110 -- 
111 1.6.6.1