1 From 2226921518eebb215ddadce09efb35b99a9db8ac Mon Sep 17 00:00:00 2001
2 From: Syed Mohammed Khasim <khasim@ti.com>
3 Date: Sun, 11 Apr 2010 17:44:39 +0200
4 Subject: [PATCH 10/16] Enable DSS driver for Beagle
6 Configures DSS to display color bar on Svideo
7 Configures DSS to display background color on DVID
9 Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
10 ---
11 board/ti/beagle/beagle.c | 1 +
12 board/ti/beagle/beagle.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++
13 2 files changed, 61 insertions(+), 0 deletions(-)
15 diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
16 index 04e4259..7c80a97 100644
17 --- a/board/ti/beagle/beagle.c
18 +++ b/board/ti/beagle/beagle.c
19 @@ -318,6 +318,7 @@ int misc_init_r(void)
20 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
22 dieid_num_r();
23 + omap3_dss_enable();
25 return 0;
26 }
27 diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
28 index 48228dc..bdf2a6f 100644
29 --- a/board/ti/beagle/beagle.h
30 +++ b/board/ti/beagle/beagle.h
31 @@ -23,6 +23,8 @@
32 #ifndef _BEAGLE_H_
33 #define _BEAGLE_H_
35 +#include <asm/arch/dss.h>
36 +
37 const omap3_sysinfo sysinfo = {
38 DDR_STACKED,
39 "OMAP3 Beagle board",
40 @@ -471,6 +473,64 @@ const omap3_sysinfo sysinfo = {
41 MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
43 /*
44 + * Display Configuration
45 + */
46 +
47 +#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
48 +#define VENC_HEIGHT 0x00ef
49 +#define VENC_WIDTH 0x027f
50 +
51 +/*
52 + * Configure VENC in DSS for Beagle to generate Color Bar
53 + *
54 + * Kindly refer to OMAP TRM for definition of these values.
55 + */
56 +static const struct venc_regs venc_config_std_tv = {
57 + .status = 0x0000001B,
58 + .f_control = 0x00000040,
59 + .vidout_ctrl = 0x00000000,
60 + .sync_ctrl = 0x00008000,
61 + .llen = 0x00008359,
62 + .flens = 0x0000020C,
63 + .hfltr_ctrl = 0x00000000,
64 + .cc_carr_wss_carr = 0x043F2631,
65 + .c_phase = 0x00000024,
66 + .gain_u = 0x00000130,
67 + .gain_v = 0x00000198,
68 + .gain_y = 0x000001C0,
69 + .black_level = 0x0000006A,
70 + .blank_level = 0x0000005C,
71 + .x_color = 0x00000000,
72 + .m_control = 0x00000001,
73 + .bstamp_wss_data = 0x0000003F,
74 + .s_carr = 0x21F07C1F,
75 + .line21 = 0x00000000,
76 + .ln_sel = 0x00000015,
77 + .l21__wc_ctl = 0x00001400,
78 + .htrigger_vtrigger = 0x00000000,
79 + .savid__eavid = 0x069300F4,
80 + .flen__fal = 0x0016020C,
81 + .lal__phase_reset = 0x00060107,
82 + .hs_int_start_stop_x = 0x008D034E,
83 + .hs_ext_start_stop_x = 0x000F0359,
84 + .vs_int_start_x = 0x01A00000,
85 + .vs_int_stop_x__vs_int_start_y = 0x020501A0,
86 + .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
87 + .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
88 + .vs_ext_stop_y = 0x00000006,
89 + .avid_start_stop_x = 0x03480079,
90 + .avid_start_stop_y = 0x02040024,
91 + .fid_int_start_x__fid_int_start_y = 0x0001008A,
92 + .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
93 + .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
94 + .tvdetgp_int_start_stop_x = 0x00140001,
95 + .tvdetgp_int_start_stop_y = 0x00010001,
96 + .gen_ctrl = 0x00FF0000,
97 + .output_control = 0x0000000D,
98 + .dac_b__dac_c = 0x00000000
99 +};
100 +
101 +/*
102 * Configure Timings for DVI D
103 */
104 static const struct panel_config dvid_cfg = {
105 --
106 1.6.6.1