6a0baea79b7aff04fa5a4ca5e8b68aafa2266763
1 From afa9025604773b90831cb93a5c80db8d2b8eed4b Mon Sep 17 00:00:00 2001
2 From: Syed Mohammed Khasim <khasim@ti.com>
3 Date: Tue, 12 Jan 2010 23:57:28 +0530
4 Subject: [PATCH 25/51] Add DSS driver for OMAP3
6 Supports dynamic panel configuration
7 Supports dynamic tv standard selection
8 Adds support for DSS register access through generic APIs
10 Incorporated DSS register access using structures.
12 Previous discussions are here
13 http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html
15 Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
16 ---
17 drivers/video/Makefile | 1 +
18 drivers/video/omap3_dss.c | 130 ++++++++++++++++++++++++++++
19 include/asm-arm/arch-omap3/dss.h | 173 ++++++++++++++++++++++++++++++++++++++
20 3 files changed, 304 insertions(+), 0 deletions(-)
21 create mode 100644 drivers/video/omap3_dss.c
22 create mode 100644 include/asm-arm/arch-omap3/dss.h
24 diff --git a/drivers/video/Makefile b/drivers/video/Makefile
25 index a5e339a..44d7ae8 100644
26 --- a/drivers/video/Makefile
27 +++ b/drivers/video/Makefile
28 @@ -38,6 +38,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
29 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
30 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
31 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
32 +COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
33 COBJS-y += videomodes.o
35 COBJS := $(COBJS-y)
36 diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
37 new file mode 100644
38 index 0000000..69c705a
39 --- /dev/null
40 +++ b/drivers/video/omap3_dss.c
41 @@ -0,0 +1,130 @@
42 +/*
43 + * (C) Copyright 2010
44 + * Texas Instruments, <www.ti.com>
45 + * Syed Mohammed Khasim <khasim@ti.com>
46 + *
47 + * Referred to Linux DSS driver files for OMAP3
48 + *
49 + * See file CREDITS for list of people who contributed to this
50 + * project.
51 + *
52 + * This program is free software; you can redistribute it and/or
53 + * modify it under the terms of the GNU General Public License as
54 + * published by the Free Software Foundation's version 2 of
55 + * the License.
56 + *
57 + * This program is distributed in the hope that it will be useful,
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + *
62 + * You should have received a copy of the GNU General Public License
63 + * along with this program; if not, write to the Free Software
64 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
65 + * MA 02111-1307 USA
66 + */
67 +
68 +#include <common.h>
69 +#include <asm/io.h>
70 +#include <asm/arch/dss.h>
71 +
72 +/*
73 + * Configure VENC for a given Mode (NTSC / PAL)
74 + */
75 +void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
76 + u32 height, u32 width)
77 +{
78 + struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
79 + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
80 + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
81 +
82 + writel(venc_cfg->status, &venc->status);
83 + writel(venc_cfg->f_control, &venc->f_control);
84 + writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
85 + writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
86 + writel(venc_cfg->llen, &venc->llen);
87 + writel(venc_cfg->flens, &venc->flens);
88 + writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
89 + writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
90 + writel(venc_cfg->c_phase, &venc->c_phase);
91 + writel(venc_cfg->gain_u, &venc->gain_u);
92 + writel(venc_cfg->gain_v, &venc->gain_v);
93 + writel(venc_cfg->gain_y, &venc->gain_y);
94 + writel(venc_cfg->black_level, &venc->black_level);
95 + writel(venc_cfg->blank_level, &venc->blank_level);
96 + writel(venc_cfg->x_color, &venc->x_color);
97 + writel(venc_cfg->m_control, &venc->m_control);
98 + writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
99 + writel(venc_cfg->s_carr, &venc->s_carr);
100 + writel(venc_cfg->line21, &venc->line21);
101 + writel(venc_cfg->ln_sel, &venc->ln_sel);
102 + writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
103 + writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
104 + writel(venc_cfg->savid__eavid, &venc->savid__eavid);
105 + writel(venc_cfg->flen__fal, &venc->flen__fal);
106 + writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
107 + writel(venc_cfg->hs_int_start_stop_x,
108 + &venc->hs_int_start_stop_x);
109 + writel(venc_cfg->hs_ext_start_stop_x,
110 + &venc->hs_ext_start_stop_x);
111 + writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
112 + writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
113 + &venc->vs_int_stop_x__vs_int_start_y);
114 + writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
115 + &venc->vs_int_stop_y__vs_ext_start_x);
116 + writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
117 + &venc->vs_ext_stop_x__vs_ext_start_y);
118 + writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
119 + writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
120 + writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
121 + writel(venc_cfg->fid_int_start_x__fid_int_start_y,
122 + &venc->fid_int_start_x__fid_int_start_y);
123 + writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
124 + &venc->fid_int_offset_y__fid_ext_start_x);
125 + writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
126 + &venc->fid_ext_start_y__fid_ext_offset_y);
127 + writel(venc_cfg->tvdetgp_int_start_stop_x,
128 + &venc->tvdetgp_int_start_stop_x);
129 + writel(venc_cfg->tvdetgp_int_start_stop_y,
130 + &venc->tvdetgp_int_start_stop_y);
131 + writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
132 + writel(venc_cfg->output_control, &venc->output_control);
133 + writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
134 +
135 + /* Configure DSS for VENC Settings */
136 + writel(VENC_DSS_CONFIG, &dss->control);
137 +
138 + /* Configure height and width for Digital out */
139 + writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
140 +}
141 +
142 +/*
143 + * Configure Panel Specific Parameters
144 + */
145 +void omap3_dss_panel_config(const struct panel_config *panel_cfg)
146 +{
147 + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
148 +
149 + writel(panel_cfg->timing_h, &dispc->timing_h);
150 + writel(panel_cfg->timing_v, &dispc->timing_v);
151 + writel(panel_cfg->pol_freq, &dispc->pol_freq);
152 + writel(panel_cfg->divisor, &dispc->divisor);
153 + writel(panel_cfg->lcd_size, &dispc->size_lcd);
154 + writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
155 + writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
156 + (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
157 + writel(panel_cfg->panel_color, &dispc->default_color0);
158 +}
159 +
160 +/*
161 + * Enable LCD and DIGITAL OUT in DSS
162 + */
163 +void omap3_dss_enable(void)
164 +{
165 + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
166 + u32 l = 0;
167 +
168 + l = readl(&dispc->control);
169 + l |= DISPC_ENABLE;
170 + writel(l, &dispc->control);
171 +}
172 diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h
173 new file mode 100644
174 index 0000000..e5e3b0d
175 --- /dev/null
176 +++ b/include/asm-arm/arch-omap3/dss.h
177 @@ -0,0 +1,173 @@
178 +/*
179 + * (C) Copyright 2010
180 + * Texas Instruments, <www.ti.com>
181 + * Syed Mohammed Khasim <khasim@ti.com>
182 + *
183 + * Referred to Linux DSS driver files for OMAP3
184 + *
185 + * See file CREDITS for list of people who contributed to this
186 + * project.
187 + *
188 + * This program is free software; you can redistribute it and/or
189 + * modify it under the terms of the GNU General Public License as
190 + * published by the Free Software Foundation's version 2 of
191 + * the License.
192 + *
193 + * This program is distributed in the hope that it will be useful,
194 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
195 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196 + * GNU General Public License for more details.
197 + *
198 + * You should have received a copy of the GNU General Public License
199 + * along with this program; if not, write to the Free Software
200 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
201 + * MA 02111-1307 USA
202 + */
203 +
204 +#ifndef DSS_H
205 +#define DSS_H
206 +
207 +/*
208 + * DSS Base Registers
209 + */
210 +#define OMAP3_DSS_BASE 0x48050040
211 +#define OMAP3_DISPC_BASE 0x48050440
212 +#define OMAP3_VENC_BASE 0x48050C00
213 +
214 +/* DSS Registers */
215 +struct dss_regs {
216 + u32 control; /* 0x40 */
217 + u32 sdi_control; /* 0x44 */
218 + u32 pll_control; /* 0x48 */
219 +};
220 +
221 +/* DISPC Registers */
222 +struct dispc_regs {
223 + u32 control; /* 0x40 */
224 + u32 config; /* 0x44 */
225 + u32 reserve_2; /* 0x48 */
226 + u32 default_color0; /* 0x4C */
227 + u32 default_color1; /* 0x50 */
228 + u32 trans_color0; /* 0x54 */
229 + u32 trans_color1; /* 0x58 */
230 + u32 line_status; /* 0x5C */
231 + u32 line_number; /* 0x60 */
232 + u32 timing_h; /* 0x64 */
233 + u32 timing_v; /* 0x68 */
234 + u32 pol_freq; /* 0x6C */
235 + u32 divisor; /* 0x70 */
236 + u32 global_alpha; /* 0x74 */
237 + u32 size_dig; /* 0x78 */
238 + u32 size_lcd; /* 0x7C */
239 +};
240 +
241 +/* VENC Registers */
242 +struct venc_regs {
243 + u32 rev_id; /* 0x00 */
244 + u32 status; /* 0x04 */
245 + u32 f_control; /* 0x08 */
246 + u32 reserve_1; /* 0x0C */
247 + u32 vidout_ctrl; /* 0x10 */
248 + u32 sync_ctrl; /* 0x14 */
249 + u32 reserve_2; /* 0x18 */
250 + u32 llen; /* 0x1C */
251 + u32 flens; /* 0x20 */
252 + u32 hfltr_ctrl; /* 0x24 */
253 + u32 cc_carr_wss_carr; /* 0x28 */
254 + u32 c_phase; /* 0x2C */
255 + u32 gain_u; /* 0x30 */
256 + u32 gain_v; /* 0x34 */
257 + u32 gain_y; /* 0x38 */
258 + u32 black_level; /* 0x3C */
259 + u32 blank_level; /* 0x40 */
260 + u32 x_color; /* 0x44 */
261 + u32 m_control; /* 0x48 */
262 + u32 bstamp_wss_data; /* 0x4C */
263 + u32 s_carr; /* 0x50 */
264 + u32 line21; /* 0x54 */
265 + u32 ln_sel; /* 0x58 */
266 + u32 l21__wc_ctl; /* 0x5C */
267 + u32 htrigger_vtrigger; /* 0x60 */
268 + u32 savid__eavid; /* 0x64 */
269 + u32 flen__fal; /* 0x68 */
270 + u32 lal__phase_reset; /* 0x6C */
271 + u32 hs_int_start_stop_x; /* 0x70 */
272 + u32 hs_ext_start_stop_x; /* 0x74 */
273 + u32 vs_int_start_x; /* 0x78 */
274 + u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
275 + u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
276 + u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
277 + u32 vs_ext_stop_y; /* 0x88 */
278 + u32 reserve_3; /* 0x8C */
279 + u32 avid_start_stop_x; /* 0x90 */
280 + u32 avid_start_stop_y; /* 0x94 */
281 + u32 reserve_4; /* 0x98 */
282 + u32 reserve_5; /* 0x9C */
283 + u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
284 + u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
285 + u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
286 + u32 reserve_6; /* 0xAC */
287 + u32 tvdetgp_int_start_stop_x; /* 0xB0 */
288 + u32 tvdetgp_int_start_stop_y; /* 0xB4 */
289 + u32 gen_ctrl; /* 0xB8 */
290 + u32 reserve_7; /* 0xBC */
291 + u32 reserve_8; /* 0xC0 */
292 + u32 output_control; /* 0xC4 */
293 + u32 dac_b__dac_c; /* 0xC8 */
294 + u32 height_width; /* 0xCC */
295 +};
296 +
297 +/* Few Register Offsets */
298 +#define FRAME_MODE_SHIFT 1
299 +#define TFTSTN_SHIFT 3
300 +#define DATALINES_SHIFT 8
301 +
302 +/* Enabling Display controller */
303 +#define LCD_ENABLE 1
304 +#define DIG_ENABLE (1 << 1)
305 +#define GO_LCD (1 << 5)
306 +#define GO_DIG (1 << 6)
307 +#define GP_OUT0 (1 << 15)
308 +#define GP_OUT1 (1 << 16)
309 +
310 +#define DISPC_ENABLE (LCD_ENABLE | \
311 + DIG_ENABLE | \
312 + GO_LCD | \
313 + GO_DIG | \
314 + GP_OUT0| \
315 + GP_OUT1)
316 +
317 +/* Configure VENC DSS Params */
318 +#define VENC_CLK_ENABLE (1 << 3)
319 +#define DAC_DEMEN (1 << 4)
320 +#define DAC_POWERDN (1 << 5)
321 +#define VENC_OUT_SEL (1 << 6)
322 +#define DIG_LPP_SHIFT 16
323 +#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
324 + DAC_DEMEN | \
325 + DAC_POWERDN | \
326 + VENC_OUT_SEL)
327 +/*
328 + * Panel Configuration
329 + */
330 +struct panel_config {
331 + u32 timing_h;
332 + u32 timing_v;
333 + u32 pol_freq;
334 + u32 divisor;
335 + u32 lcd_size;
336 + u32 panel_type;
337 + u32 data_lines;
338 + u32 load_mode;
339 + u32 panel_color;
340 +};
341 +
342 +/*
343 + * Generic DSS Functions
344 + */
345 +void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
346 + u32 height, u32 width);
347 +void omap3_dss_panel_config(const struct panel_config *panel_cfg);
348 +void omap3_dss_enable(void);
349 +
350 +#endif /* DSS_H */
351 --
352 1.6.6.1