recipes-bsp/x-load/x-load-git/xm-mem.patch

   1 From a25b926ff963a1866e26b11a4dac742564618375 Mon Sep 17 00:00:00 2001
   2 From: Steve Kipisz <s-kipisz2@ti.com>
   3 Date: Thu, 8 Jul 2010 10:30:58 -0500
   4 Subject: [PATCH] Support Micron or Numonyx memory
   5
   6 * Updated Numonyx memory size.
   7 ---
   8  board/omap3530beagle/omap3530beagle.c |   56 +++++++++++++++++++++++++++-----
   9  drivers/k9f1g08r0a.c                  |   43 +++++++++++++++++++------
  10  include/asm/arch-omap3/mem.h          |   43 ++++++++++++++++++++++++-
  11  3 files changed, 121 insertions(+), 21 deletions(-)
  12
  13 diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
  14 index eb8008e..1b3d8c7 100644
  15 --- a/board/omap3530beagle/omap3530beagle.c
  16 +++ b/board/omap3530beagle/omap3530beagle.c
  17 @@ -265,6 +265,32 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
  18  }
  19
  20  #ifdef CFG_3430SDRAM_DDR
  21 +
  22 +#define MICRON_DDR     0
  23 +#define NUMONYX_MCP    1
  24 +int identify_xm_ddr()
  25 +{
  26 +       int     mfr, id;
  27 +
  28 +       __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
  29 +       __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
  30 +       __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
  31 +       __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
  32 +       __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
  33 +       __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
  34 +
  35 +       /* Enable the GPMC Mapping */
  36 +       __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
  37 +                            ((NAND_BASE_ADR>>24) & 0x3F) |
  38 +                            (1<<6)),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
  39 +       delay(2000);
  40 +
  41 +       nand_readid(&mfr, &id);
  42 +       if (mfr == 0)
  43 +               return MICRON_DDR;
  44 +       if ((mfr == 0x20) && (id == 0xba))
  45 +               return NUMONYX_MCP;
  46 +}
  47  /*********************************************************************
  48   * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
  49   *********************************************************************/
  50 @@ -279,15 +305,27 @@ void config_3430sdram_ddr(void)
  51         __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
  52
  53         if (beagle_revision() == REVISION_XM) {
  54 -               __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
  55 -               __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_0);
  56 -               __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_1);
  57 -               __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
  58 -               __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
  59 -               __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
  60 -               __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
  61 -               __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
  62 -               __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
  63 +               if (identify_xm_ddr() == MICRON_DDR) {
  64 +                       __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
  65 +                       __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
  66 +                       __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
  67 +                       __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
  68 +                       __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
  69 +                       __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
  70 +                       __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
  71 +                       __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
  72 +                       __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
  73 +               } else {
  74 +                       __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
  75 +                       __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
  76 +                       __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
  77 +                       __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
  78 +                       __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
  79 +                       __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
  80 +                       __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
  81 +                       __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
  82 +                       __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
  83 +               }
  84         } else {
  85                 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
  86                 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
  87 diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
  88 index 8968a1b..d2da804 100644
  89 --- a/drivers/k9f1g08r0a.c
  90 +++ b/drivers/k9f1g08r0a.c
  91 @@ -154,6 +154,29 @@ static int NanD_Address(unsigned int numbytes, unsigned long ofs)
  92         return 0;
  93  }
  94
  95 +int nand_readid(int *mfr, int *id)
  96 +{
  97 +       NAND_ENABLE_CE();
  98 +
  99 +       if (NanD_Command(NAND_CMD_RESET)) {
 100 +               NAND_DISABLE_CE();
 101 +               return 1;
 102 +       }
 103 +
 104 +       if (NanD_Command(NAND_CMD_READID)) {
 105 +               NAND_DISABLE_CE();
 106 +               return 1;
 107 +       }
 108 +
 109 +       NanD_Address(ADDR_COLUMN, 0);
 110 +
 111 +       *mfr = READ_NAND(NAND_ADDR);
 112 +       *id = READ_NAND(NAND_ADDR);
 113 +
 114 +       NAND_DISABLE_CE();
 115 +       return 0;
 116 +}
 117 +
 118  /* read chip mfr and id
 119   * return 0 if they match board config
 120   * return 1 if not
 121 @@ -162,23 +185,23 @@ int nand_chip()
 122  {
 123         int mfr, id;
 124
 125 -       NAND_ENABLE_CE();
 126 +       NAND_ENABLE_CE();
 127
 128 -       if (NanD_Command(NAND_CMD_RESET)) {
 129 -               printf("Err: RESET\n");
 130 -               NAND_DISABLE_CE();
 131 +       if (NanD_Command(NAND_CMD_RESET)) {
 132 +               printf("Err: RESET\n");
 133 +               NAND_DISABLE_CE();
 134                 return 1;
 135         }
 136
 137 -       if (NanD_Command(NAND_CMD_READID)) {
 138 -               printf("Err: READID\n");
 139 -               NAND_DISABLE_CE();
 140 +       if (NanD_Command(NAND_CMD_READID)) {
 141 +               printf("Err: READID\n");
 142 +               NAND_DISABLE_CE();
 143                 return 1;
 144 -       }
 145 +       }
 146
 147 -       NanD_Address(ADDR_COLUMN, 0);
 148 +       NanD_Address(ADDR_COLUMN, 0);
 149
 150 -       mfr = READ_NAND(NAND_ADDR);
 151 +       mfr = READ_NAND(NAND_ADDR);
 152         id = READ_NAND(NAND_ADDR);
 153
 154         NAND_DISABLE_CE();
 155 diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
 156 index cba4c6f..63cdba1 100644
 157 --- a/include/asm/arch-omap3/mem.h
 158 +++ b/include/asm/arch-omap3/mem.h
 159 @@ -46,6 +46,7 @@ typedef enum {
 160  #define MMC_NAND            4
 161  #define MMC_ONENAND         5
 162  #define GPMC_NONE           6
 163 +#define GPMC_ONENAND_TRY    7
 164
 165  #endif
 166
 167 @@ -71,7 +72,8 @@ typedef enum {
 168  #define SDP_SDRC_MDCFG_0_DDR   (0x02582019|B_ALL) /* Infin ddr module */
 169  #else
 170  #define SDP_SDRC_MDCFG_0_DDR   (0x02584019|B_ALL)
 171 -#define SDP_SDRC_MDCFG_0_DDR_XM        (0x03588019|B_ALL)
 172 +#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
 173 +#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM        (0x04590019|B_ALL)
 174  #endif
 175
 176  #define SDP_SDRC_MR_0_DDR              0x00000032
 177 @@ -252,12 +254,47 @@ typedef enum {
 178                 (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
 179
 180  #define MICRON_TWTR_200   2
 181 -#define MICRON_TCKE_200   1
 182 +#define MICRON_TCKE_200   4
 183  #define MICRON_TXP_200    2
 184  #define MICRON_XSR_200   23
 185  #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
 186                                 (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
 187
 188 +/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
 189 + *   ACTIMA
 190 + *      TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
 191 + *      TDPL (Twr) = 15/6 = 2.5 -> 3
 192 + *      TRRD = 12/6 = 2
 193 + *      TRCD = 22.5/6 = 3.75 -> 4
 194 + *      TRP  = 18/6 = 3
 195 + *      TRAS = 42/6 = 7
 196 + *      TRC  = 60/6 = 10
 197 + *      TRFC = 140/6 = 23.3 -> 24
 198 + *   ACTIMB
 199 + *     TWTR = 2
 200 + *     TCKE = 2
 201 + *     TXSR = 200/6 =  33.3 -> 34
 202 + *     TXP  = 1.0 + 1.1 = 2.1 -> 3 ¿?
 203 + */
 204 +#define NUMONYX_TDAL_165   6
 205 +#define NUMONYX_TDPL_165   3
 206 +#define NUMONYX_TRRD_165   2
 207 +#define NUMONYX_TRCD_165   4
 208 +#define NUMONYX_TRP_165    3
 209 +#define NUMONYX_TRAS_165   7
 210 +#define NUMONYX_TRC_165   10
 211 +#define NUMONYX_TRFC_165  24
 212 +#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
 213 +               | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
 214 +               (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
 215 +
 216 +#define NUMONYX_TWTR_165   2
 217 +#define NUMONYX_TCKE_165   2
 218 +#define NUMONYX_TXP_165    3
 219 +#define NUMONYX_XSR_165    34
 220 +#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
 221 +                               (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
 222 +
 223  /* New and compatability speed defines */
 224  #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
 225  # define L3_100MHZ   /* Use with <= 100MHz SDRAM */
 226 @@ -276,6 +313,8 @@ typedef enum {
 227  #elif  defined(L3_165MHZ)
 228  # define MICRON_SDRC_ACTIM_CTRLA_0     MICRON_V_ACTIMA_165
 229  # define MICRON_SDRC_ACTIM_CTRLB_0     MICRON_V_ACTIMB_165
 230 +# define NUMONYX_SDRC_ACTIM_CTRLA_0    NUMONYX_V_ACTIMA_165
 231 +# define NUMONYX_SDRC_ACTIM_CTRLB_0    NUMONYX_V_ACTIMB_165
 232  #endif
 233
 234
 235 --
 236 1.6.1
 237