[glsdk/meta-ti-glsdk.git] / recipes-bsp / x-load / x-load / 0001-OMAP4-clocks-Enable-only-required-clks.patch
1 From 7c5a2dd1e20702d220bd75910f7cfb6141230e5b Mon Sep 17 00:00:00 2001
2 From: Rajendra Nayak <rnayak@ti.com>
3 Date: Tue, 21 Dec 2010 11:55:01 -0200
4 Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks
6 X-loader untill now, was enabling all clks at bootup
7 to help all modules to be functional at the kernel, even
8 with drivers which do not handle clks well.
9 Now that we are moving towards all drivers being adapted
10 to request/release clks as expected, most of this code is
11 useless and hence removed.
13 Signed-off-by: Rajendra Nayak <rnayak@ti.com>
14 Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
15 ---
16 board/omap4430panda/clock.c | 225 ++++++++++++++++++++++---------------------
17 1 files changed, 117 insertions(+), 108 deletions(-)
19 diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
20 index a83f1c6..b323885 100644
21 --- a/board/omap4430panda/clock.c
22 +++ b/board/omap4430panda/clock.c
23 @@ -552,71 +552,73 @@ static void enable_all_clocks(void)
24 {
25 volatile int regvalue = 0;
27 - /* Enable Ducati clocks */
28 - sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
29 - sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
30 -
31 - wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
32 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
33 -
34 - /* Enable ivahd and sl2 clocks */
35 - sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
36 - sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
37 - sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
38 -
39 - wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
40 -
41 - /* wait for ivahd to become accessible */
42 - //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
43 - /* wait for sl2 to become accessible */
44 - //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
45 -
46 - /* Enable Tesla clocks */
47 - sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
48 - sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
49 -
50 - wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
51 -
52 - /* wait for tesla to become accessible */
53 - //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
54 -
55 - /* TODO: Some hack needed by MM: Clean this */
56 - #if 0 /* Doesn't work on some Zebu */
57 - *(volatile int*)0x4a306910 = 0x00000003;
58 - *(volatile int*)0x550809a0 = 0x00000001;
59 - *(volatile int*)0x55080a20 = 0x00000007;
60 - #endif
61 -
62 - /* ABE clocks */
63 - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
64 - sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
65 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
66 - sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
67 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
68 - sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
69 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
70 - sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
71 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
72 - sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
73 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
74 - sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
75 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
76 - sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
77 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
78 - sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
79 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
80 - sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
81 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
82 - sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
83 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
84 - sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
85 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
86 - sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
87 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
88 - sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
89 - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
90 - /* Disable sleep transitions */
91 - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
92 + if (omap_revision() == OMAP4430_ES1_0) {
93 + /* Enable Ducati clocks */
94 + sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
95 + sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
96 +
97 + wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
98 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
99 +
100 + /* Enable ivahd and sl2 clocks */
101 + sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
102 + sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
103 + sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
104 +
105 + wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
106 +
107 + /* wait for ivahd to become accessible */
108 + //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
109 + /* wait for sl2 to become accessible */
110 + //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
111 +
112 + /* Enable Tesla clocks */
113 + sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
114 + sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
115 +
116 + wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
117 +
118 + /* wait for tesla to become accessible */
119 + //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
120 +
121 + /* TODO: Some hack needed by MM: Clean this */
122 + #if 0 /* Doesn't work on some Zebu */
123 + *(volatile int*)0x4a306910 = 0x00000003;
124 + *(volatile int*)0x550809a0 = 0x00000001;
125 + *(volatile int*)0x55080a20 = 0x00000007;
126 + #endif
127 +
128 + /* ABE clocks */
129 + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
130 + sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
131 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
132 + sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
133 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
134 + sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
135 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
136 + sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
137 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
138 + sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
139 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
140 + sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
141 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
142 + sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
143 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
144 + sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
145 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
146 + sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
147 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
148 + sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
149 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
150 + sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
151 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
152 + sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
153 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
154 + sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
155 + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
156 + /* Disable sleep transitions */
157 + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
158 + }
160 /* L4PER clocks */
161 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
162 @@ -723,50 +725,57 @@ static void enable_all_clocks(void)
163 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
164 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
166 - /* Enable Camera clocks */
167 - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
168 - sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
169 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
170 - sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
171 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
172 - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
173 -
174 - /* Enable DSS clocks */
175 - /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
176 - *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
177 - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
178 - sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
179 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
180 - sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
181 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
182 - /* Check for DSS Clocks */
183 - while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
184 - /* Set HW_AUTO transition mode */
185 - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
186 -
187 - /* Enable SGX clocks */
188 - sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
189 - sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
190 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
191 - /* Check for SGX FCLK and ICLK */
192 - while ( (*(volatile int*)0x4A009200) != 0x302 );
193 - //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
194 - /* Enable hsi/unipro/usb clocks */
195 - sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
196 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
197 - sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
198 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
199 - sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
200 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
201 - sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
202 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
203 - sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
204 - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
205 - sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
206 - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
207 - /* enable the 32K, 48M optional clocks and enable the module */
208 + if (omap_revision() == OMAP4430_ES1_0) {
209 + /* Enable Camera clocks */
210 + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
211 + sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
212 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
213 + sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
214 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
215 + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
216 +
217 + /* Enable DSS clocks */
218 + /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
219 + *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
220 + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
221 + sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
222 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
223 + sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
224 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
225 + /* Check for DSS Clocks */
226 + while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
227 + /* Set HW_AUTO transition mode */
228 + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
229 +
230 + /* Enable SGX clocks */
231 + sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
232 + sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
233 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
234 + /* Check for SGX FCLK and ICLK */
235 + while ( (*(volatile int*)0x4A009200) != 0x302 );
236 + //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
237 + /* Enable hsi/unipro/usb clocks */
238 + sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
239 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
240 + sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
241 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
242 + sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
243 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
244 + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
245 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
246 + sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
247 + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
248 + sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
249 + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
250 + /* enable the 32K, 48M optional clocks and enable the module */
251 + sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
252 + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
253 + }
254 +
255 + /* Enable clocks for USB fast boot to work */
256 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
257 - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
258 + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
259 +
260 return;
261 }
263 --
264 1.6.6.1