recipes-bsp/x-load/x-load/panda-frefclk.patch

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  49 From: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
  50 To: x-loader@googlegroups.com
  51 Cc: patches@linaro.org,
  52         Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
  53 Subject: [x-loader] [PATCH v2] omap4: pandaboard: ehci fref_clkout per board revision
  54 Date: Mon, 11 Jul 2011 04:39:17 -0300
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  76
  77 Add support for correctly configuring the fref_clkout depending on the
  78 board revision of the pandaboard. This patch is necessary to make u-boot
  79 work with the smsc usb+ethernet driver.
  80
  81 Tested USB+Eth with TFTP and PXE using linaro u-boot:
  82 http://git.linaro.org/gitweb?p=boot/u-boot-linaro-stable.git;a=summary
  83
  84 Based on patch from David Anders <x0132446@ti.com> from
  85 omap4_panda_L24.9 branch at gitorious.org/pandaboard x-loader tree.
  86
  87 Changes since v1:
  88  * Moving the code from s_init instead of adding a new block
  89
  90 Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
  91 ---
  92  board/omap4430panda/omap4430panda.c |   58 +++++++++++++++-------------------
  93  1 files changed, 26 insertions(+), 32 deletions(-)
  94
  95 diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
  96 index 9b4e457..bcee6fe 100644
  97 --- a/board/omap4430panda/omap4430panda.c
  98 +++ b/board/omap4430panda/omap4430panda.c
  99 @@ -531,6 +531,7 @@ static void ddr_init(void)
 100   *****************************************/
 101  int board_init(void)
 102  {
 103 +       unsigned int rev = omap_revision();
 104         unsigned int v;
 105
 106         /*
 107 @@ -546,10 +547,32 @@ int board_init(void)
 108         v = __raw_readl(OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
 109         __raw_writel((v & ~(1 << 30)), OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
 110
 111 -       /* kill USB PLL */
 112 +       if (rev == OMAP4430_ES1_0)
 113 +               return 0;
 114
 115 -       v = __raw_readl(CM_CLKMODE_DPLL_USB);
 116 -       __raw_writel((v & ~7) | 1, CM_CLKMODE_DPLL_USB);
 117 +       if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
 118 +               /* enable software ioreq */
 119 +               sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
 120 +               /* set for sys_clk (38.4MHz) */
 121 +               sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
 122 +               /* set divisor to 2 */
 123 +               sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
 124 +               /* set the clock source to active */
 125 +               sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
 126 +               /* enable clocks */
 127 +               sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 128 +       } else {
 129 +               /* enable software ioreq */
 130 +               sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
 131 +               /* set for PER_DPLL */
 132 +               sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
 133 +               /* set divisor to 16 */
 134 +               sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
 135 +               /* set the clock source to active */
 136 +               sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
 137 +               /* enable clocks */
 138 +               sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 139 +       }
 140
 141         return 0;
 142  }
 143 @@ -683,8 +706,6 @@ static int scale_vcores(void)
 144
 145  void s_init(void)
 146  {
 147 -       unsigned int rev = omap_revision();
 148 -
 149         /*
 150          * this is required to survive the muxconf in the case the ROM
 151          * started up USB OTG
 152 @@ -707,33 +728,6 @@ void s_init(void)
 153         /* setup_auxcr(get_device_type(), external_boot); */
 154
 155         ddr_init();
 156 -
 157 -       if (rev == OMAP4430_ES1_0)
 158 -               return;
 159 -
 160 -       if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
 161 -               /* enable software ioreq */
 162 -               sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
 163 -               /* set for sys_clk (38.4MHz) */
 164 -               sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
 165 -               /* set divisor to 2 */
 166 -               sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
 167 -               /* set the clock source to active */
 168 -               sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
 169 -               /* enable clocks */
 170 -               sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 171 -       } else {
 172 -               /* enable software ioreq */
 173 -               sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
 174 -               /* set for PER_DPLL */
 175 -               sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
 176 -               /* set divisor to 16 */
 177 -               sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
 178 -               /* set the clock source to active */
 179 -               sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
 180 -               /* enable clocks */
 181 -               sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 182 -       }
 183  }
 184
 185  /*******************************************************
 186 --
 187 1.7.4.1
 188
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