678a7b46d0a8bd6350b42a9a4b62915689bfb1a1
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-3.0 / pm-wip / voltdm / 0056-OMAP4-prcm_mpu-Fix-indent-in-few-macros.patch
1 From 3685b19f9ee67549df2323a5203c1e5a639c3883 Mon Sep 17 00:00:00 2001
2 From: Benoit Cousson <b-cousson@ti.com>
3 Date: Sat, 9 Jul 2011 19:15:06 -0600
4 Subject: [PATCH 056/149] OMAP4: prcm_mpu: Fix indent in few macros
6 Some maros were not well aligned. Re-align them.
8 Signed-off-by: Benoit Cousson <b-cousson@ti.com>
9 Cc: Paul Walmsley <paul@pwsan.com>
10 Cc: Rajendra Nayak <rnayak@ti.com>
11 Signed-off-by: Paul Walmsley <paul@pwsan.com>
12 ---
13 arch/arm/mach-omap2/prcm_mpu44xx.h | 69 +++++++++++++++++------------------
14 1 files changed, 34 insertions(+), 35 deletions(-)
16 diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
17 index d22d1b4..8a6e250 100644
18 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h
19 +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
20 @@ -31,7 +31,6 @@
21 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
23 /* PRCM_MPU instances */
24 -
25 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
26 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
27 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
28 @@ -52,46 +51,46 @@
29 */
31 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
32 -#define OMAP4_REVISION_PRCM_OFFSET 0x0000
33 -#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
34 +#define OMAP4_REVISION_PRCM_OFFSET 0x0000
35 +#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
37 /* PRCM_MPU.DEVICE_PRM register offsets */
38 -#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
39 -#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
40 -#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
41 -#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
42 +#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
43 +#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
44 +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
45 +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
47 /* PRCM_MPU.CPU0 register offsets */
48 -#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
49 -#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
50 -#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
51 -#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
52 -#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
53 -#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
54 -#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
55 -#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
56 -#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
57 -#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
58 -#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
59 -#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
60 -#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
61 -#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
62 +#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
63 +#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
64 +#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
65 +#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
66 +#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
67 +#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
68 +#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
69 +#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
70 +#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
71 +#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
72 +#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
73 +#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
74 +#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
75 +#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
77 /* PRCM_MPU.CPU1 register offsets */
78 -#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
79 -#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
80 -#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
81 -#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
82 -#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
83 -#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
84 -#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
85 -#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
86 -#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
87 -#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
88 -#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
89 -#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
90 -#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
91 -#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
92 +#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
93 +#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
94 +#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
95 +#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
96 +#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
97 +#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
98 +#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
99 +#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
100 +#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
101 +#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
102 +#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
103 +#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
104 +#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
105 +#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
107 /* Function prototypes */
108 # ifndef __ASSEMBLER__
109 --
110 1.6.6.1