8af2155fbb4de3b68e821f598a70ff50cbfb9f80
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-3.0 / pm-wip / voltdm / 0060-OMAP4-clock-data-Remove-McASP2-McASP3-and-MMC6-clock.patch
1 From a5224876877da3dce7971e82d89a58d58f4917fb Mon Sep 17 00:00:00 2001
2 From: Jon Hunter <jon-hunter@ti.com>
3 Date: Sat, 9 Jul 2011 19:14:47 -0600
4 Subject: [PATCH 060/149] OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocks
6 McASP2, 3 and MMC6 modules are not present in the OMAP4 family.
7 Remove the fclk and the clksel related to these nodes.
8 Rename the references that were potentially re-used in order nodes.
10 Remove related macros in prcm header files.
12 Update TI copyright date.
14 Signed-off-by: Jon Hunter <jon-hunter@ti.com>
15 [b-cousson@ti.com: Update the patch according to autogen output]
16 Signed-off-by: Benoit Cousson <b-cousson@ti.com>
17 [paul@pwsan.com: split PRCM data changes into a separate patch]
18 Signed-off-by: Paul Walmsley <paul@pwsan.com>
19 ---
20 arch/arm/mach-omap2/clock44xx_data.c | 86 ++++++++++++---------------------
21 1 files changed, 31 insertions(+), 55 deletions(-)
23 diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
24 index 8307c9e..96bc668 100644
25 --- a/arch/arm/mach-omap2/clock44xx_data.c
26 +++ b/arch/arm/mach-omap2/clock44xx_data.c
27 @@ -1170,19 +1170,6 @@ static struct clk func_96m_fclk = {
28 .set_rate = &omap2_clksel_set_rate,
29 };
31 -static const struct clksel hsmmc6_fclk_sel[] = {
32 - { .parent = &func_64m_fclk, .rates = div_1_0_rates },
33 - { .parent = &func_96m_fclk, .rates = div_1_1_rates },
34 - { .parent = NULL },
35 -};
36 -
37 -static struct clk hsmmc6_fclk = {
38 - .name = "hsmmc6_fclk",
39 - .parent = &func_64m_fclk,
40 - .ops = &clkops_null,
41 - .recalc = &followparent_recalc,
42 -};
43 -
44 static const struct clksel_rate div2_1to8_rates[] = {
45 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
46 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
47 @@ -1265,6 +1252,21 @@ static struct clk l4_wkup_clk_mux_ck = {
48 .recalc = &omap2_clksel_recalc,
49 };
51 +static struct clk ocp_abe_iclk = {
52 + .name = "ocp_abe_iclk",
53 + .parent = &aess_fclk,
54 + .ops = &clkops_null,
55 + .recalc = &followparent_recalc,
56 +};
57 +
58 +static struct clk per_abe_24m_fclk = {
59 + .name = "per_abe_24m_fclk",
60 + .parent = &dpll_abe_m2_ck,
61 + .ops = &clkops_null,
62 + .fixed_div = 4,
63 + .recalc = &omap_fixed_divisor_recalc,
64 +};
65 +
66 static const struct clksel per_abe_nc_fclk_div[] = {
67 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
68 { .parent = NULL },
69 @@ -1282,41 +1284,6 @@ static struct clk per_abe_nc_fclk = {
70 .set_rate = &omap2_clksel_set_rate,
71 };
73 -static const struct clksel mcasp2_fclk_sel[] = {
74 - { .parent = &func_96m_fclk, .rates = div_1_0_rates },
75 - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
76 - { .parent = NULL },
77 -};
78 -
79 -static struct clk mcasp2_fclk = {
80 - .name = "mcasp2_fclk",
81 - .parent = &func_96m_fclk,
82 - .ops = &clkops_null,
83 - .recalc = &followparent_recalc,
84 -};
85 -
86 -static struct clk mcasp3_fclk = {
87 - .name = "mcasp3_fclk",
88 - .parent = &func_96m_fclk,
89 - .ops = &clkops_null,
90 - .recalc = &followparent_recalc,
91 -};
92 -
93 -static struct clk ocp_abe_iclk = {
94 - .name = "ocp_abe_iclk",
95 - .parent = &aess_fclk,
96 - .ops = &clkops_null,
97 - .recalc = &followparent_recalc,
98 -};
99 -
100 -static struct clk per_abe_24m_fclk = {
101 - .name = "per_abe_24m_fclk",
102 - .parent = &dpll_abe_m2_ck,
103 - .ops = &clkops_null,
104 - .fixed_div = 4,
105 - .recalc = &omap_fixed_divisor_recalc,
106 -};
107 -
108 static const struct clksel pmd_stm_clock_mux_sel[] = {
109 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
110 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
111 @@ -1996,10 +1963,16 @@ static struct clk mcbsp3_fck = {
112 .clkdm_name = "abe_clkdm",
113 };
115 +static const struct clksel mcbsp4_sync_mux_sel[] = {
116 + { .parent = &func_96m_fclk, .rates = div_1_0_rates },
117 + { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
118 + { .parent = NULL },
119 +};
120 +
121 static struct clk mcbsp4_sync_mux_ck = {
122 .name = "mcbsp4_sync_mux_ck",
123 .parent = &func_96m_fclk,
124 - .clksel = mcasp2_fclk_sel,
125 + .clksel = mcbsp4_sync_mux_sel,
126 .init = &omap2_init_clksel_parent,
127 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
128 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
129 @@ -2078,11 +2051,17 @@ static struct clk mcspi4_fck = {
130 .recalc = &followparent_recalc,
131 };
133 +static const struct clksel hsmmc1_fclk_sel[] = {
134 + { .parent = &func_64m_fclk, .rates = div_1_0_rates },
135 + { .parent = &func_96m_fclk, .rates = div_1_1_rates },
136 + { .parent = NULL },
137 +};
138 +
139 /* Merged hsmmc1_fclk into mmc1 */
140 static struct clk mmc1_fck = {
141 .name = "mmc1_fck",
142 .parent = &func_64m_fclk,
143 - .clksel = hsmmc6_fclk_sel,
144 + .clksel = hsmmc1_fclk_sel,
145 .init = &omap2_init_clksel_parent,
146 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
147 .clksel_mask = OMAP4430_CLKSEL_MASK,
148 @@ -2097,7 +2076,7 @@ static struct clk mmc1_fck = {
149 static struct clk mmc2_fck = {
150 .name = "mmc2_fck",
151 .parent = &func_64m_fclk,
152 - .clksel = hsmmc6_fclk_sel,
153 + .clksel = hsmmc1_fclk_sel,
154 .init = &omap2_init_clksel_parent,
155 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
156 .clksel_mask = OMAP4430_CLKSEL_MASK,
157 @@ -3094,17 +3073,14 @@ static struct omap_clk omap44xx_clks[] = {
158 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
159 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
160 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
161 - CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
162 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
163 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
164 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
165 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
166 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
167 - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
168 - CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
169 - CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
170 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
171 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
172 + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
173 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
174 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
175 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
176 --
177 1.6.6.1