[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-3.0 / pm-wip / voltdm / 0074-OMAP-hwmod-fix-the-i2c-reset-timeout-during-bootup.patch
1 From 6cfe2201f98f68d21eecddaefed716e9803734c5 Mon Sep 17 00:00:00 2001
2 From: Avinash.H.M <avinashhm@ti.com>
3 Date: Sun, 10 Jul 2011 05:27:16 -0600
4 Subject: [PATCH 074/149] OMAP: hwmod: fix the i2c-reset timeout during bootup
6 The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
7 special sequence to reset the module. The sequence is
8 - Disable the I2C.
9 - Write to SOFTRESET bit.
10 - Enable the I2C.
11 - Poll on the RESETDONE bit.
12 The sequence is implemented as a function and the i2c_class is updated with
13 the correct 'reset' pointer. omap_hwmod_softreset function is implemented
14 which triggers the softreset by writing into sysconfig register. On following
15 this sequence, i2c module resets properly and timeouts are not seen.
17 Cc: Rajendra Nayak <rnayak@ti.com>
18 Cc: Paul Walmsley <paul@pwsan.com>
19 Cc: Benoit Cousson <b-cousson@ti.com>
20 Cc: Kevin Hilman <khilman@ti.com>
21 Signed-off-by: Avinash.H.M <avinashhm@ti.com>
22 [paul@pwsan.com: combined this patch with a patch to remove
23 HWMOD_INIT_NO_RESET from the 44xx hwmod flags; change register
24 offset conditional code to use the IP block revision; minor code
25 cleanup]
26 Signed-off-by: Paul Walmsley <paul@pwsan.com>
27 ---
28 arch/arm/mach-omap2/i2c.c | 68 ++++++++++++++++++++++++++
29 arch/arm/mach-omap2/omap_hwmod.c | 27 ++++++++++
30 arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
31 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
32 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 7 ++-
33 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 ++--
34 arch/arm/plat-omap/include/plat/i2c.h | 3 +
35 arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
36 8 files changed, 111 insertions(+), 7 deletions(-)
38 diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
39 index 79c478c..ace9994 100644
40 --- a/arch/arm/mach-omap2/i2c.c
41 +++ b/arch/arm/mach-omap2/i2c.c
42 @@ -21,9 +21,19 @@
44 #include <plat/cpu.h>
45 #include <plat/i2c.h>
46 +#include <plat/common.h>
47 +#include <plat/omap_hwmod.h>
49 #include "mux.h"
51 +/* In register I2C_CON, Bit 15 is the I2C enable bit */
52 +#define I2C_EN BIT(15)
53 +#define OMAP2_I2C_CON_OFFSET 0x24
54 +#define OMAP4_I2C_CON_OFFSET 0xA4
55 +
56 +/* Maximum microseconds to wait for OMAP module to softreset */
57 +#define MAX_MODULE_SOFTRESET_WAIT 10000
58 +
59 void __init omap2_i2c_mux_pins(int bus_id)
60 {
61 char mux_name[sizeof("i2c2_scl.i2c2_scl")];
62 @@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
63 sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
64 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
65 }
66 +
67 +/**
68 + * omap_i2c_reset - reset the omap i2c module.
69 + * @oh: struct omap_hwmod *
70 + *
71 + * The i2c moudle in omap2, omap3 had a special sequence to reset. The
72 + * sequence is:
73 + * - Disable the I2C.
74 + * - Write to SOFTRESET bit.
75 + * - Enable the I2C.
76 + * - Poll on the RESETDONE bit.
77 + * The sequence is implemented in below function. This is called for 2420,
78 + * 2430 and omap3.
79 + */
80 +int omap_i2c_reset(struct omap_hwmod *oh)
81 +{
82 + u32 v;
83 + u16 i2c_con;
84 + int c = 0;
85 +
86 + if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
87 + i2c_con = OMAP4_I2C_CON_OFFSET;
88 + } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
89 + i2c_con = OMAP2_I2C_CON_OFFSET;
90 + } else {
91 + WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
92 + oh->name);
93 + return -EINVAL;
94 + }
95 +
96 + /* Disable I2C */
97 + v = omap_hwmod_read(oh, i2c_con);
98 + v &= ~I2C_EN;
99 + omap_hwmod_write(v, oh, i2c_con);
100 +
101 + /* Write to the SOFTRESET bit */
102 + omap_hwmod_softreset(oh);
103 +
104 + /* Enable I2C */
105 + v = omap_hwmod_read(oh, i2c_con);
106 + v |= I2C_EN;
107 + omap_hwmod_write(v, oh, i2c_con);
108 +
109 + /* Poll on RESETDONE bit */
110 + omap_test_timeout((omap_hwmod_read(oh,
111 + oh->class->sysc->syss_offs)
112 + & SYSS_RESETDONE_MASK),
113 + MAX_MODULE_SOFTRESET_WAIT, c);
114 +
115 + if (c == MAX_MODULE_SOFTRESET_WAIT)
116 + pr_warning("%s: %s: softreset failed (waited %d usec)\n",
117 + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
118 + else
119 + pr_debug("%s: %s: softreset in %d usec\n", __func__,
120 + oh->name, c);
121 +
122 + return 0;
123 +}
124 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
125 index 7d242c9..02b6016 100644
126 --- a/arch/arm/mach-omap2/omap_hwmod.c
127 +++ b/arch/arm/mach-omap2/omap_hwmod.c
128 @@ -1656,6 +1656,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
129 }
131 /**
132 + * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
133 + * @oh: struct omap_hwmod *
134 + *
135 + * This is a public function exposed to drivers. Some drivers may need to do
136 + * some settings before and after resetting the device. Those drivers after
137 + * doing the necessary settings could use this function to start a reset by
138 + * setting the SYSCONFIG.SOFTRESET bit.
139 + */
140 +int omap_hwmod_softreset(struct omap_hwmod *oh)
141 +{
142 + u32 v;
143 + int ret;
144 +
145 + if (!oh || !(oh->_sysc_cache))
146 + return -EINVAL;
147 +
148 + v = oh->_sysc_cache;
149 + ret = _set_softreset(oh, &v);
150 + if (ret)
151 + goto error;
152 + _write_sysconfig(v, oh);
153 +
154 +error:
155 + return ret;
156 +}
157 +
158 +/**
159 * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
160 * @oh: struct omap_hwmod *
161 * @idlemode: SIDLEMODE field bits (shifted to bit 0)
162 diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
163 index 7af2514..a015c69 100644
164 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
165 +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
166 @@ -1030,6 +1030,7 @@ static struct omap_hwmod_class i2c_class = {
167 .name = "i2c",
168 .sysc = &i2c_sysc,
169 .rev = OMAP_I2C_IP_VERSION_1,
170 + .reset = &omap_i2c_reset,
171 };
173 static struct omap_i2c_dev_attr i2c_dev_attr = {
174 diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
175 index 405688a..16743c7 100644
176 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
177 +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
178 @@ -1079,6 +1079,7 @@ static struct omap_hwmod_class i2c_class = {
179 .name = "i2c",
180 .sysc = &i2c_sysc,
181 .rev = OMAP_I2C_IP_VERSION_1,
182 + .reset = &omap_i2c_reset,
183 };
185 static struct omap_i2c_dev_attr i2c_dev_attr = {
186 diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
187 index c704ac8..25bf43b 100644
188 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
189 +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
190 @@ -1306,9 +1306,10 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
191 };
193 static struct omap_hwmod_class i2c_class = {
194 - .name = "i2c",
195 - .sysc = &i2c_sysc,
196 - .rev = OMAP_I2C_IP_VERSION_1,
197 + .name = "i2c",
198 + .sysc = &i2c_sysc,
199 + .rev = OMAP_I2C_IP_VERSION_1,
200 + .reset = &omap_i2c_reset,
201 };
203 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
204 diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
205 index 55331df..5d5df49 100644
206 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
207 +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
208 @@ -22,6 +22,7 @@
210 #include <plat/omap_hwmod.h>
211 #include <plat/cpu.h>
212 +#include <plat/i2c.h>
213 #include <plat/gpio.h>
214 #include <plat/dma.h>
215 #include <plat/mcspi.h>
216 @@ -2162,6 +2163,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
217 .name = "i2c",
218 .sysc = &omap44xx_i2c_sysc,
219 .rev = OMAP_I2C_IP_VERSION_2,
220 + .reset = &omap_i2c_reset,
221 };
223 static struct omap_i2c_dev_attr i2c_dev_attr = {
224 @@ -2207,7 +2209,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
225 static struct omap_hwmod omap44xx_i2c1_hwmod = {
226 .name = "i2c1",
227 .class = &omap44xx_i2c_hwmod_class,
228 - .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
229 + .flags = HWMOD_16BIT_REG,
230 .mpu_irqs = omap44xx_i2c1_irqs,
231 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
232 .main_clk = "i2c1_fck",
233 @@ -2261,7 +2263,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
234 static struct omap_hwmod omap44xx_i2c2_hwmod = {
235 .name = "i2c2",
236 .class = &omap44xx_i2c_hwmod_class,
237 - .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
238 + .flags = HWMOD_16BIT_REG,
239 .mpu_irqs = omap44xx_i2c2_irqs,
240 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
241 .main_clk = "i2c2_fck",
242 @@ -2315,7 +2317,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
243 static struct omap_hwmod omap44xx_i2c3_hwmod = {
244 .name = "i2c3",
245 .class = &omap44xx_i2c_hwmod_class,
246 - .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
247 + .flags = HWMOD_16BIT_REG,
248 .mpu_irqs = omap44xx_i2c3_irqs,
249 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
250 .main_clk = "i2c3_fck",
251 @@ -2369,7 +2371,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
252 static struct omap_hwmod omap44xx_i2c4_hwmod = {
253 .name = "i2c4",
254 .class = &omap44xx_i2c_hwmod_class,
255 - .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
256 + .flags = HWMOD_16BIT_REG,
257 .mpu_irqs = omap44xx_i2c4_irqs,
258 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
259 .main_clk = "i2c4_fck",
260 diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
261 index fd75dad..7c22b9e 100644
262 --- a/arch/arm/plat-omap/include/plat/i2c.h
263 +++ b/arch/arm/plat-omap/include/plat/i2c.h
264 @@ -53,4 +53,7 @@ struct omap_i2c_dev_attr {
265 void __init omap1_i2c_mux_pins(int bus_id);
266 void __init omap2_i2c_mux_pins(int bus_id);
268 +struct omap_hwmod;
269 +int omap_i2c_reset(struct omap_hwmod *oh);
270 +
271 #endif /* __ASM__ARCH_OMAP_I2C_H */
272 diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
273 index ce06ac6..fafdfe3 100644
274 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
275 +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
276 @@ -566,6 +566,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
278 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
279 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
280 +int omap_hwmod_softreset(struct omap_hwmod *oh);
282 int omap_hwmod_count_resources(struct omap_hwmod *oh);
283 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
284 --
285 1.6.6.1