[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-3.0 / pm-wip / voltdm / 0076-OMAP4-clock-data-Add-missing-divider-selection-for-a.patch
1 From ce0ebe8b4f82a3205f9576400840d9fc0ae719d9 Mon Sep 17 00:00:00 2001
2 From: Rajendra Nayak <rnayak@ti.com>
3 Date: Sun, 10 Jul 2011 05:56:14 -0600
4 Subject: [PATCH 076/149] OMAP4: clock data: Add missing divider selection for auxclks
6 On OMAP4 the auxclk nodes (part of SCRM) support both
7 divider as well as parent selection.
8 Supporting this requires splitting the existing nodes
9 (which support only parent selection) into two nodes,
10 one for parent and another for divider selection.
11 The nodes for parent selection are named auxclk*_src_ck
12 and the ones for divider selection as auxclk*_ck.
14 Signed-off-by: Rajendra Nayak <rnayak@ti.com>
15 [b-cousson@ti.com: Rebase on top of clock cleanup
16 and autogen alignement]
17 Signed-off-by: Benoit Cousson <b-cousson@ti.com>
18 Cc: Paul Walmsley <paul@pwsan.com>
19 Signed-off-by: Paul Walmsley <paul@pwsan.com>
20 ---
21 arch/arm/mach-omap2/clock44xx_data.c | 176 +++++++++++++++++++++++++++++-----
22 1 files changed, 152 insertions(+), 24 deletions(-)
24 diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
25 index 763507f..07bf0de 100644
26 --- a/arch/arm/mach-omap2/clock44xx_data.c
27 +++ b/arch/arm/mach-omap2/clock44xx_data.c
28 @@ -2774,19 +2774,39 @@ static struct clk trace_clk_div_ck = {
30 /* SCRM aux clk nodes */
32 -static const struct clksel auxclk_sel[] = {
33 +static const struct clksel auxclk_src_sel[] = {
34 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
35 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
36 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
37 { .parent = NULL },
38 };
40 -static struct clk auxclk0_ck = {
41 - .name = "auxclk0_ck",
42 +static const struct clksel_rate div16_1to16_rates[] = {
43 + { .div = 1, .val = 0, .flags = RATE_IN_4430 },
44 + { .div = 2, .val = 1, .flags = RATE_IN_4430 },
45 + { .div = 3, .val = 2, .flags = RATE_IN_4430 },
46 + { .div = 4, .val = 3, .flags = RATE_IN_4430 },
47 + { .div = 5, .val = 4, .flags = RATE_IN_4430 },
48 + { .div = 6, .val = 5, .flags = RATE_IN_4430 },
49 + { .div = 7, .val = 6, .flags = RATE_IN_4430 },
50 + { .div = 8, .val = 7, .flags = RATE_IN_4430 },
51 + { .div = 9, .val = 8, .flags = RATE_IN_4430 },
52 + { .div = 10, .val = 9, .flags = RATE_IN_4430 },
53 + { .div = 11, .val = 10, .flags = RATE_IN_4430 },
54 + { .div = 12, .val = 11, .flags = RATE_IN_4430 },
55 + { .div = 13, .val = 12, .flags = RATE_IN_4430 },
56 + { .div = 14, .val = 13, .flags = RATE_IN_4430 },
57 + { .div = 15, .val = 14, .flags = RATE_IN_4430 },
58 + { .div = 16, .val = 15, .flags = RATE_IN_4430 },
59 + { .div = 0 },
60 +};
61 +
62 +static struct clk auxclk0_src_ck = {
63 + .name = "auxclk0_src_ck",
64 .parent = &sys_clkin_ck,
65 .init = &omap2_init_clksel_parent,
66 .ops = &clkops_omap2_dflt,
67 - .clksel = auxclk_sel,
68 + .clksel = auxclk_src_sel,
69 .clksel_reg = OMAP4_SCRM_AUXCLK0,
70 .clksel_mask = OMAP4_SRCSELECT_MASK,
71 .recalc = &omap2_clksel_recalc,
72 @@ -2794,12 +2814,29 @@ static struct clk auxclk0_ck = {
73 .enable_bit = OMAP4_ENABLE_SHIFT,
74 };
76 -static struct clk auxclk1_ck = {
77 - .name = "auxclk1_ck",
78 +static const struct clksel auxclk0_sel[] = {
79 + { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
80 + { .parent = NULL },
81 +};
82 +
83 +static struct clk auxclk0_ck = {
84 + .name = "auxclk0_ck",
85 + .parent = &auxclk0_src_ck,
86 + .clksel = auxclk0_sel,
87 + .clksel_reg = OMAP4_SCRM_AUXCLK0,
88 + .clksel_mask = OMAP4_CLKDIV_MASK,
89 + .ops = &clkops_null,
90 + .recalc = &omap2_clksel_recalc,
91 + .round_rate = &omap2_clksel_round_rate,
92 + .set_rate = &omap2_clksel_set_rate,
93 +};
94 +
95 +static struct clk auxclk1_src_ck = {
96 + .name = "auxclk1_src_ck",
97 .parent = &sys_clkin_ck,
98 .init = &omap2_init_clksel_parent,
99 .ops = &clkops_omap2_dflt,
100 - .clksel = auxclk_sel,
101 + .clksel = auxclk_src_sel,
102 .clksel_reg = OMAP4_SCRM_AUXCLK1,
103 .clksel_mask = OMAP4_SRCSELECT_MASK,
104 .recalc = &omap2_clksel_recalc,
105 @@ -2807,12 +2844,29 @@ static struct clk auxclk1_ck = {
106 .enable_bit = OMAP4_ENABLE_SHIFT,
107 };
109 -static struct clk auxclk2_ck = {
110 - .name = "auxclk2_ck",
111 +static const struct clksel auxclk1_sel[] = {
112 + { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
113 + { .parent = NULL },
114 +};
115 +
116 +static struct clk auxclk1_ck = {
117 + .name = "auxclk1_ck",
118 + .parent = &auxclk1_src_ck,
119 + .clksel = auxclk1_sel,
120 + .clksel_reg = OMAP4_SCRM_AUXCLK1,
121 + .clksel_mask = OMAP4_CLKDIV_MASK,
122 + .ops = &clkops_null,
123 + .recalc = &omap2_clksel_recalc,
124 + .round_rate = &omap2_clksel_round_rate,
125 + .set_rate = &omap2_clksel_set_rate,
126 +};
127 +
128 +static struct clk auxclk2_src_ck = {
129 + .name = "auxclk2_src_ck",
130 .parent = &sys_clkin_ck,
131 .init = &omap2_init_clksel_parent,
132 .ops = &clkops_omap2_dflt,
133 - .clksel = auxclk_sel,
134 + .clksel = auxclk_src_sel,
135 .clksel_reg = OMAP4_SCRM_AUXCLK2,
136 .clksel_mask = OMAP4_SRCSELECT_MASK,
137 .recalc = &omap2_clksel_recalc,
138 @@ -2820,12 +2874,29 @@ static struct clk auxclk2_ck = {
139 .enable_bit = OMAP4_ENABLE_SHIFT,
140 };
142 -static struct clk auxclk3_ck = {
143 - .name = "auxclk3_ck",
144 +static const struct clksel auxclk2_sel[] = {
145 + { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
146 + { .parent = NULL },
147 +};
148 +
149 +static struct clk auxclk2_ck = {
150 + .name = "auxclk2_ck",
151 + .parent = &auxclk2_src_ck,
152 + .clksel = auxclk2_sel,
153 + .clksel_reg = OMAP4_SCRM_AUXCLK2,
154 + .clksel_mask = OMAP4_CLKDIV_MASK,
155 + .ops = &clkops_null,
156 + .recalc = &omap2_clksel_recalc,
157 + .round_rate = &omap2_clksel_round_rate,
158 + .set_rate = &omap2_clksel_set_rate,
159 +};
160 +
161 +static struct clk auxclk3_src_ck = {
162 + .name = "auxclk3_src_ck",
163 .parent = &sys_clkin_ck,
164 .init = &omap2_init_clksel_parent,
165 .ops = &clkops_omap2_dflt,
166 - .clksel = auxclk_sel,
167 + .clksel = auxclk_src_sel,
168 .clksel_reg = OMAP4_SCRM_AUXCLK3,
169 .clksel_mask = OMAP4_SRCSELECT_MASK,
170 .recalc = &omap2_clksel_recalc,
171 @@ -2833,12 +2904,29 @@ static struct clk auxclk3_ck = {
172 .enable_bit = OMAP4_ENABLE_SHIFT,
173 };
175 -static struct clk auxclk4_ck = {
176 - .name = "auxclk4_ck",
177 +static const struct clksel auxclk3_sel[] = {
178 + { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
179 + { .parent = NULL },
180 +};
181 +
182 +static struct clk auxclk3_ck = {
183 + .name = "auxclk3_ck",
184 + .parent = &auxclk3_src_ck,
185 + .clksel = auxclk3_sel,
186 + .clksel_reg = OMAP4_SCRM_AUXCLK3,
187 + .clksel_mask = OMAP4_CLKDIV_MASK,
188 + .ops = &clkops_null,
189 + .recalc = &omap2_clksel_recalc,
190 + .round_rate = &omap2_clksel_round_rate,
191 + .set_rate = &omap2_clksel_set_rate,
192 +};
193 +
194 +static struct clk auxclk4_src_ck = {
195 + .name = "auxclk4_src_ck",
196 .parent = &sys_clkin_ck,
197 .init = &omap2_init_clksel_parent,
198 .ops = &clkops_omap2_dflt,
199 - .clksel = auxclk_sel,
200 + .clksel = auxclk_src_sel,
201 .clksel_reg = OMAP4_SCRM_AUXCLK4,
202 .clksel_mask = OMAP4_SRCSELECT_MASK,
203 .recalc = &omap2_clksel_recalc,
204 @@ -2846,12 +2934,29 @@ static struct clk auxclk4_ck = {
205 .enable_bit = OMAP4_ENABLE_SHIFT,
206 };
208 -static struct clk auxclk5_ck = {
209 - .name = "auxclk5_ck",
210 +static const struct clksel auxclk4_sel[] = {
211 + { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
212 + { .parent = NULL },
213 +};
214 +
215 +static struct clk auxclk4_ck = {
216 + .name = "auxclk4_ck",
217 + .parent = &auxclk4_src_ck,
218 + .clksel = auxclk4_sel,
219 + .clksel_reg = OMAP4_SCRM_AUXCLK4,
220 + .clksel_mask = OMAP4_CLKDIV_MASK,
221 + .ops = &clkops_null,
222 + .recalc = &omap2_clksel_recalc,
223 + .round_rate = &omap2_clksel_round_rate,
224 + .set_rate = &omap2_clksel_set_rate,
225 +};
226 +
227 +static struct clk auxclk5_src_ck = {
228 + .name = "auxclk5_src_ck",
229 .parent = &sys_clkin_ck,
230 .init = &omap2_init_clksel_parent,
231 .ops = &clkops_omap2_dflt,
232 - .clksel = auxclk_sel,
233 + .clksel = auxclk_src_sel,
234 .clksel_reg = OMAP4_SCRM_AUXCLK5,
235 .clksel_mask = OMAP4_SRCSELECT_MASK,
236 .recalc = &omap2_clksel_recalc,
237 @@ -2859,6 +2964,23 @@ static struct clk auxclk5_ck = {
238 .enable_bit = OMAP4_ENABLE_SHIFT,
239 };
241 +static const struct clksel auxclk5_sel[] = {
242 + { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
243 + { .parent = NULL },
244 +};
245 +
246 +static struct clk auxclk5_ck = {
247 + .name = "auxclk5_ck",
248 + .parent = &auxclk5_src_ck,
249 + .clksel = auxclk5_sel,
250 + .clksel_reg = OMAP4_SCRM_AUXCLK5,
251 + .clksel_mask = OMAP4_CLKDIV_MASK,
252 + .ops = &clkops_null,
253 + .recalc = &omap2_clksel_recalc,
254 + .round_rate = &omap2_clksel_round_rate,
255 + .set_rate = &omap2_clksel_set_rate,
256 +};
257 +
258 static const struct clksel auxclkreq_sel[] = {
259 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
260 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
261 @@ -3150,17 +3272,23 @@ static struct omap_clk omap44xx_clks[] = {
262 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
263 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
264 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
265 + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
266 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
267 - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
268 - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
269 - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
270 - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
271 - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
272 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
273 + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
274 + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
275 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
276 + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
277 + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
278 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
279 + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
280 + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
281 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
282 + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
283 + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
284 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
285 + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
286 + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
287 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
288 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
289 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
290 --
291 1.6.6.1