9e7f40ffe6d8d6f9f33122a835a2f6ae2119153b
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-3.0 / pm-wip / voltdm / 0126-OMAP3-PM-VC-handle-mutant-channel-config-for-OMAP4-M.patch
1 From 872a3007113d65d07cbc22e5cffc2e9264a7636d Mon Sep 17 00:00:00 2001
2 From: Kevin Hilman <khilman@ti.com>
3 Date: Thu, 2 Jun 2011 17:28:13 -0700
4 Subject: [PATCH 126/149] OMAP3+: PM: VC: handle mutant channel config for OMAP4 MPU channel
6 On OMAP3+, all VC channels have the the same bitfield ordering for all
7 VC channels, except the OMAP4 MPU channel. This appears to be a freak
8 accident as all other VC channel (including OMAP5) have the standard
9 configuration. Handle the mutant case by adding a per-channel flag
10 to signal the deformity and handle it during VC init.
12 Special thanks to Nishanth Menon <nm@ti.com> for finding this problem
13 and for proposing the initial solution.
15 Cc: Nishanth Menon <nm@ti.com>
16 Signed-off-by: Kevin Hilman <khilman@ti.com>
17 ---
18 arch/arm/mach-omap2/vc.c | 64 +++++++++++++++++++++++++++++-------
19 arch/arm/mach-omap2/vc.h | 1 +
20 arch/arm/mach-omap2/vc44xx_data.c | 2 +-
21 3 files changed, 53 insertions(+), 14 deletions(-)
23 diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
24 index 97a4c6c..9e51782 100644
25 --- a/arch/arm/mach-omap2/vc.c
26 +++ b/arch/arm/mach-omap2/vc.c
27 @@ -10,17 +10,51 @@
28 #include "prm-regbits-44xx.h"
29 #include "prm44xx.h"
31 -/*
32 - * Channel configuration bits, common for OMAP3 & 4
33 +/**
34 + * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
35 + * @sa: bit for slave address
36 + * @rav: bit for voltage configuration register
37 + * @rac: bit for command configuration register
38 + * @racen: enable bit for RAC
39 + * @cmd: bit for command value set selection
40 + *
41 + * Channel configuration bits, common for OMAP3+
42 * OMAP3 register: PRM_VC_CH_CONF
43 * OMAP4 register: PRM_VC_CFG_CHANNEL
44 + * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
45 */
46 -#define CFG_CHANNEL_SA BIT(0)
47 -#define CFG_CHANNEL_RAV BIT(1)
48 -#define CFG_CHANNEL_RAC BIT(2)
49 -#define CFG_CHANNEL_RACEN BIT(3)
50 -#define CFG_CHANNEL_CMD BIT(4)
51 -#define CFG_CHANNEL_MASK 0x3f
52 +struct omap_vc_channel_cfg {
53 + u8 sa;
54 + u8 rav;
55 + u8 rac;
56 + u8 racen;
57 + u8 cmd;
58 +};
59 +
60 +static struct omap_vc_channel_cfg vc_default_channel_cfg = {
61 + .sa = BIT(0),
62 + .rav = BIT(1),
63 + .rac = BIT(2),
64 + .racen = BIT(3),
65 + .cmd = BIT(4),
66 +};
67 +
68 +/*
69 + * On OMAP3+, all VC channels have the above default bitfield
70 + * configuration, except the OMAP4 MPU channel. This appears
71 + * to be a freak accident as every other VC channel has the
72 + * default configuration, thus creating a mutant channel config.
73 + */
74 +static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
75 + .sa = BIT(0),
76 + .rav = BIT(2),
77 + .rac = BIT(3),
78 + .racen = BIT(4),
79 + .cmd = BIT(1),
80 +};
81 +
82 +static struct omap_vc_channel_cfg *vc_cfg_bits;
83 +#define CFG_CHANNEL_MASK 0x1f
85 /**
86 * omap_vc_config_channel - configure VC channel to PMIC mappings
87 @@ -47,7 +81,7 @@ static int omap_vc_config_channel(struct voltagedomain *voltdm)
88 * All others must stay at zero (see function comment above.)
89 */
90 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
91 - vc->cfg_channel &= CFG_CHANNEL_RACEN;
92 + vc->cfg_channel &= vc_cfg_bits->racen;
94 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
95 vc->cfg_channel << vc->cfg_channel_sa_shift,
96 @@ -283,6 +317,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
97 }
99 vc->cfg_channel = 0;
100 + if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
101 + vc_cfg_bits = &vc_mutant_channel_cfg;
102 + else
103 + vc_cfg_bits = &vc_default_channel_cfg;
105 /* get PMIC/board specific settings */
106 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
107 @@ -294,7 +332,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
108 voltdm->rmw(vc->smps_sa_mask,
109 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
110 vc->common->smps_sa_reg);
111 - vc->cfg_channel |= CFG_CHANNEL_SA;
112 + vc->cfg_channel |= vc_cfg_bits->sa;
114 /*
115 * Configure the PMIC register addresses.
116 @@ -302,13 +340,13 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
117 voltdm->rmw(vc->smps_volra_mask,
118 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
119 vc->common->smps_volra_reg);
120 - vc->cfg_channel |= CFG_CHANNEL_RAV;
121 + vc->cfg_channel |= vc_cfg_bits->rav;
123 if (vc->cmd_reg_addr) {
124 voltdm->rmw(vc->smps_cmdra_mask,
125 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
126 vc->common->smps_cmdra_reg);
127 - vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
128 + vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
129 }
131 /* Set up the on, inactive, retention and off voltage */
132 @@ -321,7 +359,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
133 (ret_vsel << vc->common->cmd_ret_shift) |
134 (off_vsel << vc->common->cmd_off_shift));
135 voltdm->write(val, vc->cmdval_reg);
136 - vc->cfg_channel |= CFG_CHANNEL_CMD;
137 + vc->cfg_channel |= vc_cfg_bits->cmd;
139 /* Channel configuration */
140 omap_vc_config_channel(voltdm);
141 diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
142 index c577f28..ec50643 100644
143 --- a/arch/arm/mach-omap2/vc.h
144 +++ b/arch/arm/mach-omap2/vc.h
145 @@ -64,6 +64,7 @@ struct omap_vc_common {
147 /* omap_vc_channel.flags values */
148 #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
149 +#define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
151 /**
152 * struct omap_vc_channel - VC per-instance data
153 diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
154 index 148be18..0a4fc37 100644
155 --- a/arch/arm/mach-omap2/vc44xx_data.c
156 +++ b/arch/arm/mach-omap2/vc44xx_data.c
157 @@ -52,7 +52,7 @@ static const struct omap_vc_common omap4_vc_common = {
159 /* VC instance data for each controllable voltage line */
160 struct omap_vc_channel omap4_vc_mpu = {
161 - .flags = OMAP_VC_CHANNEL_DEFAULT,
162 + .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
163 .common = &omap4_vc_common,
164 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
165 .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
166 --
167 1.6.6.1