[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-omap-2.6.39 / mfd / 0012-MFD-TWL4030-workaround-changes-for-Erratum-27.patch
1 From 0bec9f7b20e7c61e0bab93195ec39cf94f1f8e25 Mon Sep 17 00:00:00 2001
2 From: Lesly A M <leslyam@ti.com>
3 Date: Wed, 1 Jun 2011 14:57:01 -0700
4 Subject: [PATCH 12/13] MFD: TWL4030: workaround changes for Erratum 27
6 Workaround for TWL5030 Silicon Errata 27 & 28:
7 27 - VDD1, VDD2, may have glitches when their output value is updated.
8 28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
9 is switched from internal to external.
11 Erratum 27:
12 If the DCDC regulators is running on their internal oscillator,
13 negative glitches may occur on VDD1, VDD2 output when voltage is changed.
14 The OMAP device may reboot if the VDD1 or VDD2 go below the
15 core minimum operating voltage.
17 WORKAROUND
18 Set up the TWL5030 DC-DC power supplies to use the HFCLKIN instead of
19 the internal oscillator.
21 Erratum 28:
22 VDD1/VDD2 clock system may hang during switching the clock source from
23 internal oscillator to external. VDD1/VDD2 output voltages may collapse
24 if clock stops.
26 WORKAROUND
27 If HFCLK is disabled in OFFMODE, modify the sleep/wakeup sequence and
28 setuptimes to make sure the switching will happen only when HFCLKIN is stable.
29 Also use the TWL5030 watchdog to safeguard the first switching from
30 internal oscillator to HFCLKIN during the TWL5030 init.
32 IMPACT
33 power sequence is changed.
34 sleep/wakeup time values will be changed.
36 The workaround changes are called from twl4030_power_init(), since we have to
37 make some i2c_read calls to check the TWL4030 version & the i2c will not be
38 initialized in the early stage.
40 This workaround is required for TWL5030 Silicon version less than ES1.2
41 The power script & setup time changes are recommended by TI HW team.
43 For more information please see:
44 http://omapedia.org/wiki/TWL4030_power_scripts
46 Changes taken from TWL4030 Erratum 27 workaround patch by Nishanth Menon.
48 Signed-off-by: Lesly A M <leslyam@ti.com>
49 Cc: Nishanth Menon <nm@ti.com>
50 Cc: David Derrick <dderrick@ti.com>
51 Cc: Samuel Ortiz <sameo@linux.intel.com>
52 ---
53 drivers/mfd/twl4030-power.c | 79 +++++++++++++++++++
54 drivers/mfd/twl4030-script-omap.c | 150 +++++++++++++++++++++++++++++++++++++
55 include/linux/i2c/twl.h | 1 +
56 3 files changed, 230 insertions(+), 0 deletions(-)
58 diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
59 index 91d5bc8..8af3fe3 100644
60 --- a/drivers/mfd/twl4030-power.c
61 +++ b/drivers/mfd/twl4030-power.c
62 @@ -63,6 +63,14 @@ static u8 twl4030_start_script_address = 0x2b;
63 #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
64 #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
66 +#define R_VDD1_OSC 0x5C
67 +#define R_VDD2_OSC 0x6A
68 +#define R_VIO_OSC 0x52
69 +#define EXT_FS_CLK_EN BIT(6)
70 +
71 +#define R_WDT_CFG 0x03
72 +#define WDT_WRK_TIMEOUT 0x03
73 +
74 /* resource configuration registers
75 <RESOURCE>_DEV_GRP at address 'n+0'
76 <RESOURCE>_TYPE at address 'n+1'
77 @@ -512,6 +520,67 @@ int twl4030_remove_script(u8 flags)
78 }
79 EXPORT_SYMBOL_GPL(twl4030_remove_script);
81 +/**
82 + * twl_dcdc_use_hfclk - API to use HFCLK for TWL DCDCs
83 + *
84 + * TWL DCDCs switching to HFCLK instead of using internal RC oscillator.
85 + */
86 +static int twl_dcdc_use_hfclk(void)
87 +{
88 + u8 val;
89 + u8 smps_osc_reg[] = {R_VDD1_OSC, R_VDD2_OSC, R_VIO_OSC};
90 + int i;
91 + int err;
92 +
93 + for (i = 0; i < sizeof(smps_osc_reg); i++) {
94 + err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &val,
95 + smps_osc_reg[i]);
96 + val |= EXT_FS_CLK_EN;
97 + err |= twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, val,
98 + smps_osc_reg[i]);
99 + }
100 + return err;
101 +}
102 +
103 +/**
104 + * twl_erratum27_workaround - Workaround for TWL5030 Silicon Erratum 27
105 + * 27 - VDD1, VDD2, may have glitches when their output value is updated.
106 + * 28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock is
107 + * switched from internal to external.
108 + *
109 + * Workaround requires the TWL DCDCs to use HFCLK instead of
110 + * internal oscillator. Also enable TWL watchdog before switching the osc
111 + * to recover if the VDD1/VDD2 stop working.
112 + */
113 +static void twl_erratum27_workaround(void)
114 +{
115 + u8 wdt_counter_val = 0;
116 + int err;
117 +
118 + /* Setup the twl wdt to take care of borderline failure case */
119 + err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &wdt_counter_val,
120 + R_WDT_CFG);
121 + err |= twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, WDT_WRK_TIMEOUT,
122 + R_WDT_CFG);
123 +
124 + /* TWL DCDC switching to HFCLK */
125 + err |= twl_dcdc_use_hfclk();
126 +
127 + /* restore the original value */
128 + err |= twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, wdt_counter_val,
129 + R_WDT_CFG);
130 + if (err)
131 + pr_warning("TWL4030: workaround setup failed!\n");
132 +}
133 +
134 +static bool is_twl5030_erratum27wa_required(void)
135 +{
136 + if (twl_get_type() == TWL_SIL_5030)
137 + return (twl_get_version() < TWL5030_REV_1_2);
138 +
139 + return 0;
140 +}
141 +
142 int twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
143 {
144 int err = 0;
145 @@ -530,6 +599,16 @@ int twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
146 TWL4030_PM_MASTER_PROTECT_KEY);
147 if (err)
148 goto unlock;
149 +
150 + /* Applying TWL5030 Erratum 27 WA based on Si revision &
151 + * flag updated from board file*/
152 + if (is_twl5030_erratum27wa_required()) {
153 + pr_info("TWL5030: Enabling workaround for Si Erratum 27\n");
154 + twl_erratum27_workaround();
155 + if (twl4030_scripts->twl5030_erratum27wa_script)
156 + twl4030_scripts->twl5030_erratum27wa_script();
157 + }
158 +
159 for (i = 0; i < twl4030_scripts->num; i++) {
160 err = load_twl4030_script(twl4030_scripts->scripts[i], address);
161 if (err)
162 diff --git a/drivers/mfd/twl4030-script-omap.c b/drivers/mfd/twl4030-script-omap.c
163 index 867a442..ff93fd2 100644
164 --- a/drivers/mfd/twl4030-script-omap.c
165 +++ b/drivers/mfd/twl4030-script-omap.c
166 @@ -326,10 +326,160 @@ static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
167 { 0, 0},
168 };
170 +/*
171 + * Sleep and active sequences with changes for TWL5030 Erratum 27 workaround
172 + *
173 + * Sysoff (using sys_off signal):
174 + * When SYS_CLKREQ goes low during retention no resources will be affected
175 + * since no resources are assigned to P3 only.
176 + *
177 + * Since all resources are assigned to P1 and P3 then all resources
178 + * will be affected on the falling edge of P3 (SYS_CLKREQ).
179 + * When OMAP lower the SYS_CLKREQ signal PMIC will execute the
180 + * A2S sequence in which HFCLKOUT is dissabled first and
181 + * after 488.32 usec(PRM_VOLTOFFSET) resources assigned to P1 and P3
182 + * and of TYPE2=1 are put to sleep
183 + * (VDD1, VDD2, VPLL1, REGEN, NRESPWRON & SYSEN).
184 + * Again after a 61.04 usec resources assigned to P1 and P3
185 + * and of TYPE2=2 are put to sleep
186 + * (VINTANA1, VINTANA2, VINTDIG, VIO & CLKEN).
187 + *
188 + * On wakeup event OMAP goes active and pulls the SYS_CLKREQ high,
189 + * and will execute the S2A sequence which is same for P1_P2 & P3.
190 + * This will turn on all resources of TYPE2=2 to go to the active state.
191 + * Three dummy broadcast messages are added to get a delay of ~10 ms
192 + * before enabling the HFCLKOUT resource. And after a 30.52 usec
193 + * all resources of TYPE2=1 are put to the active state.
194 + *
195 + * This 10ms delay can be reduced if the oscillator is having less
196 + * stabilization time. A should be taken care if it needs more time
197 + * for stabilization.
198 + *
199 + */
200 +
201 +/**
202 + * DOC: Sleep to Active sequence for P1/P2/P3
203 + *
204 + * The wakeup sequence is adjusted to do the VDD1/VDD2 voltage ramp-up
205 + * only after HFCLKIN is stabilized and the HFCLKOUT is enabled.
206 + */
207 +static struct twl4030_ins wakeup_seq_erratum27[] __initdata = {
208 + /*
209 + * Broadcast message to put res(TYPE2 = 2) to active.
210 + * Wait for ~10 mS (ramp-up time for OSC on the board)
211 + * after HFCLKIN is enabled
212 + */
213 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
214 + RES_STATE_ACTIVE), 55},
215 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
216 + RES_STATE_ACTIVE), 55},
217 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
218 + RES_STATE_ACTIVE), 54},
219 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
220 + RES_STATE_ACTIVE), 1},
221 + /* Singular message to enable HCLKOUT after HFCLKIN is stabilized */
222 + {MSG_SINGULAR(DEV_GRP_NULL, RES_HFCLKOUT, RES_STATE_ACTIVE), 1},
223 + /*
224 + * Broadcast message to put res(TYPE2 = 1) to active.
225 + * VDD1/VDD2 ramp-up after HFCLKIN is stable and HFCLKOUT is enabled.
226 + */
227 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
228 + RES_STATE_ACTIVE), 2},
229 +};
230 +
231 +static struct twl4030_script wakeup_script_erratum27 __initdata = {
232 + .script = wakeup_seq_erratum27,
233 + .size = ARRAY_SIZE(wakeup_seq_erratum27),
234 + .flags = TWL4030_WAKEUP12_SCRIPT | TWL4030_WAKEUP3_SCRIPT,
235 +};
236 +
237 +/**
238 + * DOC: Active to Sleep sequence for P1/P2/P3
239 + *
240 + * The sleep sequence is adjusted to do the switching of VDD1/VDD2/VIO OSC from
241 + * HFCLKIN to internal oscillator when the HFCLKIN is stable.
242 + */
243 +static struct twl4030_ins sleep_on_seq_erratum27[] __initdata = {
244 + /*
245 + * Singular message to disable HCLKOUT.
246 + * Wait for ~488.32 uS to do the switching of VDD1/VDD2/VIO OSC from
247 + * HFCLKIN to internal oscillator before disabling HFCLKIN.
248 + */
249 + {MSG_SINGULAR(DEV_GRP_NULL, RES_HFCLKOUT, RES_STATE_SLEEP), 20},
250 + /* Broadcast message to put res(TYPE2 = 1) to sleep */
251 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
252 + RES_STATE_SLEEP), 2},
253 + /* Broadcast message to put res(TYPE2 = 2) to sleep, disable HFCLKIN */
254 + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
255 + RES_STATE_SLEEP), 2},
256 +};
257 +
258 +static struct twl4030_script sleep_on_script_erratum27 __initdata = {
259 + .script = sleep_on_seq_erratum27,
260 + .size = ARRAY_SIZE(sleep_on_seq_erratum27),
261 + .flags = TWL4030_SLEEP_SCRIPT,
262 +};
263 +
264 +/* TWL4030 script for sleep, wakeup & warm_reset */
265 +static struct twl4030_script *twl4030_scripts_erratum27[] __initdata = {
266 + &wakeup_script_erratum27,
267 + &sleep_on_script_erratum27,
268 + &wrst_script,
269 +};
270 +
271 +/**
272 + * DOC: TWL4030 resource configuration
273 + *
274 + * VDD1/VDD2/VPLL are assigned to P1 and P3, to have better control
275 + * during OFFMODE. HFCLKOUT is assigned to P1 and P3 (*p2) to turn off
276 + * only during OFFMODE.
277 + * (*P2 is included if the platform uses it for modem/some other processor)
278 + */
279 +static struct twl4030_resconfig twl4030_rconfig_erratum27[] __initdata = {
280 + { .resource = RES_VPLL1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
281 + .type = 3, .type2 = 1, .remap_sleep = RES_STATE_OFF },
282 + { .resource = RES_VINTANA1, .devgroup = DEV_GRP_ALL, .type = 1,
283 + .type2 = 2, .remap_sleep = RES_STATE_SLEEP },
284 + { .resource = RES_VINTANA2, .devgroup = DEV_GRP_ALL, .type = 0,
285 + .type2 = 2, .remap_sleep = RES_STATE_SLEEP },
286 + { .resource = RES_VINTDIG, .devgroup = DEV_GRP_ALL, .type = 1,
287 + .type2 = 2, .remap_sleep = RES_STATE_SLEEP },
288 + { .resource = RES_VIO, .devgroup = DEV_GRP_ALL, .type = 2,
289 + .type2 = 2, .remap_sleep = RES_STATE_SLEEP },
290 + { .resource = RES_VDD1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
291 + .type = 4, .type2 = 1, .remap_sleep = RES_STATE_OFF },
292 + { .resource = RES_VDD2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
293 + .type = 3, .type2 = 1, .remap_sleep = RES_STATE_OFF },
294 + { .resource = RES_REGEN, .devgroup = DEV_GRP_ALL, .type = 2,
295 + .type2 = 1, .remap_sleep = RES_STATE_SLEEP },
296 + { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_ALL, .type = 0,
297 + .type2 = 1, .remap_sleep = RES_STATE_SLEEP },
298 + { .resource = RES_CLKEN, .devgroup = DEV_GRP_ALL, .type = 3,
299 + .type2 = 2, .remap_sleep = RES_STATE_SLEEP },
300 + { .resource = RES_SYSEN, .devgroup = DEV_GRP_ALL, .type = 6,
301 + .type2 = 1, .remap_sleep = RES_STATE_SLEEP },
302 + { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
303 + .type = 0, .type2 = 1, .remap_sleep = RES_STATE_SLEEP },
304 + { 0, 0},
305 +};
306 +
307 +/**
308 + * twl5030_script_erratum27() - API to modify TWL4030 script
309 + *
310 + * Updating the TWL4030 script & resource configuration
311 + */
312 +static void __init twl5030_script_erratum27(void)
313 +{
314 + twl4030_generic_script.scripts = twl4030_scripts_erratum27;
315 + twl4030_generic_script.num = ARRAY_SIZE(twl4030_scripts_erratum27);
316 + twl4030_generic_script.resource_config = twl4030_rconfig_erratum27;
317 +}
318 +
319 struct twl4030_power_data twl4030_generic_script __initdata = {
320 .scripts = twl4030_scripts,
321 .num = ARRAY_SIZE(twl4030_scripts),
322 .resource_config = twl4030_rconfig,
323 + .twl5030_erratum27wa_script = twl5030_script_erratum27,
324 };
326 static int __init twl4030_script_probe(struct platform_device *pdev)
327 diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
328 index 23ec058..10cb6e2 100644
329 --- a/include/linux/i2c/twl.h
330 +++ b/include/linux/i2c/twl.h
331 @@ -681,6 +681,7 @@ struct twl4030_power_data {
332 struct twl4030_script **scripts;
333 unsigned num;
334 struct twl4030_resconfig *resource_config;
335 + void (*twl5030_erratum27wa_script)(void);
336 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
337 };
339 --
340 1.6.6.1