[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / 3.2.10 / 0054-drm-i915-gen7-Disable-the-RHWO-optimization-as-it-ca.patch
1 From 62636ad79afb701ad1580d4b45eb5840e811064f Mon Sep 17 00:00:00 2001
2 From: Kenneth Graunke <kenneth@whitecape.org>
3 Date: Wed, 8 Feb 2012 12:53:52 -0800
4 Subject: [PATCH 54/95] drm/i915: gen7: Disable the RHWO optimization as it
5 can cause GPU hangs.
7 commit d71de14ddf423ccc9a2e3f7e37553c99ead20d7c upstream.
9 The BSpec Workarounds page states that bits 10 and 26 must be set to
10 avoid 3D ring hangs.
12 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
13 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610
14 Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
15 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
16 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 ---
19 drivers/gpu/drm/i915/i915_reg.h | 3 +++
20 drivers/gpu/drm/i915/intel_display.c | 4 ++++
21 2 files changed, 7 insertions(+)
23 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
24 index 2ae87ca..1608d2a 100644
25 --- a/drivers/gpu/drm/i915/i915_reg.h
26 +++ b/drivers/gpu/drm/i915/i915_reg.h
27 @@ -2887,6 +2887,9 @@
28 #define DISP_FBC_WM_DIS (1<<15)
30 /* GEN7 chicken */
31 +#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
32 +# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
33 +
34 #define GEN7_L3CNTLREG1 0xB01C
35 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
37 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
38 index bf3deb1..72dc505 100644
39 --- a/drivers/gpu/drm/i915/intel_display.c
40 +++ b/drivers/gpu/drm/i915/intel_display.c
41 @@ -8255,6 +8255,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
43 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
45 + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
46 + I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
47 + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
48 +
49 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
50 I915_WRITE(GEN7_L3CNTLREG1,
51 GEN7_WA_FOR_GEN7_L3_CONTROL);
52 --
53 1.7.9.4