[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / 3.2.17 / 0119-ARM-7396-1-errata-only-handle-ARM-erratum-326103-on-.patch
1 From 73a8033457dd006878a2eeeb14133724923cd6af Mon Sep 17 00:00:00 2001
2 From: Will Deacon <will.deacon@arm.com>
3 Date: Fri, 20 Apr 2012 17:20:08 +0100
4 Subject: [PATCH 119/165] ARM: 7396/1: errata: only handle ARM erratum #326103
5 on affected cores
7 commit f0c4b8d653f5ee091fb8d4d02ed7eaad397491bb upstream.
9 Erratum #326103 ("FSR write bit incorrect on a SWP to read-only memory")
10 only affects the ARM 1136 core prior to r1p0. The workaround
11 disassembles the faulting instruction to determine whether it was a read
12 or write access on all v6 cores.
14 An issue has been reported on the ARM 11MPCore whereby loading the
15 faulting instruction may happen in parallel with that page being
16 unmapped, resulting in a deadlock due to the lack of TLB broadcasting
17 in hardware:
19 http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091561.html
21 This patch limits the workaround so that it is only used on affected
22 cores, which are known to be UP only. Other v6 cores can rely on the
23 FSR to indicate the access type correctly.
25 Signed-off-by: Will Deacon <will.deacon@arm.com>
26 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
27 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
28 ---
29 arch/arm/Kconfig | 9 +++++++++
30 arch/arm/mm/abort-ev6.S | 17 +++++++++++------
31 2 files changed, 20 insertions(+), 6 deletions(-)
33 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
34 index 6cd71ec..26574f0 100644
35 --- a/arch/arm/Kconfig
36 +++ b/arch/arm/Kconfig
37 @@ -1156,6 +1156,15 @@ if !MMU
38 source "arch/arm/Kconfig-nommu"
39 endif
41 +config ARM_ERRATA_326103
42 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
43 + depends on CPU_V6
44 + help
45 + Executing a SWP instruction to read-only memory does not set bit 11
46 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
47 + treat the access as a read, preventing a COW from occurring and
48 + causing the faulting task to livelock.
49 +
50 config ARM_ERRATA_411920
51 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
52 depends on CPU_V6 || CPU_V6K
53 diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
54 index ff1f7cc..8074199 100644
55 --- a/arch/arm/mm/abort-ev6.S
56 +++ b/arch/arm/mm/abort-ev6.S
57 @@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
58 mrc p15, 0, r1, c5, c0, 0 @ get FSR
59 mrc p15, 0, r0, c6, c0, 0 @ get FAR
60 /*
61 - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
62 - * The test below covers all the write situations, including Java bytecodes
63 + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
64 */
65 - bic r1, r1, #1 << 11 @ clear bit 11 of FSR
66 +#ifdef CONFIG_ARM_ERRATA_326103
67 + ldr ip, =0x4107b36
68 + mrc p15, 0, r3, c0, c0, 0 @ get processor id
69 + teq ip, r3, lsr #4 @ r0 ARM1136?
70 + bne do_DataAbort
71 tst r5, #PSR_J_BIT @ Java?
72 + tsteq r5, #PSR_T_BIT @ Thumb?
73 bne do_DataAbort
74 - do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
75 - ldreq r3, [r4] @ read aborted ARM instruction
76 + bic r1, r1, #1 << 11 @ clear bit 11 of FSR
77 + ldr r3, [r4] @ read aborted ARM instruction
78 #ifdef CONFIG_CPU_ENDIAN_BE8
79 - reveq r3, r3
80 + rev r3, r3
81 #endif
82 do_ldrd_abort tmp=ip, insn=r3
83 tst r3, #1 << 20 @ L = 0 -> write
84 orreq r1, r1, #1 << 11 @ yes.
85 +#endif
86 b do_DataAbort
87 --
88 1.7.7.6