[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / 3.2.17 / 0151-ARM-7410-1-Add-extra-clobber-registers-for-assembly-.patch
1 From 8a73393b01a8d2a9959a094d34d037802d78161b Mon Sep 17 00:00:00 2001
2 From: Tim Bird <tim.bird@am.sony.com>
3 Date: Wed, 2 May 2012 22:55:39 +0100
4 Subject: [PATCH 151/165] ARM: 7410/1: Add extra clobber registers for
5 assembly in kernel_execve
7 commit e787ec1376e862fcea1bfd523feb7c5fb43ecdb9 upstream.
9 The inline assembly in kernel_execve() uses r8 and r9. Since this
10 code sequence does not return, it usually doesn't matter if the
11 register clobber list is accurate. However, I saw a case where a
12 particular version of gcc used r8 as an intermediate for the value
13 eventually passed to r9. Because r8 is used in the inline
14 assembly, and not mentioned in the clobber list, r9 was set
15 to an incorrect value.
17 This resulted in a kernel panic on execution of the first user-space
18 program in the system. r9 is used in ret_to_user as the thread_info
19 pointer, and if it's wrong, bad things happen.
21 Signed-off-by: Tim Bird <tim.bird@am.sony.com>
22 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
23 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
24 ---
25 arch/arm/kernel/sys_arm.c | 2 +-
26 1 files changed, 1 insertions(+), 1 deletions(-)
28 diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
29 index d2b1779..76cbb05 100644
30 --- a/arch/arm/kernel/sys_arm.c
31 +++ b/arch/arm/kernel/sys_arm.c
32 @@ -115,7 +115,7 @@ int kernel_execve(const char *filename,
33 "Ir" (THREAD_START_SP - sizeof(regs)),
34 "r" (®s),
35 "Ir" (sizeof(regs))
36 - : "r0", "r1", "r2", "r3", "ip", "lr", "memory");
37 + : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory");
39 out:
40 return ret;
41 --
42 1.7.7.6