[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / 3.2.21 / 0018-crypto-aesni-intel-fix-unaligned-cbc-decrypt-for-x86.patch
1 From e7814580e8b3d8f81dac54f4919f7f3b75b40c0d Mon Sep 17 00:00:00 2001
2 From: Mathias Krause <minipli@googlemail.com>
3 Date: Wed, 30 May 2012 01:43:08 +0200
4 Subject: [PATCH 18/67] crypto: aesni-intel - fix unaligned cbc decrypt for
5 x86-32
7 commit 7c8d51848a88aafdb68f42b6b650c83485ea2f84 upstream.
9 The 32 bit variant of cbc(aes) decrypt is using instructions requiring
10 128 bit aligned memory locations but fails to ensure this constraint in
11 the code. Fix this by loading the data into intermediate registers with
12 load unaligned instructions.
14 This fixes reported general protection faults related to aesni.
16 References: https://bugzilla.kernel.org/show_bug.cgi?id=43223
17 Reported-by: Daniel <garkein@mailueberfall.de>
18 Signed-off-by: Mathias Krause <minipli@googlemail.com>
19 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
20 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
21 ---
22 arch/x86/crypto/aesni-intel_asm.S | 6 ++++--
23 1 file changed, 4 insertions(+), 2 deletions(-)
25 diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S
26 index be6d9e3..3470624 100644
27 --- a/arch/x86/crypto/aesni-intel_asm.S
28 +++ b/arch/x86/crypto/aesni-intel_asm.S
29 @@ -2460,10 +2460,12 @@ ENTRY(aesni_cbc_dec)
30 pxor IN3, STATE4
31 movaps IN4, IV
32 #else
33 - pxor (INP), STATE2
34 - pxor 0x10(INP), STATE3
35 pxor IN1, STATE4
36 movaps IN2, IV
37 + movups (INP), IN1
38 + pxor IN1, STATE2
39 + movups 0x10(INP), IN2
40 + pxor IN2, STATE3
41 #endif
42 movups STATE1, (OUTP)
43 movups STATE2, 0x10(OUTP)
44 --
45 1.7.9.5