[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / 3.2.9 / 0019-ARM-7325-1-fix-v7-boot-with-lockdep-enabled.patch
1 From ceb484992b356b7f9b499cf56b8ba8da8289aa74 Mon Sep 17 00:00:00 2001
2 From: Rabin Vincent <rabin@rab.in>
3 Date: Wed, 15 Feb 2012 16:01:42 +0100
4 Subject: [PATCH 19/73] ARM: 7325/1: fix v7 boot with lockdep enabled
6 commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream.
8 Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
9 ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").
11 This is because v7_setup (which is called very early during boot) calls
12 v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
13 ends up attempting to call into lockdep C code (trace_hardirqs_off())
14 when we are in no position to execute it (no stack, MMU off).
16 Fix this by using a notrace variant of save_and_disable_irqs. The code
17 already uses the notrace variant of restore_irqs.
19 Reviewed-by: Nicolas Pitre <nico@linaro.org>
20 Acked-by: Stephen Boyd <sboyd@codeaurora.org>
21 Cc: Catalin Marinas <catalin.marinas@arm.com>
22 Signed-off-by: Rabin Vincent <rabin@rab.in>
23 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
24 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
25 ---
26 arch/arm/include/asm/assembler.h | 5 +++++
27 arch/arm/mm/cache-v7.S | 2 +-
28 2 files changed, 6 insertions(+), 1 deletions(-)
30 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
31 index 29035e8..7bb8bf9 100644
32 --- a/arch/arm/include/asm/assembler.h
33 +++ b/arch/arm/include/asm/assembler.h
34 @@ -137,6 +137,11 @@
35 disable_irq
36 .endm
38 + .macro save_and_disable_irqs_notrace, oldcpsr
39 + mrs \oldcpsr, cpsr
40 + disable_irq_notrace
41 + .endm
42 +
43 /*
44 * Restore interrupt state previously stored in a register. We don't
45 * guarantee that this will preserve the flags.
46 diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
47 index 7a24d39..a655d3d 100644
48 --- a/arch/arm/mm/cache-v7.S
49 +++ b/arch/arm/mm/cache-v7.S
50 @@ -55,7 +55,7 @@ loop1:
51 cmp r1, #2 @ see what cache we have at this level
52 blt skip @ skip if no cache, or just i-cache
53 #ifdef CONFIG_PREEMPT
54 - save_and_disable_irqs r9 @ make cssr&csidr read atomic
55 + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
56 #endif
57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
58 isb @ isb to sych the new cssr&csidr
59 --
60 1.7.7.4