[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / beaglebone / 0047-Adding-many-of-the-missing-signals-to-the-mux-table.patch
1 From 023eed8b578f4b3ccc992ade8344277f9f9e08d6 Mon Sep 17 00:00:00 2001
2 From: Bas Laarhoven <sjml@xs4all.nl>
3 Date: Sun, 13 May 2012 18:16:34 +0200
4 Subject: [PATCH 47/79] Adding many of the missing signals to the mux table.
6 Signed-off-by: Bas Laarhoven <sjml@xs4all.nl>
7 ---
8 arch/arm/mach-omap2/mux33xx.c | 197 +++++++++++++++++++++--------------------
9 1 file changed, 101 insertions(+), 96 deletions(-)
11 diff --git a/arch/arm/mach-omap2/mux33xx.c b/arch/arm/mach-omap2/mux33xx.c
12 index 25dcedb..26ecd66 100644
13 --- a/arch/arm/mach-omap2/mux33xx.c
14 +++ b/arch/arm/mach-omap2/mux33xx.c
15 @@ -28,6 +28,11 @@
16 }
18 /* AM33XX pin mux super set */
19 +/* 20120513 - SJL added a lot of missing signals using datasheet rev. C.
20 + * Converted all names to lower case, except for the A and B
21 + * channel suffixes, as that seems to be the rule.
22 + * Marked lines with completed spec by leading empty comment.
23 + */
24 static struct omap_mux __initdata am33xx_muxmodes[] = {
25 _AM33XX_MUXENTRY(GPMC_AD0, 0,
26 "gpmc_ad0", "mmc1_dat0", NULL, NULL,
27 @@ -53,21 +58,21 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
28 _AM33XX_MUXENTRY(GPMC_AD7, 0,
29 "gpmc_ad7", "mmc1_dat7", NULL, NULL,
30 NULL, NULL, NULL, "gpio1_7"),
31 - _AM33XX_MUXENTRY(GPMC_AD8, 0,
32 +/**/ _AM33XX_MUXENTRY(GPMC_AD8, 0,
33 "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
34 - NULL, NULL, NULL, "gpio0_22"),
35 - _AM33XX_MUXENTRY(GPMC_AD9, 0,
36 + "ehrpwm2A", "pr1_mii_mt0_clk", NULL, "gpio0_22"),
37 +/**/ _AM33XX_MUXENTRY(GPMC_AD9, 0,
38 "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
39 - "ehrpwm2B", NULL, NULL, "gpio0_23"),
40 - _AM33XX_MUXENTRY(GPMC_AD10, 0,
41 + "ehrpwm2B", "pr1_mii0_col", NULL, "gpio0_23"),
42 +/**/ _AM33XX_MUXENTRY(GPMC_AD10, 0,
43 "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
44 - NULL, NULL, NULL, "gpio0_26"),
45 - _AM33XX_MUXENTRY(GPMC_AD11, 0,
46 + "ehrpwm2_tripzone_input", "pr1_mii0_txen", NULL, "gpio0_26"),
47 +/**/ _AM33XX_MUXENTRY(GPMC_AD11, 0,
48 "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
49 - NULL, NULL, NULL, "gpio0_27"),
50 - _AM33XX_MUXENTRY(GPMC_AD12, 0,
51 + "ehrpwm0_synco", "pr1_mii0_txd3", NULL, "gpio0_27"),
52 +/**/ _AM33XX_MUXENTRY(GPMC_AD12, 0,
53 "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
54 - NULL, NULL, NULL, "gpio1_12"),
55 + "eqep2a_in", "pr1_mii0_txd2", "pr1_pru0_pru_r30_14", "gpio1_12"),
56 _AM33XX_MUXENTRY(GPMC_AD13, 0,
57 "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
58 NULL, NULL, NULL, "gpio1_13"),
59 @@ -77,33 +82,33 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
60 _AM33XX_MUXENTRY(GPMC_AD15, 0,
61 "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
62 NULL, NULL, NULL, "gpio1_15"),
63 - _AM33XX_MUXENTRY(GPMC_A0, 0,
64 - "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
65 - NULL, NULL, NULL, "gpio1_16"),
66 - _AM33XX_MUXENTRY(GPMC_A1, 0,
67 - "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
68 - NULL, NULL, NULL, "gpio1_17"),
69 - _AM33XX_MUXENTRY(GPMC_A2, 0,
70 - "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
71 - NULL, NULL, "ehrpwm1A", "gpio1_18"),
72 - _AM33XX_MUXENTRY(GPMC_A3, 0,
73 - "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
74 - NULL, NULL, NULL, "gpio1_19"),
75 - _AM33XX_MUXENTRY(GPMC_A4, 0,
76 - "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
77 - "gpmc_a20", NULL, NULL, "gpio1_20"),
78 - _AM33XX_MUXENTRY(GPMC_A5, 0,
79 - "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
80 - "gpmc_a21", NULL, NULL, "gpio1_21"),
81 - _AM33XX_MUXENTRY(GPMC_A6, 0,
82 - "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
83 - "gpmc_a22", NULL, NULL, "gpio1_22"),
84 - _AM33XX_MUXENTRY(GPMC_A7, 0,
85 - "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
86 - NULL, NULL, NULL, "gpio1_23"),
87 - _AM33XX_MUXENTRY(GPMC_A8, 0,
88 - "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
89 - NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
90 +/**/ _AM33XX_MUXENTRY(GPMC_A0, 0,
91 + "gpmc_a0", "gmii2_txen", "rgmii2_tctl", "rmii2_txen",
92 + "gpmc_a16", "pr1_mii_mt1_clk", "ehrpwm1_tripzone_input", "gpio1_16"),
93 +/**/ _AM33XX_MUXENTRY(GPMC_A1, 0,
94 + "gpmc_a1", "gmii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
95 + "gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
96 +/**/ _AM33XX_MUXENTRY(GPMC_A2, 0,
97 + "gpmc_a2", "gmii2_txd3", "rgmii2_td3", "mmc2_dat1",
98 + "gpmc_a18", "pr1_mii1_txd2", "ehrpwm1A", "gpio1_18"),
99 +/**/ _AM33XX_MUXENTRY(GPMC_A3, 0,
100 + "gpmc_a3", "gmii2_txd2", "rgmii2_td2", "mmc2_dat2",
101 + "gpmc_a19", "pr1_mii1_txd1", "ehrpwm1B", "gpio1_19"),
102 +/**/ _AM33XX_MUXENTRY(GPMC_A4, 0,
103 + "gpmc_a4", "gmii2_txd1", "rgmii2_td1", "rmii2_txd1",
104 + "gpmc_a20", "pr1_mii1_txd0", "eqep1a_in", "gpio1_20"),
105 +/**/ _AM33XX_MUXENTRY(GPMC_A5, 0,
106 + "gpmc_a5", "gmii2_txd0", "rgmii2_td0", "rmii2_txd0",
107 + "gpmc_a21", "pr1_mii1_rxd3", "eqep1b_in", "gpio1_21"),
108 +/**/ _AM33XX_MUXENTRY(GPMC_A6, 0,
109 + "gpmc_a6", "gmii2_txclk", "rgmii2_tclk", "mmc2_dat4",
110 + "gpmc_a22", "pr1_mii1_rxd2", "eqep1_index", "gpio1_22"),
111 +/**/ _AM33XX_MUXENTRY(GPMC_A7, 0,
112 + "gpmc_a7", "gmii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
113 + "gpmc_a23", "pr1_mii1_rxd1", "eqep1_strobe", "gpio1_23"),
114 +/**/ _AM33XX_MUXENTRY(GPMC_A8, 0,
115 + "gpmc_a8", "gmii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
116 + "gpmc_a24", "pr1_mii1_rxd0", "mcasp0_aclkx", "gpio1_24"),
117 _AM33XX_MUXENTRY(GPMC_A9, 0,
118 "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
119 NULL, NULL, "mcasp0_fsx", "gpio1_25"),
120 @@ -122,18 +127,18 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
121 _AM33XX_MUXENTRY(GPMC_BEN1, 0,
122 "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
123 NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
124 - _AM33XX_MUXENTRY(GPMC_CSN0, 0,
125 +/**/ _AM33XX_MUXENTRY(GPMC_CSN0, 0,
126 "gpmc_csn0", NULL, NULL, NULL,
127 NULL, NULL, NULL, "gpio1_29"),
128 - _AM33XX_MUXENTRY(GPMC_CSN1, 0,
129 - "gpmc_csn1", NULL, "mmc1_clk", NULL,
130 - NULL, NULL, NULL, "gpio1_30"),
131 - _AM33XX_MUXENTRY(GPMC_CSN2, 0,
132 - "gpmc_csn2", NULL, "mmc1_cmd", NULL,
133 - NULL, NULL, NULL, "gpio1_31"),
134 - _AM33XX_MUXENTRY(GPMC_CSN3, 0,
135 +/**/ _AM33XX_MUXENTRY(GPMC_CSN1, 0,
136 + "gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
137 + "pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
138 +/**/ _AM33XX_MUXENTRY(GPMC_CSN2, 0,
139 + "gpmc_csn2", "gpmc_be1n", "mmc1_cmd", "pr1_edio_data_in7",
140 + "pr1_edio_data_out7", "pr1_pru1_pru_r30_13", "pr1_pru1_pru_r31_13", "gpio1_31"),
141 +/**/ _AM33XX_MUXENTRY(GPMC_CSN3, 0,
142 "gpmc_csn3", NULL, NULL, "mmc2_cmd",
143 - NULL, NULL, NULL, "gpio2_0"),
144 + "pr1_mii0_crs", "pr1_mdio_data", "EMU4", "gpio2_0"),
145 _AM33XX_MUXENTRY(GPMC_CLK, 0,
146 "gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
147 NULL, NULL, "mcasp0_fsr", "gpio2_1"),
148 @@ -155,33 +160,33 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
149 _AM33XX_MUXENTRY(LCD_DATA1, 0,
150 "lcd_data1", "gpmc_a1", NULL, NULL,
151 NULL, NULL, NULL, "gpio2_7"),
152 - _AM33XX_MUXENTRY(LCD_DATA2, 0,
153 - "lcd_data2", "gpmc_a2", NULL, NULL,
154 - NULL, NULL, NULL, "gpio2_8"),
155 - _AM33XX_MUXENTRY(LCD_DATA3, 0,
156 - "lcd_data3", "gpmc_a3", NULL, NULL,
157 - NULL, NULL, NULL, "gpio2_9"),
158 - _AM33XX_MUXENTRY(LCD_DATA4, 0,
159 - "lcd_data4", "gpmc_a4", NULL, NULL,
160 - NULL, NULL, NULL, "gpio2_10"),
161 - _AM33XX_MUXENTRY(LCD_DATA5, 0,
162 - "lcd_data5", "gpmc_a5", NULL, NULL,
163 - NULL, NULL, NULL, "gpio2_11"),
164 - _AM33XX_MUXENTRY(LCD_DATA6, 0,
165 - "lcd_data6", "gpmc_a6", NULL, NULL,
166 - NULL, NULL, NULL, "gpio2_12"),
167 - _AM33XX_MUXENTRY(LCD_DATA7, 0,
168 - "lcd_data7", "gpmc_a7", NULL, NULL,
169 - NULL, NULL, NULL, "gpio2_13"),
170 +/**/ _AM33XX_MUXENTRY(LCD_DATA2, 0,
171 + "lcd_data2", "gpmc_a2", "pr1_mii0_txd3", "ehrpwm2_tripzone_input",
172 + NULL, "pr1_pru1_pru_r30_2", "pr1_pru1_pru_r31_2", "gpio2_8"),
173 +/**/ _AM33XX_MUXENTRY(LCD_DATA3, 0,
174 + "lcd_data3", "gpmc_a3", "pr1_mii0_txd2","ehrpwm0_synco",
175 + NULL, "pr1_pru1_pru_r30_3", "pr1_pru1_pru_r31_3", "gpio2_9"),
176 +/**/ _AM33XX_MUXENTRY(LCD_DATA4, 0,
177 + "lcd_data4", "gpmc_a4", "pr1_mii0_txd1", "eQEP2A_in",
178 + NULL, "pr1_pru1_pru_r30_4", "pr1_pru1_pru_r31_4", "gpio2_10"),
179 +/**/ _AM33XX_MUXENTRY(LCD_DATA5, 0,
180 + "lcd_data5", "gpmc_a5", "pr1_mii0_txd0", "eqep2b_in",
181 + NULL, "pr1_pru1_pru_r30_5", "pr1_pru1_pru_r31_5", "gpio2_11"),
182 +/**/ _AM33XX_MUXENTRY(LCD_DATA6, 0,
183 + "lcd_data6", "gpmc_a6", "pr1_edio_data_in6", "eqep2_index",
184 + "pr1_edio_data_out6", "pr1_pru1_pru_r30_6", "pr1_pru1_pru_r31_6", "gpio2_12"),
185 +/**/ _AM33XX_MUXENTRY(LCD_DATA7, 0,
186 + "lcd_data7", "gpmc_a7", "pr1_edio_data_in7", "eqep2_strobe",
187 + "pr1_pru1_pru_r30_7", "pr1_pru_pru1_r30_7", "pr1_pru1_pru_r31_7", "gpio2_13"),
188 _AM33XX_MUXENTRY(LCD_DATA8, 0,
189 "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
190 NULL, NULL, "uart2_ctsn", "gpio2_14"),
191 _AM33XX_MUXENTRY(LCD_DATA9, 0,
192 "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
193 NULL, NULL, "uart2_rtsn", "gpio2_15"),
194 - _AM33XX_MUXENTRY(LCD_DATA10, 0,
195 - "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
196 - NULL, NULL, NULL, "gpio2_16"),
197 +/**/ _AM33XX_MUXENTRY(LCD_DATA10, 0,
198 + "lcd_data10", "gpmc_a14", "ehrpwm1A", "mcasp0_axr0",
199 + "mcasp0_axr0", "pr1_mii0_rxd1", "uart3_ctsn", "gpio2_16"),
200 _AM33XX_MUXENTRY(LCD_DATA11, 0,
201 "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
202 "mcasp0_axr2", NULL, NULL, "gpio2_17"),
203 @@ -197,18 +202,18 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
204 _AM33XX_MUXENTRY(LCD_DATA15, 0,
205 "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
206 "mcasp0_axr3", NULL, NULL, "gpio0_11"),
207 - _AM33XX_MUXENTRY(LCD_VSYNC, 0,
208 - "lcd_vsync", NULL, NULL, NULL,
209 - NULL, NULL, NULL, "gpio2_22"),
210 - _AM33XX_MUXENTRY(LCD_HSYNC, 0,
211 - "lcd_hsync", NULL, NULL, NULL,
212 - NULL, NULL, NULL, "gpio2_23"),
213 - _AM33XX_MUXENTRY(LCD_PCLK, 0,
214 - "lcd_pclk", NULL, NULL, NULL,
215 - NULL, NULL, NULL, "gpio2_24"),
216 - _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
217 - "lcd_ac_bias_en", NULL, NULL, NULL,
218 - NULL, NULL, NULL, "gpio2_25"),
219 +/**/ _AM33XX_MUXENTRY(LCD_VSYNC, 0,
220 + "lcd_vsync", "gpmc_a8", NULL, "pr1_edio_data_in2",
221 + "pr1_edio_data_out2", "pr1_pru1_pru_r30_8", "pr1_pru1_pru_r31_8", "gpio2_22"),
222 +/**/ _AM33XX_MUXENTRY(LCD_HSYNC, 0,
223 + "lcd_hsync", "gpmc_a9", NULL, "pr1_edio_data_in3",
224 + "pr1_edio_data_out3", "pr1_pru1_pru_r30_9", "pr1_pru1_pru_r31_9", "gpio2_23"),
225 +/**/ _AM33XX_MUXENTRY(LCD_PCLK, 0,
226 + "lcd_pclk", "gpmc_a10", "pr1_mii0_crs", "pr1_edio_data_in4",
227 + "pr1_edio_data_out4", "pr1_pru1_pru_r30_10", "pr1_pru1_pru_r31_10", "gpio2_24"),
228 +/**/ _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
229 + "lcd_ac_bias_en", "gpmc_a11", "pr1_mii1_crs", "pr1_edio_data_in5",
230 + "pr1_edio_data_out5", "pr1_pru1_pru_r30_11", "pr1_pru1_pru_r31_11", "gpio2_25"),
231 _AM33XX_MUXENTRY(MMC0_DAT3, 0,
232 "mmc0_dat3", NULL, NULL, NULL,
233 NULL, NULL, NULL, "gpio2_26"),
234 @@ -296,9 +301,9 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
235 _AM33XX_MUXENTRY(SPI0_CS1, 0,
236 "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
237 NULL, "mmc0_sdcd", NULL, "gpio0_6"),
238 - _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
239 - "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
240 - "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
241 +/**/ _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
242 + "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
243 + "spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
244 _AM33XX_MUXENTRY(UART0_CTSN, 0,
245 "uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
246 "spi1_d0", NULL, NULL, "gpio1_8"),
247 @@ -389,11 +394,11 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
248 _AM33XX_MUXENTRY(TRSTN, 0,
249 NULL, NULL, NULL, NULL,
250 NULL, NULL, NULL, NULL),
251 - _AM33XX_MUXENTRY(EMU0, 0,
252 - NULL, NULL, NULL, NULL,
253 +/**/ _AM33XX_MUXENTRY(EMU0, 0,
254 + "emu0", NULL, NULL, NULL,
255 NULL, NULL, NULL, "gpio3_7"),
256 - _AM33XX_MUXENTRY(EMU1, 0,
257 - NULL, NULL, NULL, NULL,
258 +/**/ _AM33XX_MUXENTRY(EMU1, 0,
259 + "emu1", NULL, NULL, NULL,
260 NULL, NULL, NULL, "gpio3_8"),
261 _AM33XX_MUXENTRY(RTC_XTALIN, 0,
262 NULL, NULL, NULL, NULL,
263 @@ -572,34 +577,34 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
264 _AM33XX_MUXENTRY(DDR_VTP, 0,
265 NULL, NULL, NULL, NULL,
266 NULL, NULL, NULL, NULL),
267 - _AM33XX_MUXENTRY(AIN0, 0,
268 +/**/ _AM33XX_MUXENTRY(AIN0, 0,
269 "ain0", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL),
271 - _AM33XX_MUXENTRY(AIN1, 0,
272 +/**/ _AM33XX_MUXENTRY(AIN1, 0,
273 "ain1", NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL),
275 - _AM33XX_MUXENTRY(AIN2, 0,
276 +/**/ _AM33XX_MUXENTRY(AIN2, 0,
277 "ain2", NULL, NULL, NULL,
278 NULL, NULL, NULL, NULL),
279 - _AM33XX_MUXENTRY(AIN3, 0,
280 +/**/ _AM33XX_MUXENTRY(AIN3, 0,
281 "ain3", NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL),
283 - _AM33XX_MUXENTRY(AIN4, 0,
284 +/**/ _AM33XX_MUXENTRY(AIN4, 0,
285 "ain4", NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL),
287 - _AM33XX_MUXENTRY(AIN5, 0,
288 +/**/ _AM33XX_MUXENTRY(AIN5, 0,
289 "ain5", NULL, NULL, NULL,
290 NULL, NULL, NULL, NULL),
291 - _AM33XX_MUXENTRY(AIN6, 0,
292 +/**/ _AM33XX_MUXENTRY(AIN6, 0,
293 "ain6", NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL),
295 - _AM33XX_MUXENTRY(AIN7, 0,
296 +/**/ _AM33XX_MUXENTRY(AIN7, 0,
297 "ain7", NULL, NULL, NULL,
298 NULL, NULL, NULL, NULL),
299 - _AM33XX_MUXENTRY(VREFP, 0,
300 +/**/ _AM33XX_MUXENTRY(VREFP, 0,
301 "vrefp", NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL),
303 - _AM33XX_MUXENTRY(VREFN, 0,
304 +/**/ _AM33XX_MUXENTRY(VREFN, 0,
305 "vrefn", NULL, NULL, NULL,
306 NULL, NULL, NULL, NULL),
307 { .reg_offset = OMAP_MUX_TERMINATOR },
308 --
309 1.7.10