linux-ti33x-psp 3.2: backport PM and USB fixes from PSP
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / psp / 0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch
1 From 824f30e3a045347806deedb75f16e96b057f430b Mon Sep 17 00:00:00 2001
2 From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3 Date: Tue, 22 May 2012 16:25:53 +0530
4 Subject: [PATCH 01/18] ARM: OMAP: AM33XX: Add missing EMIF register offsets
6 Add a couple of missing register offsets in the EMIF
7 header file. While here also fix the indentation issue.
9 Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
10 ---
11  arch/arm/plat-omap/include/plat/emif.h |   34 ++++++++++++++++----------------
12  1 files changed, 17 insertions(+), 17 deletions(-)
14 diff --git a/arch/arm/plat-omap/include/plat/emif.h b/arch/arm/plat-omap/include/plat/emif.h
15 index 314c126..445cbb1 100644
16 --- a/arch/arm/plat-omap/include/plat/emif.h
17 +++ b/arch/arm/plat-omap/include/plat/emif.h
18 @@ -17,23 +17,23 @@
19  #define __EMIF_H
20  
21  #define EMIF_MOD_ID_REV                        (0x0)
22 -#define EMIF4_0_SDRAM_STATUS            (0x04)
23 -#define EMIF4_0_SDRAM_CONFIG            (0x08)
24 -#define EMIF4_0_SDRAM_CONFIG2           (0x0C)
25 -#define EMIF4_0_SDRAM_REF_CTRL          (0x10)
26 -#define EMIF4_0_SDRAM_REF_CTRL_SHADOW   (0x14)
27 -#define EMIF4_0_SDRAM_TIM_1             (0x18)
28 -#define EMIF4_0_SDRAM_TIM_1_SHADOW      (0x1C)
29 -#define EMIF4_0_SDRAM_TIM_2             (0x20)
30 -#define EMIF4_0_SDRAM_TIM_2_SHADOW      (0x24)
31 -#define EMIF4_0_SDRAM_TIM_3             (0x28)
32 -#define EMIF4_0_SDRAM_TIM_3_SHADOW      (0x2C)
33 -#define EMIF4_0_SDRAM_MGMT_CTRL         (0x38)
34 -#define EMIF4_0_SDRAM_MGMT_CTRL_SHD     (0x3C)
35 -#define EMIF4_0_DDR_PHY_CTRL_1          (0xE4)
36 -#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW   (0xE8)
37 -#define EMIF4_0_DDR_PHY_CTRL_2          (0xEC)
38 -#define EMIF4_0_IODFT_TLGC              (0x60)
39 +#define EMIF4_0_SDRAM_STATUS           (0x04)
40 +#define EMIF4_0_SDRAM_CONFIG           (0x08)
41 +#define EMIF4_0_SDRAM_CONFIG2          (0x0C)
42 +#define EMIF4_0_SDRAM_REF_CTRL         (0x10)
43 +#define EMIF4_0_SDRAM_REF_CTRL_SHADOW  (0x14)
44 +#define EMIF4_0_SDRAM_TIM_1            (0x18)
45 +#define EMIF4_0_SDRAM_TIM_1_SHADOW     (0x1C)
46 +#define EMIF4_0_SDRAM_TIM_2            (0x20)
47 +#define EMIF4_0_SDRAM_TIM_2_SHADOW     (0x24)
48 +#define EMIF4_0_SDRAM_TIM_3            (0x28)
49 +#define EMIF4_0_SDRAM_TIM_3_SHADOW     (0x2C)
50 +#define EMIF4_0_SDRAM_MGMT_CTRL                (0x38)
51 +#define EMIF4_0_SDRAM_MGMT_CTRL_SHADOW (0x3C)
52 +#define EMIF4_0_IODFT_TLGC             (0x60)
53 +#define EMIF4_0_ZQ_CONFIG              (0xC8)
54 +#define EMIF4_0_DDR_PHY_CTRL_1         (0xE4)
55 +#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW  (0xE8)
56  
57  #define SELF_REFRESH_ENABLE(m)         (0x2 << 8 | (m << 4))
58  #define SELF_REFRESH_DISABLE           (0x0 << 8)
59 -- 
60 1.7.7.6