linux-ti33x-psp 3.2: backport PM and USB fixes from PSP
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / psp / 0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch
1 From 49b0e8259aec1ffb11e0d2be13fc89fc84162fac Mon Sep 17 00:00:00 2001
2 From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3 Date: Tue, 22 May 2012 12:19:21 +0530
4 Subject: [PATCH 03/18] ARM: OMAP: AM33XX: PM: Skip DDR PHY reconfiguration in
5  resume
7 DDR PHY registers were earlier being reconfigured in the resume
8 path. This is not necessary since these registers lie in the
9 WKUP domain and retain their content across various low power
10 state. Skipping the reconfiguration will also enabling in getting
11 a single kernel image to work for boards with different memory
12 types.
14 Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
15 ---
16  arch/arm/mach-omap2/pm33xx.h    |   75 +------------
17  arch/arm/mach-omap2/sleep33xx.S |  245 +--------------------------------------
18  2 files changed, 7 insertions(+), 313 deletions(-)
20 diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
21 index 7b3504b..f52e54c 100644
22 --- a/arch/arm/mach-omap2/pm33xx.h
23 +++ b/arch/arm/mach-omap2/pm33xx.h
24 @@ -60,59 +60,6 @@ struct am33xx_padconf {
25  #define M3_STATE_MSG_FOR_LP            2
26  #define M3_STATE_MSG_FOR_RESET         3
27  
28 -/* DDR offsets */
29 -#define DDR_CMD0_IOCTRL                        (AM33XX_CTRL_BASE + 0x1404)
30 -#define DDR_CMD1_IOCTRL                        (AM33XX_CTRL_BASE + 0x1408)
31 -#define DDR_CMD2_IOCTRL                        (AM33XX_CTRL_BASE + 0x140C)
32 -#define DDR_DATA0_IOCTRL               (AM33XX_CTRL_BASE + 0x1440)
33 -#define DDR_DATA1_IOCTRL               (AM33XX_CTRL_BASE + 0x1444)
34 -
35 -#define DDR_IO_CTRL                    (AM33XX_CTRL_BASE + 0x0E04)
36 -#define VTP0_CTRL_REG                  (AM33XX_CTRL_BASE + 0x0E0C)
37 -#define DDR_CKE_CTRL                   (AM33XX_CTRL_BASE + 0x131C)
38 -#define DDR_PHY_BASE_ADDR              (AM33XX_CTRL_BASE + 0x2000)
39 -
40 -#define CMD0_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x01C)
41 -#define CMD0_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x020)
42 -#define CMD0_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x024)
43 -#define CMD0_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x028)
44 -#define CMD0_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x02C)
45 -
46 -#define CMD1_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x050)
47 -#define CMD1_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x054)
48 -#define CMD1_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x058)
49 -#define CMD1_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x05C)
50 -#define CMD1_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x060)
51 -
52 -#define CMD2_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x084)
53 -#define CMD2_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x088)
54 -#define CMD2_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x08C)
55 -#define CMD2_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x090)
56 -#define CMD2_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x094)
57 -
58 -#define DATA0_RD_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0C8)
59 -#define DATA0_RD_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0CC)
60 -
61 -#define DATA0_WR_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0DC)
62 -#define DATA0_WR_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0E0)
63 -
64 -#define DATA0_WRLVL_INIT_RATIO_0       (DDR_PHY_BASE_ADDR + 0x0F0)
65 -#define DATA0_WRLVL_INIT_RATIO_1       (DDR_PHY_BASE_ADDR + 0x0F4)
66 -
67 -#define DATA0_GATELVL_INIT_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0FC)
68 -#define DATA0_GATELVL_INIT_RATIO_1     (DDR_PHY_BASE_ADDR + 0x100)
69 -
70 -#define DATA0_FIFO_WE_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x108)
71 -#define DATA0_FIFO_WE_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x10C)
72 -
73 -#define DATA0_WR_DATA_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x120)
74 -#define DATA0_WR_DATA_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x124)
75 -
76 -#define DATA0_DLL_LOCK_DIFF_0          (DDR_PHY_BASE_ADDR + 0x138)
77 -
78 -#define DATA0_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x134)
79 -#define DATA1_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x1D8)
80 -
81  /* Temp placeholder for the values we want in the registers */
82  #define EMIF_READ_LATENCY      0x100005        /* Enable Dynamic Power Down */
83  #define EMIF_TIM1              0x0666B3C9
84 @@ -124,28 +71,12 @@ struct am33xx_padconf {
85  #define EMIF_SDRAM             0x00004650
86  #define EMIF_PHYCFG            0x2
87  
88 -#define DDR2_DLL_LOCK_DIFF     0x0
89 -#define DDR2_RD_DQS            0x12
90 -#define DDR2_PHY_FIFO_WE       0x80
91 -
92 -#define DDR_PHY_RESET          (0x1 << 10)
93 -#define DDR_PHY_READY          (0x1 << 2)
94 -#define DDR2_RATIO             0x80
95 -#define CMD_FORCE              0x00
96 -#define CMD_DELAY              0x00
97 -
98 -#define DDR2_INVERT_CLKOUT     0x00
99 -#define DDR2_WR_DQS            0x00
100 -#define DDR2_PHY_WRLVL         0x00
101 -#define DDR2_PHY_GATELVL       0x00
102 -#define DDR2_PHY_WR_DATA       0x40
103 -#define PHY_RANK0_DELAY                0x01
104 -#define PHY_DLL_LOCK_DIFF      0x0
105 -#define DDR_IOCTRL_VALUE       0x18B
107  #define VTP_CTRL_READY         (0x1 << 5)
108  #define VTP_CTRL_ENABLE                (0x1 << 6)
109  #define VTP_CTRL_LOCK_EN       (0x1 << 4)
110  #define VTP_CTRL_START_EN      (0x1)
111  
112 +#define DDR_IO_CTRL                    (AM33XX_CTRL_BASE + 0x0E04)
113 +#define VTP0_CTRL_REG                  (AM33XX_CTRL_BASE + 0x0E0C)
115  #endif
116 diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
117 index 9c57335..4c601b11 100644
118 --- a/arch/arm/mach-omap2/sleep33xx.S
119 +++ b/arch/arm/mach-omap2/sleep33xx.S
120 @@ -273,21 +273,9 @@ ENTRY(am33xx_resume_from_deep_sleep)
121         bic     r1, r1, #28
122         str     r1, [r0]
123  
124 -/*
125 - * Instead of harcoding the EMIF and DDR PHY related settings
126 - * in this file, the sane thing to do would have been to backup
127 - * the register contents during suspend and restore it back in
128 - * the resume path. However, due to the Si errata related to
129 - * DDR PHY registers, these registers are read-only. So, we'll
130 - * need to hardcode atleast the DDR PHY configuration over here.
131 - * We _could_ back up the EMIF registers but in order to be
132 - * consistent with the DDR setup procedure we skip this for now.
133 - * The person updating the DDR PHY config values is expected
134 - * to update the EMIF config values also.
135 - */
136  
137  config_vtp:
138 -       ldr     r0, vtp0_addr
139 +       ldr     r0, phys_ddr_vtp_ctrl
140         ldr     r1, [r0]
141         mov     r2, #0x0        @ clear the register
142         str     r2, [r0]
143 @@ -312,179 +300,6 @@ poll_vtp_ready:
144         tst     r1, #(1 << 5)
145         beq     poll_vtp_ready
146  
147 -cmd_macro_config:
148 -       ldr     r0, ddr_phy_base
149 -       ldr     r1, [r0]
150 -       ldr     r2, ddr2_ratio_val
151 -       mov     r3, r2
152 -       @ TODO: Need to use proper variable here
153 -       mov     r4, #0
154 -       str     r3, [r0, #28]   @cmd0
155 -       str     r4, [r0, #32]
156 -       str     r4, [r0, #36]
157 -       str     r4, [r0, #40]
158 -       str     r4, [r0, #44]
159 -       str     r3, [r0, #80]   @cmd1
160 -       str     r4, [r0, #84]
161 -       str     r4, [r0, #88]
162 -       str     r4, [r0, #92]
163 -       str     r4, [r0, #96]
164 -       str     r3, [r0, #132]  @cmd2
165 -       str     r4, [r0, #136]
166 -       str     r4, [r0, #140]
167 -       str     r4, [r0, #144]
168 -       str     r4, [r0, #148]
170 -       mov     r3, #0x0
171 -       bl      data_macro_config
172 -       mov     r3, #0xa4
173 -       bl      data_macro_config
174 -       b       setup_rank_delays
176 -data_macro_config:
177 -       ldr     r0, ddr_phy_base
178 -       add     r0, r0, r3
179 -rd_dqs:
180 -       ldr     r1, data0_rd_dqs_slave_ratio0_val
181 -       mov     r2, r1
182 -       /* shift by 30, 20, 10 and orr */
183 -       mov     r5, r2, lsl #10
184 -       mov     r6, r2, lsl #20
185 -       mov     r7, r2, lsl #30
186 -       orr     r2, r2, r5
187 -       orr     r2, r2, r6
188 -       orr     r2, r2, r7
189 -       /* Done with crazy bit ops. store it now */
190 -       str     r2, [r0, #200]
191 -       ldr     r1, data0_rd_dqs_slave_ratio1_val
192 -       mov     r2, r1
193 -       mov     r5, r2, lsr #2
194 -       mov     r2, r5
195 -       str     r2, [r0, #204]
196 -wr_dqs:
197 -       ldr     r1, data0_wr_dqs_slave_ratio0_val
198 -       mov     r2, r1
199 -       /* shift by 30, 20, 10 and orr */
200 -       mov     r5, r2, lsl #10
201 -       mov     r6, r2, lsl #20
202 -       mov     r7, r2, lsl #30
203 -       orr     r2, r2, r5
204 -       orr     r2, r2, r6
205 -       orr     r2, r2, r7
206 -       /* Done with crazy bit ops. store it now */
207 -       str     r2, [r0, #220]
208 -       ldr     r1, data0_wr_dqs_slave_ratio1_val
209 -       mov     r2, r1
210 -       mov     r5, r2, lsr #2
211 -       mov     r2, r5
212 -       str     r2, [r0, #224]
213 -wr_lvl:
214 -       ldr     r1, data0_wr_lvl_init_ratio0_val
215 -       mov     r2, r1
216 -       /* shift by 30, 20, 10 and orr */
217 -       mov     r5, r2, lsl #10
218 -       mov     r6, r2, lsl #20
219 -       mov     r7, r2, lsl #30
220 -       orr     r2, r2, r5
221 -       orr     r2, r2, r6
222 -       orr     r2, r2, r7
223 -       /* Done with crazy bit ops. store it now */
224 -       str     r2, [r0, #240]
225 -       ldr     r1, data0_wr_lvl_init_ratio1_val
226 -       mov     r2, r1
227 -       mov     r5, r2, lsr #2
228 -       mov     r2, r5
229 -       str     r2, [r0, #244]
230 -gate_lvl:
231 -       ldr     r1, data0_gate_lvl_init_ratio0_val
232 -       mov     r2, r1
233 -       /* shift by 30, 20, 10 and orr */
234 -       mov     r5, r2, lsl #10
235 -       mov     r6, r2, lsl #20
236 -       mov     r7, r2, lsl #30
237 -       orr     r2, r2, r5
238 -       orr     r2, r2, r6
239 -       orr     r2, r2, r7
240 -       /* Done with crazy bit ops. store it now */
241 -       str     r2, [r0, #248]
242 -       ldr     r1, data0_gate_lvl_init_ratio1_val
243 -       mov     r2, r1
244 -       mov     r5, r2, lsr #2
245 -       mov     r2, r5
246 -       str     r2, [r0, #256]
247 -we_slv:
248 -       ldr     r1, data0_wr_lvl_slave_ratio0_val
249 -       mov     r2, r1
250 -       /* shift by 30, 20, 10 and orr */
251 -       mov     r5, r2, lsl #10
252 -       mov     r6, r2, lsl #20
253 -       mov     r7, r2, lsl #30
254 -       orr     r2, r2, r5
255 -       orr     r2, r2, r6
256 -       orr     r2, r2, r7
257 -       /* Done with crazy bit ops. store it now */
258 -       str     r2, [r0, #264]
259 -       ldr     r1, data0_wr_lvl_slave_ratio1_val
260 -       mov     r2, r1
261 -       mov     r5, r2, lsr #2
262 -       mov     r2, r5
263 -       str     r2, [r0, #268]
264 -wr_data:
265 -       ldr     r1, data0_wr_data_slave_ratio0_val
266 -       mov     r2, r1
267 -       /* shift by 30, 20, 10 and orr */
268 -       mov     r5, r2, lsl #10
269 -       mov     r6, r2, lsl #20
270 -       mov     r7, r2, lsl #30
271 -       orr     r2, r2, r5
272 -       orr     r2, r2, r6
273 -       orr     r2, r2, r7
274 -       /* Done with crazy bit ops. store it now */
275 -       str     r2, [r0, #288]
276 -       ldr     r1, data0_wr_data_slave_ratio1_val
277 -       mov     r2, r1
278 -       mov     r5, r2, lsr #2
279 -       mov     r2, r5
280 -       str     r2, [r0, #292]
281 -dll_lock:
282 -       ldr     r1, data0_dll_lock_diff_val
283 -       mov     r2, r1
284 -       str     r2, [r0, #312]
286 -setup_rank_delays:
287 -       ldr     r1, data0_rank0_delay0_val
288 -       mov     r2, r1
289 -       str     r2, [r0, #308]
290 -       ldr     r1, data1_rank0_delay1_val
291 -       mov     r2, r1
292 -       str     r2, [r0, #472]
294 -setup_io_ctrl:
295 -       ldr     r0, control_base
296 -       ldr     r1, ddr_ioctrl_val
297 -       mov     r2, r1
298 -       ldr     r4, ddr_cmd_offset
299 -       mov     r3, r4
300 -       str     r2, [r0, r3]    @cmd0 0x1404
301 -       add     r3, r3, #4
302 -       str     r2, [r0, r3]    @cmd1 0x1408
303 -       add     r3, r3, #4
304 -       str     r2, [r0, r3]    @cmd2 0x140c
305 -       ldr     r4, ddr_data_offset
306 -       mov     r3, r4
307 -       str     r2, [r0, r3]    @data0 0x1440
308 -       add     r3, r3, #4
309 -       str     r2, [r0, r3]    @data1 0x1444
311 -misc_config:
312 -       ldr     r1, ddr_io_ctrl_addr
313 -       ldr     r2, [r1]
314 -       and     r2, #0xefffffff
315 -       str     r2, [r1]
316 -       ldr     r1, ddr_cke_addr
317 -       ldr     r2, [r1]
318 -       orr     r2, #0x00000001
319 -       str     r2, [r1]
320  
321  config_emif_timings:
322         mov     r3, #1275068416 @ 0x4c000000
323 @@ -628,61 +443,6 @@ module_disabled_val:
324         .word   0x30000
325  
326  /* DDR related stuff */
327 -vtp0_addr:
328 -       .word   VTP0_CTRL_REG
329 -vtp_enable:
330 -       .word   VTP_CTRL_ENABLE
331 -vtp_start_en:
332 -       .word   VTP_CTRL_START_EN
333 -vtp_ready:
334 -       .word   VTP_CTRL_READY
336 -ddr_phy_base:
337 -       .word   DDR_PHY_BASE_ADDR
338 -ddr2_ratio_val:
339 -       .word   DDR2_RATIO
340 -data0_rd_dqs_slave_ratio0_val:
341 -       .word   DDR2_RD_DQS
342 -data0_rd_dqs_slave_ratio1_val:
343 -       .word   DDR2_RD_DQS
344 -data0_wr_dqs_slave_ratio0_val:
345 -       .word   DDR2_WR_DQS
346 -data0_wr_dqs_slave_ratio1_val:
347 -       .word   DDR2_WR_DQS
348 -data0_wr_lvl_init_ratio0_val:
349 -       .word   DDR2_PHY_WRLVL
350 -data0_wr_lvl_init_ratio1_val:
351 -       .word   DDR2_PHY_WRLVL
352 -data0_gate_lvl_init_ratio0_val:
353 -       .word   DDR2_PHY_GATELVL
354 -data0_gate_lvl_init_ratio1_val:
355 -       .word   DDR2_PHY_GATELVL
356 -data0_wr_lvl_slave_ratio0_val:
357 -       .word   DDR2_PHY_FIFO_WE
358 -data0_wr_lvl_slave_ratio1_val:
359 -       .word   DDR2_PHY_FIFO_WE
360 -data0_wr_data_slave_ratio0_val:
361 -       .word   DDR2_PHY_WR_DATA
362 -data0_wr_data_slave_ratio1_val:
363 -       .word   DDR2_PHY_WR_DATA
364 -data0_dll_lock_diff_val:
365 -       .word   PHY_DLL_LOCK_DIFF
367 -data0_rank0_delay0_val:
368 -       .word   PHY_RANK0_DELAY
369 -data1_rank0_delay1_val:
370 -       .word   PHY_RANK0_DELAY
372 -control_base:
373 -       .word   AM33XX_CTRL_BASE
374 -ddr_io_ctrl_addr:
375 -       .word   DDR_IO_CTRL
376 -ddr_ioctrl_val:
377 -       .word   0x18B
378 -ddr_cmd_offset:
379 -       .word   0x1404
380 -ddr_data_offset:
381 -       .word   0x1440
382  virt_ddr_io_ctrl:
383         .word   AM33XX_CTRL_REGADDR(0x0E04)
384  phys_ddr_io_ctrl:
385 @@ -691,6 +451,9 @@ virt_ddr_vtp_ctrl:
386         .word   AM33XX_CTRL_REGADDR(0x0E0C)
387  phys_ddr_vtp_ctrl:
388         .word   VTP0_CTRL_REG
389 +vtp_enable:
390 +       .word   VTP_CTRL_ENABLE
392  virt_ddr_io_pull1:
393         .word   AM33XX_CTRL_REGADDR(0x1440)
394  phys_ddr_io_pull1:
395 -- 
396 1.7.7.6