linux-ti33x-psp 3.2: backport PM and USB fixes from PSP
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / psp / 0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch
1 From 334c051e4d0b3214136dbee1b0a52e2d29747c0a Mon Sep 17 00:00:00 2001
2 From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3 Date: Tue, 22 May 2012 12:24:55 +0530
4 Subject: [PATCH 04/18] ARM: OMAP: AM33XX: PM: Save and restore EMIF registers
6 The EMIF configuration parameters were earlier harcoded
7 under the assumption that the person updating the DDR PHY
8 configuration values will update the EMIF parameters also.
10 Now that the DDR PHY reconfiguration has been dropped, this
11 restriction can also go away by adopting a save and restore
12 mechanism of these registers.
14 At the same time switch to macros for EMIF register offsets
15 to improve readability.
17 Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
18 ---
19  arch/arm/mach-omap2/pm33xx.h    |   11 ---
20  arch/arm/mach-omap2/sleep33xx.S |  141 +++++++++++++++++++++------------------
21  2 files changed, 75 insertions(+), 77 deletions(-)
23 diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
24 index f52e54c..a40f4d4 100644
25 --- a/arch/arm/mach-omap2/pm33xx.h
26 +++ b/arch/arm/mach-omap2/pm33xx.h
27 @@ -60,17 +60,6 @@ struct am33xx_padconf {
28  #define M3_STATE_MSG_FOR_LP            2
29  #define M3_STATE_MSG_FOR_RESET         3
30  
31 -/* Temp placeholder for the values we want in the registers */
32 -#define EMIF_READ_LATENCY      0x100005        /* Enable Dynamic Power Down */
33 -#define EMIF_TIM1              0x0666B3C9
34 -#define EMIF_TIM2              0x243631CA
35 -#define EMIF_TIM3              0x0000033F
36 -#define EMIF_SDCFG             0x41805332
37 -#define EMIF_SDREF             0x0000081a
38 -#define EMIF_SDMGT             0x80000000
39 -#define EMIF_SDRAM             0x00004650
40 -#define EMIF_PHYCFG            0x2
41 -
42  #define VTP_CTRL_READY         (0x1 << 5)
43  #define VTP_CTRL_ENABLE                (0x1 << 6)
44  #define VTP_CTRL_LOCK_EN       (0x1 << 4)
45 diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
46 index 4c601b11..b7a1612 100644
47 --- a/arch/arm/mach-omap2/sleep33xx.S
48 +++ b/arch/arm/mach-omap2/sleep33xx.S
49 @@ -71,6 +71,26 @@ wait_pll_lock_\name:
50  
51         str     r0, emif_addr_virt
52  
53 +       /* Save EMIF configuration */
54 +       ldr     r1, [r0, #EMIF4_0_SDRAM_CONFIG]
55 +       str     r1, emif_sdcfg_val
56 +       ldr     r1, [r0, #EMIF4_0_SDRAM_REF_CTRL]
57 +       str     r1, emif_ref_ctrl_val
58 +       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_1]
59 +       str     r1, emif_timing1_val
60 +       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_2]
61 +       str     r1, emif_timing2_val
62 +       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_3]
63 +       str     r1, emif_timing3_val
64 +       ldr     r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL]
65 +       str     r1, emif_pmcr_val
66 +       ldr     r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
67 +       str     r1, emif_pmcr_shdw_val
68 +       ldr     r1, [r0, #EMIF4_0_ZQ_CONFIG]
69 +       str     r1, emif_zqcfg_val
70 +       ldr     r1, [r0, #EMIF4_0_DDR_PHY_CTRL_1]
71 +       str     r1, emif_rd_lat_val
72 +
73         /* Ensure that all the writes to DDR leave the A8 */
74         dsb
75         dmb
76 @@ -302,58 +322,52 @@ poll_vtp_ready:
77  
78  
79  config_emif_timings:
80 -       mov     r3, #1275068416 @ 0x4c000000
81 -disable_sr:
82 -       mov     r4, #0
83 -       str     r4, [r3, #56]   @ 0x38
84 +       ldr     r3, emif_phys_addr
85         ldr     r4, emif_rd_lat_val
86 -       mov     r2, r4
87  rd_lat:
88 -       str     r2, [r3, #228]  @ 0xe4
89 -       str     r2, [r3, #232]  @ 0xe8
90 -       str     r2, [r3, #236]  @ 0xec
91 +       str     r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1]
92 +       str     r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1_SHADOW]
93  timing1:
94         ldr     r4, emif_timing1_val
95 -       mov     r2, r4
96 -       str     r2, [r3, #24]
97 -       str     r2, [r3, #28]
98 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_1]
99 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_1_SHADOW]
100  timing2:
101         ldr     r4, emif_timing2_val
102 -       mov     r2, r4
103 -       str     r2, [r3, #32]
104 -       str     r2, [r3, #36]   @ 0x24
105 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_2]
106 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_2_SHADOW]
107  timing3:
108         ldr     r4, emif_timing3_val
109 -       mov     r2, r4
110 -       str     r2, [r3, #40]   @ 0x28
111 -       str     r2, [r3, #44]   @ 0x2c
112 -sdcfg1:
113 -       ldr     r4, emif_sdcfg_val
114 -       mov     r2, r4
115 -       str     r2, [r3, #8]
116 -       str     r2, [r3, #12]
117 -ref_ctrl_const:
118 -       ldr     r4, emif_ref_ctrl_const_val
119 -       mov     r2, r4
120 -       str     r2, [r3, #16]
121 -       str     r2, [r3, #20]
123 -       /* GEL had a loop with init value of 5000 */
124 -       mov     r0, #0x1000
125 -wait_loop1:
126 -       subs    r0, r0, #1
127 -       bne     wait_loop1
129 -ref_ctrl_actual:
130 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_3]
131 +       str     r4, [r3, #EMIF4_0_SDRAM_TIM_3_SHADOW]
132 +sdram_ref_ctrl:
133         ldr     r4, emif_ref_ctrl_val
134 -       mov     r2, r4
135 -       str     r2, [r3, #16]
136 -       str     r2, [r3, #20]
137 -sdcfg2:
138 +       str     r4, [r3, #EMIF4_0_SDRAM_REF_CTRL]
139 +       str     r4, [r3, #EMIF4_0_SDRAM_REF_CTRL_SHADOW]
140 +pmcr:
141 +       ldr     r4, emif_pmcr_val
142 +       str     r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL]
143 +pmcr_shdw:
144 +       ldr     r4, emif_pmcr_shdw_val
145 +       str     r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
147 +       /*
148 +        * Output impedence calib needed only for DDR3
149 +        * but since the initial state of this will be
150 +        * disabled for DDR2 no harm in restoring the
151 +        * old configuration
152 +        */
153 +zqcfg:
154 +       ldr     r4, emif_zqcfg_val
155 +       str     r4, [r3, #EMIF4_0_ZQ_CONFIG]
157 +       /*
158 +        * A write to SDRAM CONFIG register triggers
159 +        * an init sequence and hence it must be done
160 +        * at the end
161 +        */
162 +sdcfg:
163         ldr     r4, emif_sdcfg_val
164 -       mov     r2, r4
165 -       str     r2, [r3, #8]
166 -       str     r2, [r3, #12]
167 +       str     r4, [r3, #EMIF4_0_SDRAM_CONFIG]
168  
169         /* Back from la-la-land. Kill some time for sanity to settle in */
170         mov     r0, #0x1000
171 @@ -377,10 +391,8 @@ emif_addr_func:
172  emif_phys_addr:
173         .word   AM33XX_EMIF0_BASE
174  
175 -emif_pm_ctrl:
176 -       .word EMIF4_0_SDRAM_MGMT_CTRL
177  ddr_start:
178 -       .word PAGE_OFFSET
179 +       .word   PAGE_OFFSET
180  
181  virt_mpu_idlest:
182         .word   AM33XX_CM_IDLEST_DPLL_MPU
183 @@ -467,37 +479,34 @@ virt_ddr_io_pull3:
184  phys_ddr_io_pull3:
185         .word   AM33XX_CTRL_BASE + (0x1448)
186  
187 -ddr_cke_addr:
188 -       .word   DDR_CKE_CTRL
189 -emif_rd_lat_val:
190 -       .word   EMIF_READ_LATENCY
191 -emif_timing1_val:
192 -       .word   EMIF_TIM1
193 -emif_timing2_val:
194 -       .word   EMIF_TIM2
195 -emif_timing3_val:
196 -       .word   EMIF_TIM3
197 -emif_sdcfg_val:
198 -       .word   EMIF_SDCFG
199 -emif_ref_ctrl_const_val:
200 -       .word   0x4650
201 -emif_ref_ctrl_val:
202 -       .word   EMIF_SDREF
204  susp_io_pull:
205         .word   0x3FF00003
206  resume_io_pull1:
207         .word   0x18B
208  resume_io_pull2:
209         .word   0x18B
210 -dyn_pd_val:
211 -       .word   0x100000
212 -susp_sdram_config:
213 -       .word   0x40805332
214  susp_vtp_ctrl_val:
215         .word   0x10117
216  emif_addr_virt:
217         .word   0xDEADBEEF
218 +emif_rd_lat_val:
219 +       .word   0xDEADBEEF
220 +emif_timing1_val:
221 +       .word   0xDEADBEEF
222 +emif_timing2_val:
223 +       .word   0xDEADBEEF
224 +emif_timing3_val:
225 +       .word   0xDEADBEEF
226 +emif_sdcfg_val:
227 +       .word   0xDEADBEEF
228 +emif_ref_ctrl_val:
229 +       .word   0xDEADBEEF
230 +emif_zqcfg_val:
231 +       .word   0xDEADBEEF
232 +emif_pmcr_val:
233 +       .word   0xDEADBEEF
234 +emif_pmcr_shdw_val:
235 +       .word   0xDEADBEEF
236  
237  
238  ENTRY(am33xx_do_wfi_sz)
239 -- 
240 1.7.7.6