linux-ti33x-psp 3.2: backport PM and USB fixes from PSP
[glsdk/meta-ti-glsdk.git] / recipes-kernel / linux / linux-ti33x-psp-3.2 / psp / 0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch
1 From d3ec36ec2c36ecb234c5a575b713205473e6cab8 Mon Sep 17 00:00:00 2001
2 From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3 Date: Tue, 22 May 2012 12:43:01 +0530
4 Subject: [PATCH 06/18] ARM: OMAP: AM33XX: PM: Restore the PLLs to pre-suspend
5  state
7 In some scenarios all the PLLs (especially Display) might not be
8 in a locked state when the suspend process starts. Trying to relock
9 a PLL in MN-bypass mode without a proper set of M and N values results
10 into the PLLs never locking and the resume process hanging. Fix this
11 by restoring the PLLs to the mode that they were in before the suspend
12 process started.
14 Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
15 ---
16  arch/arm/mach-omap2/sleep33xx.S |   57 +++++++++++++++++++++++++-------------
17  1 files changed, 37 insertions(+), 20 deletions(-)
19 diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
20 index 79a9e39..4db3a94 100644
21 --- a/arch/arm/mach-omap2/sleep33xx.S
22 +++ b/arch/arm/mach-omap2/sleep33xx.S
23 @@ -37,10 +37,11 @@
24  ENTRY(am33xx_do_wfi)
25         stmfd   sp!, {r4 - r11, lr}     @ save registers on stack
26  
27 -       .macro  pll_bypass, name, clk_mode_addr, idlest_addr
28 +       .macro  pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
29  pll_bypass_\name:
30         ldr     r0, \clk_mode_addr
31         ldr     r1, [r0]
32 +       str     r1, clk_mode_\pll_mode
33         bic     r1, r1, #(7 << 0)
34         orr     r1, r1, #0x5
35         str     r1, [r0]
36 @@ -51,18 +52,21 @@ wait_pll_bypass_\name:
37         bne     wait_pll_bypass_\name
38         .endm
39  
40 -       .macro  pll_lock, name, clk_mode_addr, idlest_addr
41 +       .macro  pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
42  pll_lock_\name:
43         ldr     r0, \clk_mode_addr
44 -       ldr     r1, [r0]
45 -       bic     r1, r1, #(7 << 0)
46 -       orr     r1, r1, #0x7
47 +       ldr     r1, clk_mode_\pll_mode
48         str     r1, [r0]
49 +       and     r1, r1, #0x7
50 +       cmp     r1, #0x7
51 +       bne     pll_mode_restored_\name
52         ldr     r0, \idlest_addr
53  wait_pll_lock_\name:
54         ldr     r1, [r0]
55         ands    r1, #0x1
56         beq     wait_pll_lock_\name
57 +pll_mode_restored_\name:
58 +       nop
59         .endm
60  
61         /* EMIF config for low power mode */
62 @@ -154,11 +158,11 @@ wait_emif_disable:
63         str     r1, [r0]
64  
65         /* Put the PLLs in bypass mode */
66 -       pll_bypass      core, virt_core_clk_mode, virt_core_idlest
67 -       pll_bypass      ddr, virt_ddr_clk_mode, virt_ddr_idlest
68 -       pll_bypass      disp, virt_disp_clk_mode, virt_disp_idlest
69 -       pll_bypass      per, virt_per_clk_mode, virt_per_idlest
70 -       pll_bypass      mpu, virt_mpu_clk_mode, virt_mpu_idlest
71 +       pll_bypass      core, virt_core_clk_mode, virt_core_idlest, core_val
72 +       pll_bypass      ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
73 +       pll_bypass      disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
74 +       pll_bypass      per, virt_per_clk_mode, virt_per_idlest, per_val
75 +       pll_bypass      mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
76  
77         dsb
78         dmb
79 @@ -176,15 +180,17 @@ wait_emif_disable:
80         nop
81         nop
82         nop
83 +       nop
84 +       nop
85  
86         /* We come here in case of an abort */
87  
88         /* Relock the PLLs */
89 -       pll_lock        mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest
90 -       pll_lock        per_abt, virt_per_clk_mode, virt_per_idlest
91 -       pll_lock        disp_abt, virt_disp_clk_mode, virt_disp_idlest
92 -       pll_lock        ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest
93 -       pll_lock        core_abt, virt_core_clk_mode, virt_core_idlest
94 +       pll_lock        mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
95 +       pll_lock        per_abt, virt_per_clk_mode, virt_per_idlest, per_val
96 +       pll_lock        disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
97 +       pll_lock        ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
98 +       pll_lock        core_abt, virt_core_clk_mode, virt_core_idlest, core_val
99  
100         /* Disable SRAM LDO ret mode */
101         ldr     r0, virt_sram_ldo_addr
102 @@ -259,11 +265,11 @@ ENTRY(am33xx_resume_offset)
103  
104  ENTRY(am33xx_resume_from_deep_sleep)
105         /* Take the PLLs out of LP_BYPASS */
106 -       pll_lock        mpu, phys_mpu_clk_mode, phys_mpu_idlest
107 -       pll_lock        per, phys_per_clk_mode, phys_per_idlest
108 -       pll_lock        disp, phys_disp_clk_mode, phys_disp_idlest
109 -       pll_lock        ddr, phys_ddr_clk_mode, phys_ddr_idlest
110 -       pll_lock        core, phys_core_clk_mode, phys_core_idlest
111 +       pll_lock        mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
112 +       pll_lock        per, phys_per_clk_mode, phys_per_idlest, per_val
113 +       pll_lock        disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
114 +       pll_lock        ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
115 +       pll_lock        core, phys_core_clk_mode, phys_core_idlest, core_val
116  
117         /* Disable SRAM LDO ret mode */
118         ldr     r0, phys_sram_ldo_addr
119 @@ -508,6 +514,17 @@ emif_pmcr_val:
120  emif_pmcr_shdw_val:
121         .word   0xDEADBEEF
122  
123 +/* PLL CLKMODE before suspend */
124 +clk_mode_mpu_val:
125 +       .word   0xDEADBEEF
126 +clk_mode_per_val:
127 +       .word   0xDEADBEEF
128 +clk_mode_disp_val:
129 +       .word   0xDEADBEEF
130 +clk_mode_ddr_val:
131 +       .word   0xDEADBEEF
132 +clk_mode_core_val:
133 +       .word   0xDEADBEEF
134  
135  ENTRY(am33xx_do_wfi_sz)
136         .word   . - am33xx_do_wfi
137 -- 
138 1.7.7.6