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raw | patch | inline | side by side (parent: 60f1c4f)
raw | patch | inline | side by side (parent: 60f1c4f)
| author | Koen Kooi <koen@dominion.thruhere.net> | |
| Sun, 2 Jan 2011 15:50:43 +0000 (16:50 +0100) | ||
| committer | Koen Kooi <koen@dominion.thruhere.net> | |
| Mon, 3 Jan 2011 08:01:08 +0000 (09:01 +0100) |
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
12 files changed:
diff --git a/conf/machine/omap3evm.conf b/conf/machine/omap3evm.conf
--- /dev/null
@@ -0,0 +1,52 @@
+#@TYPE: Machine
+#@NAME: OMAP3 EVM
+#@DESCRIPTION: Machine configuration for the TI OMAP3 EVM
+TARGET_ARCH = "arm"
+
+PREFERRED_PROVIDER_virtual/xserver = "xserver-xorg"
+XSERVER = "xserver-xorg \
+ xf86-input-evdev \
+ xf86-input-mouse \
+ xf86-input-tslib \
+ xf86-video-omapfb \
+ xf86-input-keyboard"
+
+GUI_MACHINE_CLASS = "smallscreen"
+
+require conf/machine/include/omap3.inc
+
+# Ship all kernel modules
+
+IMAGE_FSTYPES ?= "jffs2 tar.bz2"
+EXTRA_IMAGECMD_jffs2 = "-lnp -e 0x20000 -s 2048"
+
+SERIAL_CONSOLE = "115200 ttyS0"
+USE_VT = "0"
+
+PREFERRED_PROVIDER_virtual/kernel = "linux-omap-psp"
+
+PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
+
+UBOOT_ARCH = "arm"
+UBOOT_MACHINE = "omap3_evm_config"
+XLOAD_MACHINE = "omap3evm_config"
+
+MACHINE_FEATURES = "kernel26 apm usbgadget usbhost vfat ext2 screen touchscreen"
+
+# NOTE: there are NAND and OneNAND versions of this board...
+
+# do ubiattach /dev/ubi_ctrl -m 4
+# From dmesg:
+# UBI: smallest flash I/O unit: 2048
+# UBI: logical eraseblock size: 129024 bytes
+# from ubiattach stdout:
+# UBI device number 0, total 1996 LEBs
+MKUBIFS_ARGS = "-m 2048 -e 129024 -c 1996"
+
+# do ubiattach /dev/ubi_ctrl -m 4
+# from dmesg:
+# UBI: smallest flash I/O unit: 2048
+# UBI: physical eraseblock size: 131072 bytes (128 KiB)
+# UBI: sub-page size: 512
+UBINIZE_ARGS = "-m 2048 -p 128KiB -s 512"
+
diff --git a/recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch b/recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch
--- /dev/null
@@ -0,0 +1,30 @@
+From 6b23ecf49d1c2ee5227ff57101919af46ecd7396 Mon Sep 17 00:00:00 2001
+From: Roger Monk <r-monk@ti.com>
+Date: Fri, 9 Jul 2010 08:37:04 +0100
+Subject: [PATCH] omap3evm: Change default 'console' serial port from ttyS2 to ttyS0
+
+ * Update default kernel console env variable ($(console))
+ to use ttyS0 (instead of ttyS2) to match the serial port
+ used by x-loader and u-boot
+
+Signed-off-by: Roger Monk <r-monk@ti.com>
+---
+ include/configs/omap3_evm.h | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
+index 73a5c98..d01d733 100644
+--- a/include/configs/omap3_evm.h
++++ b/include/configs/omap3_evm.h
+@@ -203,7 +203,7 @@
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+- "console=ttyS2,115200n8\0" \
++ "console=ttyS0,115200n8\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+--
+1.6.0.4
+
index 37508630bc982e7972e856663ad8df8ea37b800d..3aa69b77f4692fb56bf49823484225ccbab21930 100644 (file)
FILESPATHPKG =. "u-boot-git:"
FILESPATHPKG =. "u-boot-git:"
-SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git \
+SRC_URI_beagleboard = "git://www.denx.de/git/u-boot.git;protocol=git \
file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch \
file://0002-OMAP3-add-board-revision-detection-for-Overo.patch \
file://0003-OMAP3-update-Beagle-revision-detection-to-recognize-.patch \
file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch \
file://0002-OMAP3-add-board-revision-detection-for-Overo.patch \
file://0003-OMAP3-update-Beagle-revision-detection-to-recognize-.patch \
file://0044-Beagleboard-Adjust-boot.patch \
file://0045-BeagleBoard-Enable-pullups-on-i2c2.patch \
file://0046-BeagleBoard-Add-camera-to-default-bootargs.patch \
file://0044-Beagleboard-Adjust-boot.patch \
file://0045-BeagleBoard-Enable-pullups-on-i2c2.patch \
file://0046-BeagleBoard-Add-camera-to-default-bootargs.patch \
- file://0001-BeagleBoard-move-ramdisk-parameters.patch \
+ file://0001-BeagleBoard-move-ramdisk-parameters.patch \
file://fw_env.config \
"
file://fw_env.config \
"
-SRCREV = "ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55"
-PV = "2010.03+${PR}+gitr${SRCREV}"
+SRCREV_beagleboard = "ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55"
+PV_beagleboard = "2010.03+${PR}+gitr${SRCREV}"
+
+# ~ TI PSP v2009.11_OMAPPSP_03.00.01.06 (+ couple of commits)
+SRC_URI_omap3evm = "git://arago-project.org/git/projects/u-boot-omap3.git;protocol=git \
+ file://0001-omap3evm-Change-default-console-serial-port-from.patch \
+"
+SRCREV_omap3evm = "c0a8fb217fdca7888d89f9a3dee74a4cec865620"
+PV_omap3evm = "2009.11+${PR}+gitr${SRCREV}"
S = "${WORKDIR}/git"
S = "${WORKDIR}/git"
diff --git a/recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch b/recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce Mon Sep 17 00:00:00 2001
-From: Laine Walker-Avina <lwalkera@ieee.org>
-Date: Tue, 13 Apr 2010 13:27:31 -0700
-Subject: [PATCH] FAT: Find the start of the first partition in a non-hardcoded way
-
----
- fs/fat/fat.c | 12 +++++-------
- 1 files changed, 5 insertions(+), 7 deletions(-)
-
-diff --git a/fs/fat/fat.c b/fs/fat/fat.c
-index eb754c0..c6bdb13 100644
---- a/fs/fat/fat.c
-+++ b/fs/fat/fat.c
-@@ -145,13 +145,11 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
- return -1;
- }
- #else
-- /* FIXME we need to determine the start block of the
-- * partition where the DOS FS resides. This can be done
-- * by using the get_partition_info routine. For this
-- * purpose the libpart must be included.
-- */
-- part_offset=63;
-- //part_offset=0;
-+ part_offset = buffer[DOS_PART_TBL_OFFSET+8] |
-+ buffer[DOS_PART_TBL_OFFSET+9] <<8 |
-+ buffer[DOS_PART_TBL_OFFSET+10]<<16 |
-+ buffer[DOS_PART_TBL_OFFSET+11]<<24;
-+
- cur_part = 1;
- #endif
- }
---
-1.6.1
-
diff --git a/recipes-bsp/x-load/x-load-git/name.patch b/recipes-bsp/x-load/x-load-git/name.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- git/Makefile-orig 2010-03-08 06:56:36.000000000 -0800
-+++ git/Makefile 2010-03-08 06:56:52.000000000 -0800
-@@ -153,8 +153,8 @@ omap3evm_config : unconfig
- overo_config : unconfig
- @./mkconfig $(@:_config=) arm omap3 overo
-
--omap3530beagle_config : unconfig
-- @./mkconfig $(@:_config=) arm omap3 omap3530beagle
-+beagleboard_config : unconfig
-+ @./mkconfig omap3530beagle arm omap3 omap3530beagle
-
- #########################################################################
-
diff --git a/recipes-bsp/x-load/x-load-git/xm-mem.patch b/recipes-bsp/x-load/x-load-git/xm-mem.patch
+++ /dev/null
@@ -1,237 +0,0 @@
-From a25b926ff963a1866e26b11a4dac742564618375 Mon Sep 17 00:00:00 2001
-From: Steve Kipisz <s-kipisz2@ti.com>
-Date: Thu, 8 Jul 2010 10:30:58 -0500
-Subject: [PATCH] Support Micron or Numonyx memory
-
-* Updated Numonyx memory size.
----
- board/omap3530beagle/omap3530beagle.c | 56 +++++++++++++++++++++++++++-----
- drivers/k9f1g08r0a.c | 43 +++++++++++++++++++------
- include/asm/arch-omap3/mem.h | 43 ++++++++++++++++++++++++-
- 3 files changed, 121 insertions(+), 21 deletions(-)
-
-diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
-index eb8008e..1b3d8c7 100644
---- a/board/omap3530beagle/omap3530beagle.c
-+++ b/board/omap3530beagle/omap3530beagle.c
-@@ -265,6 +265,32 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
- }
-
- #ifdef CFG_3430SDRAM_DDR
-+
-+#define MICRON_DDR 0
-+#define NUMONYX_MCP 1
-+int identify_xm_ddr()
-+{
-+ int mfr, id;
-+
-+ __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
-+ __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
-+ __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
-+ __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
-+ __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
-+ __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-+
-+ /* Enable the GPMC Mapping */
-+ __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
-+ ((NAND_BASE_ADR>>24) & 0x3F) |
-+ (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
-+ delay(2000);
-+
-+ nand_readid(&mfr, &id);
-+ if (mfr == 0)
-+ return MICRON_DDR;
-+ if ((mfr == 0x20) && (id == 0xba))
-+ return NUMONYX_MCP;
-+}
- /*********************************************************************
- * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
- *********************************************************************/
-@@ -279,15 +305,27 @@ void config_3430sdram_ddr(void)
- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
- if (beagle_revision() == REVISION_XM) {
-- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
-- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_0);
-- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_1);
-- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
-- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
-- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
-- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
-- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
-- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
-+ if (identify_xm_ddr() == MICRON_DDR) {
-+ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
-+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
-+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
-+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
-+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
-+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
-+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
-+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
-+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
-+ } else {
-+ __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
-+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
-+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
-+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
-+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
-+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
-+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
-+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
-+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
-+ }
- } else {
- __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
-diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
-index 8968a1b..d2da804 100644
---- a/drivers/k9f1g08r0a.c
-+++ b/drivers/k9f1g08r0a.c
-@@ -154,6 +154,29 @@ static int NanD_Address(unsigned int numbytes, unsigned long ofs)
- return 0;
- }
-
-+int nand_readid(int *mfr, int *id)
-+{
-+ NAND_ENABLE_CE();
-+
-+ if (NanD_Command(NAND_CMD_RESET)) {
-+ NAND_DISABLE_CE();
-+ return 1;
-+ }
-+
-+ if (NanD_Command(NAND_CMD_READID)) {
-+ NAND_DISABLE_CE();
-+ return 1;
-+ }
-+
-+ NanD_Address(ADDR_COLUMN, 0);
-+
-+ *mfr = READ_NAND(NAND_ADDR);
-+ *id = READ_NAND(NAND_ADDR);
-+
-+ NAND_DISABLE_CE();
-+ return 0;
-+}
-+
- /* read chip mfr and id
- * return 0 if they match board config
- * return 1 if not
-@@ -162,23 +185,23 @@ int nand_chip()
- {
- int mfr, id;
-
-- NAND_ENABLE_CE();
-+ NAND_ENABLE_CE();
-
-- if (NanD_Command(NAND_CMD_RESET)) {
-- printf("Err: RESET\n");
-- NAND_DISABLE_CE();
-+ if (NanD_Command(NAND_CMD_RESET)) {
-+ printf("Err: RESET\n");
-+ NAND_DISABLE_CE();
- return 1;
- }
-
-- if (NanD_Command(NAND_CMD_READID)) {
-- printf("Err: READID\n");
-- NAND_DISABLE_CE();
-+ if (NanD_Command(NAND_CMD_READID)) {
-+ printf("Err: READID\n");
-+ NAND_DISABLE_CE();
- return 1;
-- }
-+ }
-
-- NanD_Address(ADDR_COLUMN, 0);
-+ NanD_Address(ADDR_COLUMN, 0);
-
-- mfr = READ_NAND(NAND_ADDR);
-+ mfr = READ_NAND(NAND_ADDR);
- id = READ_NAND(NAND_ADDR);
-
- NAND_DISABLE_CE();
-diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
-index cba4c6f..63cdba1 100644
---- a/include/asm/arch-omap3/mem.h
-+++ b/include/asm/arch-omap3/mem.h
-@@ -46,6 +46,7 @@ typedef enum {
- #define MMC_NAND 4
- #define MMC_ONENAND 5
- #define GPMC_NONE 6
-+#define GPMC_ONENAND_TRY 7
-
- #endif
-
-@@ -71,7 +72,8 @@ typedef enum {
- #define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */
- #else
- #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL)
--#define SDP_SDRC_MDCFG_0_DDR_XM (0x03588019|B_ALL)
-+#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
-+#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL)
- #endif
-
- #define SDP_SDRC_MR_0_DDR 0x00000032
-@@ -252,12 +254,47 @@ typedef enum {
- (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
-
- #define MICRON_TWTR_200 2
--#define MICRON_TCKE_200 1
-+#define MICRON_TCKE_200 4
- #define MICRON_TXP_200 2
- #define MICRON_XSR_200 23
- #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
- (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
-
-+/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
-+ * ACTIMA
-+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
-+ * TDPL (Twr) = 15/6 = 2.5 -> 3
-+ * TRRD = 12/6 = 2
-+ * TRCD = 22.5/6 = 3.75 -> 4
-+ * TRP = 18/6 = 3
-+ * TRAS = 42/6 = 7
-+ * TRC = 60/6 = 10
-+ * TRFC = 140/6 = 23.3 -> 24
-+ * ACTIMB
-+ * TWTR = 2
-+ * TCKE = 2
-+ * TXSR = 200/6 = 33.3 -> 34
-+ * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿?
-+ */
-+#define NUMONYX_TDAL_165 6
-+#define NUMONYX_TDPL_165 3
-+#define NUMONYX_TRRD_165 2
-+#define NUMONYX_TRCD_165 4
-+#define NUMONYX_TRP_165 3
-+#define NUMONYX_TRAS_165 7
-+#define NUMONYX_TRC_165 10
-+#define NUMONYX_TRFC_165 24
-+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
-+ | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
-+ (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
-+
-+#define NUMONYX_TWTR_165 2
-+#define NUMONYX_TCKE_165 2
-+#define NUMONYX_TXP_165 3
-+#define NUMONYX_XSR_165 34
-+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
-+ (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
-+
- /* New and compatability speed defines */
- #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
- # define L3_100MHZ /* Use with <= 100MHz SDRAM */
-@@ -276,6 +313,8 @@ typedef enum {
- #elif defined(L3_165MHZ)
- # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165
- # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165
-+# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165
-+# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165
- #endif
-
-
---
-1.6.1
-
diff --git a/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch b/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch
--- /dev/null
@@ -0,0 +1,265 @@
+From 94fee465a6d63b6f0551037fe14cec4410bb9af2 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Tue, 21 Dec 2010 11:55:01 -0200
+Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks
+
+X-loader untill now, was enabling all clks at bootup
+to help all modules to be functional at the kernel, even
+with drivers which do not handle clks well.
+Now that we are moving towards all drivers being adapted
+to request/release clks as expected, most of this code is
+useless and hence removed.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c | 225 ++++++++++++++++++++++---------------------
+ 1 files changed, 117 insertions(+), 108 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 792e5d6..149fc85 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -552,71 +552,73 @@ static void enable_all_clocks(void)
+ {
+ volatile int regvalue = 0;
+
+- /* Enable Ducati clocks */
+- sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
+- sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
+-
+- wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
+-
+- /* Enable ivahd and sl2 clocks */
+- sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
+- sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
+- sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
+-
+- wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
+-
+- /* wait for ivahd to become accessible */
+- //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
+- /* wait for sl2 to become accessible */
+- //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
+-
+- /* Enable Tesla clocks */
+- sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
+- sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
+-
+- wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
+-
+- /* wait for tesla to become accessible */
+- //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
+-
+- /* TODO: Some hack needed by MM: Clean this */
+- #if 0 /* Doesn't work on some Zebu */
+- *(volatile int*)0x4a306910 = 0x00000003;
+- *(volatile int*)0x550809a0 = 0x00000001;
+- *(volatile int*)0x55080a20 = 0x00000007;
+- #endif
+-
+- /* ABE clocks */
+- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
+- sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
+- sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
+- /* Disable sleep transitions */
+- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
++ if (omap_revision() == OMAP4430_ES1_0) {
++ /* Enable Ducati clocks */
++ sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
++ sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
++
++ wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
++
++ /* Enable ivahd and sl2 clocks */
++ sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
++ sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
++ sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
++
++ wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
++
++ /* wait for ivahd to become accessible */
++ //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
++ /* wait for sl2 to become accessible */
++ //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
++
++ /* Enable Tesla clocks */
++ sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
++ sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
++
++ wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
++
++ /* wait for tesla to become accessible */
++ //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
++
++ /* TODO: Some hack needed by MM: Clean this */
++ #if 0 /* Doesn't work on some Zebu */
++ *(volatile int*)0x4a306910 = 0x00000003;
++ *(volatile int*)0x550809a0 = 0x00000001;
++ *(volatile int*)0x55080a20 = 0x00000007;
++ #endif
++
++ /* ABE clocks */
++ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
++ sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
++ sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
++ /* Disable sleep transitions */
++ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
++ }
+
+ /* L4PER clocks */
+ sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
+@@ -723,50 +725,57 @@ static void enable_all_clocks(void)
+ sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
+
+- /* Enable Camera clocks */
+- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
+- sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
+- sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
+- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
+-
+- /* Enable DSS clocks */
+- /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
+- *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
+- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
+- sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
+- sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
+- /* Check for DSS Clocks */
+- while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
+- /* Set HW_AUTO transition mode */
+- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
+-
+- /* Enable SGX clocks */
+- sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
+- sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
+- /* Check for SGX FCLK and ICLK */
+- while ( (*(volatile int*)0x4A009200) != 0x302 );
+- //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
+- /* Enable hsi/unipro/usb clocks */
+- sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
+- sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
+- sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
+- sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
+- sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
+- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
+- sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
+- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
+- /* enable the 32K, 48M optional clocks and enable the module */
++ if (omap_revision() == OMAP4430_ES1_0) {
++ /* Enable Camera clocks */
++ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
++ sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
++ sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
++ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
++
++ /* Enable DSS clocks */
++ /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
++ *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
++ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
++ sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
++ sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
++ /* Check for DSS Clocks */
++ while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
++ /* Set HW_AUTO transition mode */
++ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
++
++ /* Enable SGX clocks */
++ sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
++ sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
++ /* Check for SGX FCLK and ICLK */
++ while ( (*(volatile int*)0x4A009200) != 0x302 );
++ //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
++ /* Enable hsi/unipro/usb clocks */
++ sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
++ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
++ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
++ /* enable the 32K, 48M optional clocks and enable the module */
++ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
++ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
++ }
++
++ /* Enable clocks for USB fast boot to work */
+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
+- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
++ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
++
+ return;
+ }
+
+--
+1.6.6.1
+
diff --git a/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch b/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch
--- /dev/null
@@ -0,0 +1,32 @@
+From fff093ab92c5dadd646130c38097dc167d2d0e1e Mon Sep 17 00:00:00 2001
+From: Rajeev Kulkarni <rajeevk@ti.com>
+Date: Tue, 26 Oct 2010 07:34:43 -0500
+Subject: [PATCH 2/5] OMAP4: Select DPLL PER Clock as source for SGX FCLK
+
+The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER
+is set 1536 Mhz, There is no need to change dividers, just
+parent clock need to change. And DPLL PER is set at 1536.
+
+Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 149fc85..0961f51 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -772,6 +772,9 @@ static void enable_all_clocks(void)
+ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
+ }
+
++ /* Select DPLL PER CLOCK as source for SGX FCLK */
++ sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
++
+ /* Enable clocks for USB fast boot to work */
+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
+--
+1.6.6.1
+
diff --git a/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch b/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch
--- /dev/null
@@ -0,0 +1,33 @@
+From daaaf036f3336e01a83a13dd93b8030b00a0af50 Mon Sep 17 00:00:00 2001
+From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+Date: Tue, 21 Dec 2010 12:03:50 -0200
+Subject: [PATCH 3/5] MUX: Configure SYS_NIRQ2 pin in safe mode
+
+SYS_NIRQ2 pin if not in safe mode, with audio driver
+enabled gates CORE RET. Hence configured in safe mode.
+Audio driver is expected to re-init the pin in the
+kernel.
+
+Patch from sdp, by Rajendra Nayak <rnayak@ti.com>
+
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/omap4430panda.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
+index 5695733..814b2cb 100644
+--- a/board/omap4430panda/omap4430panda.c
++++ b/board/omap4430panda/omap4430panda.c
+@@ -910,7 +910,7 @@ int dram_init(void)
+ MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
+ MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
+ MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
+- MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
++ MV(CP(SYS_NIRQ2) , (M7_SAFE)) /* sys_nirq2 */ \
+ MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
+ MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
+ MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
+--
+1.6.6.1
+
diff --git a/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch b/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch
--- /dev/null
@@ -0,0 +1,34 @@
+From 4af562525c7779cd41ae9a68d56771407df558d7 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Mon, 4 Oct 2010 18:49:18 +0530
+Subject: [PATCH 4/5] OMAP4: clocks: Disable slimbus and pad_clks
+
+The slimbus and pad_clks if left enabled in x-loader
+would gate abe power domain from transitioning to RET.
+
+These should be enabled by the audio driver (if present)
+in the kernel.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c | 3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 0961f51..c591a9f 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -333,9 +333,6 @@ static void configure_abe_dpll(u32 clk_index)
+ /* Select sys_clk as ref clk for ABE dpll */
+ sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
+
+- /* Enable slimbus and pad clocks */
+- sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
+-
+ /* Unlock the ABE dpll */
+ sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
+--
+1.6.6.1
+
diff --git a/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch b/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch
--- /dev/null
@@ -0,0 +1,49 @@
+From ce1ae065d5eb875990f55ede0405e061e4d4b8d3 Mon Sep 17 00:00:00 2001
+From: Sebastien Jan <s-jan@ti.com>
+Date: Wed, 22 Dec 2010 13:53:18 +0100
+Subject: [PATCH 5/5] omap4: Make 1GHz as default MPU clock
+
+Signed-off-by: Aneesh V <aneesh@ti.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Sebastien Jan <s-jan@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ Makefile | 8 ++++++++
+ include/configs/omap4430panda.h | 1 -
+ 2 files changed, 8 insertions(+), 1 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index d134fdc..1c4fdd5 100644
+--- a/Makefile
++++ b/Makefile
+@@ -170,6 +170,14 @@ omap3530beagle_config : unconfig
+ #########################################################################
+ omap4430panda_config : unconfig
+ @./mkconfig $(@:_config=) arm omap4 omap4430panda
++ @[ -n "$(findstring _MPU_600MHz,$@)" ] || \
++ { echo "#define CONFIG_MPU_1000 1" >> $(obj)include/config.h; \
++ echo "MPU at 1GHz revision.."; \
++ }
++ @[ -z "$(findstring _MPU_600MHz,$@)" ] || \
++ { echo "#define CONFIG_MPU_600 1" >> $(obj)include/config.h; \
++ echo "MPU at 600MHz revision.."; \
++ }
+
+ #########################################################################
+
+diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h
+index 74e2f42..eae02ef 100644
+--- a/include/configs/omap4430panda.h
++++ b/include/configs/omap4430panda.h
+@@ -44,7 +44,6 @@
+ * On Phoenix board vlotage needs to be bumped up
+ * before scaling the MPU up
+ */
+-#define CONFIG_MPU_600 1
+ #define CORE_190MHZ 1
+ /* Enable the below macro if MMC boot support is required */
+ #define CONFIG_MMC 1
+--
+1.6.6.1
+
index f45bac95161413a5be63f726e0ba30b402b09eb1..ddb20907ec49a61572d28ca3ad2eefa88f858598 100644 (file)
require x-load.inc
require x-load.inc
-DEFAULT_PREFERENCE_omap3-pandora = "-1"
-
-FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/x-load-git"
-
-SRCREV_pn-${PN} = "1c9276af4d6a5b7014a7630a1abeddf3b3177563"
+#FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}"
PV = "1.44+${PR}+gitr${SRCREV}"
PV = "1.44+${PR}+gitr${SRCREV}"
-PR ="r16"
+PR ="r17"
PE = "1"
PE = "1"
-SRC_URI = "git://gitorious.org/x-load-omap3/mainline.git;branch=master;protocol=git"
+SRCREV_pn-${PN} = "6f3a26101303051e0f91b6213735b68ce804e94e"
+SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \
+ file://0001-OMAP4-clocks-Enable-only-required-clks.patch \
+ file://0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch \
+ file://0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch \
+ file://0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch \
+ file://0005-omap4-Make-1GHz-as-default-MPU-clock.patch \
+ "
-SRC_URI_append_beagleboard = " \
- file://name.patch \
- file://bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch \
- file://xm-mem.patch \
- "
S = "${WORKDIR}/git"
S = "${WORKDIR}/git"
+XLOAD_MACHINE_beagleboard = "omap3530beagle_config"
+
PACKAGE_ARCH = "${MACHINE_ARCH}"
PACKAGE_ARCH = "${MACHINE_ARCH}"