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raw | patch | inline | side by side (parent: 6587ff8)
raw | patch | inline | side by side (parent: 6587ff8)
author | Koen Kooi <koen@dominion.thruhere.net> | |
Thu, 21 Jul 2011 12:52:50 +0000 (14:52 +0200) | ||
committer | Koen Kooi <koen@dominion.thruhere.net> | |
Thu, 21 Jul 2011 12:52:50 +0000 (14:52 +0200) |
* Bump SRCREV to latest 3.0rc from Linux
* Merge in pm-voltdm patches
* Merge in ABB support
* Merge in expansion-board support (unfished)
* Add hack for switch to GPTIMER1
* Set default cpufreq governor to performance
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
* Merge in pm-voltdm patches
* Merge in ABB support
* Merge in expansion-board support (unfished)
* Add hack for switch to GPTIMER1
* Set default cpufreq governor to performance
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
185 files changed:
diff --git a/recipes-kernel/linux/linux-3.0/beagle/0001-OMAP3-beagle-add-support-for-beagleboard-xM-revision.patch b/recipes-kernel/linux/linux-3.0/beagle/0001-OMAP3-beagle-add-support-for-beagleboard-xM-revision.patch
index 9f9b43edcd2bf6d572581816311f0335e51dec40..ff914dc85da95b53ca26c8940194bfd5a71acb96 100644 (file)
-From 033514238d4b2b59b1507f39372dbabe7365c102 Mon Sep 17 00:00:00 2001
+From fa563f291feaed45803ae17db71514928a17a6a6 Mon Sep 17 00:00:00 2001
From: Fernandes, Joel A <joelagnel@ti.com>
Date: Tue, 7 Jun 2011 15:54:45 -0500
-Subject: [PATCH] OMAP3: beagle: add support for beagleboard xM revision C
+Subject: [PATCH 1/3] OMAP3: beagle: add support for beagleboard xM revision C
OMAP3: beagle: add support for beagleboard xM revision C
1 files changed, 51 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 7f21d24..4b113b2 100644
+index 34f8411..32f5f89 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -61,7 +61,8 @@
+@@ -60,7 +60,8 @@
* AXBX = GPIO173, GPIO172, GPIO171: 1 1 1
* C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0
* C4 = GPIO173, GPIO172, GPIO171: 1 0 1
*/
enum {
OMAP3BEAGLE_BOARD_UNKN = 0,
-@@ -69,14 +70,26 @@ enum {
+@@ -68,14 +69,26 @@ enum {
OMAP3BEAGLE_BOARD_C1_3,
OMAP3BEAGLE_BOARD_C4,
OMAP3BEAGLE_BOARD_XM,
static struct gpio omap3_beagle_rev_gpios[] __initdata = {
{ 171, GPIOF_IN, "rev_id_0" },
-@@ -111,18 +124,32 @@ static void __init omap3_beagle_init_rev(void)
+@@ -110,18 +123,32 @@ static void __init omap3_beagle_init_rev(void)
case 7:
printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
break;
default:
printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
-@@ -234,7 +261,7 @@ static struct omap2_hsmmc_info mmc[] = {
+@@ -225,7 +252,7 @@ static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
},
{} /* Terminator */
};
-@@ -252,17 +279,11 @@ static struct gpio_led gpio_leds[];
+@@ -243,17 +270,11 @@ static struct gpio_led gpio_leds[];
static int beagle_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
-@@ -276,9 +297,8 @@ static int beagle_twl_gpio_setup(struct device *dev,
+@@ -263,9 +284,8 @@ static int beagle_twl_gpio_setup(struct device *dev,
* high / others active low)
* DVI reset GPIO is different between beagle revisions
*/
/*
* gpio + 1 on Xm controls the TFP410's enable line (active low)
* gpio + 2 control varies depending on the board rev as below:
-@@ -296,8 +316,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
+@@ -283,8 +303,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
pr_err("%s: unable to configure DVI_LDO_EN\n",
__func__);
} else {
/*
* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
-@@ -305,8 +323,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
+@@ -292,8 +310,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
pr_err("%s: unable to configure EHCI_nOC\n", __func__);
}
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-@@ -458,7 +478,8 @@ static struct platform_device leds_gpio = {
+@@ -404,7 +424,8 @@ static struct platform_device leds_gpio = {
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_EXTRA,
.desc = "user",
.wakeup = 1,
},
-@@ -525,8 +546,8 @@ static void __init beagle_opp_init(void)
+@@ -468,8 +489,8 @@ static void __init beagle_opp_init(void)
return;
}
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
struct device *dev;
-@@ -566,6 +587,9 @@ static void __init omap3_beagle_init(void)
+@@ -509,6 +530,9 @@ static void __init omap3_beagle_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_init_rev();
omap3_beagle_i2c_init();
diff --git a/recipes-kernel/linux/linux-3.0/beagle/0002-UNFINISHED-OMAP3-beagle-add-support-for-expansionboa.patch b/recipes-kernel/linux/linux-3.0/beagle/0002-UNFINISHED-OMAP3-beagle-add-support-for-expansionboa.patch
--- /dev/null
@@ -0,0 +1,313 @@
+From 04557e8b744e8e6f8ab8b7c4fc715cecd585f2ab Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Thu, 21 Jul 2011 14:29:42 +0200
+Subject: [PATCH 2/3] UNFINISHED: OMAP3: beagle: add support for expansionboards
+
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c | 246 +++++++++++++++++++++++++++++++
+ 1 files changed, 246 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 32f5f89..e542df0 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -21,6 +21,7 @@
+ #include <linux/io.h>
+ #include <linux/leds.h>
+ #include <linux/gpio.h>
++#include <linux/irq.h>
+ #include <linux/input.h>
+ #include <linux/gpio_keys.h>
+ #include <linux/opp.h>
+@@ -156,6 +157,167 @@ static void __init omap3_beagle_init_rev(void)
+ }
+ }
+
++char expansionboard_name[16];
++
++#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++#include <linux/regulator/fixed.h>
++#include <linux/wl12xx.h>
++
++#define OMAP_BEAGLE_WLAN_EN_GPIO (139)
++#define OMAP_BEAGLE_BT_EN_GPIO (138)
++#define OMAP_BEAGLE_WLAN_IRQ_GPIO (137)
++#define OMAP_BEAGLE_FM_EN_BT_WU (136)
++
++struct wl12xx_platform_data omap_beagle_wlan_data __initdata = {
++ .irq = OMAP_GPIO_IRQ(OMAP_BEAGLE_WLAN_IRQ_GPIO),
++ .board_ref_clock = 2, /* 38.4 MHz */
++};
++
++static int gpios[] = {OMAP_BEAGLE_BT_EN_GPIO, OMAP_BEAGLE_FM_EN_BT_WU, -1};
++static struct platform_device wl12xx_device = {
++ .name = "kim",
++ .id = -1,
++ .dev.platform_data = &gpios,
++};
++
++static struct omap2_hsmmc_info mmcbbt[] = {
++ {
++ .mmc = 1,
++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
++ .gpio_wp = 29,
++ },
++ {
++ .name = "wl1271",
++ .mmc = 2,
++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
++ .gpio_wp = -EINVAL,
++ .gpio_cd = -EINVAL,
++ .ocr_mask = MMC_VDD_165_195,
++ .nonremovable = true,
++ },
++ {} /* Terminator */
++ };
++
++static struct regulator_consumer_supply beagle_vmmc2_supply =
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++
++static struct regulator_init_data beagle_vmmc2 = {
++ .constraints = {
++ .min_uV = 1850000,
++ .max_uV = 1850000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &beagle_vmmc2_supply,
++};
++
++static struct fixed_voltage_config beagle_vwlan = {
++ .supply_name = "vwl1271",
++ .microvolts = 1800000, /* 1.8V */
++ .gpio = OMAP_BEAGLE_WLAN_EN_GPIO,
++ .startup_delay = 70000, /* 70ms */
++ .enable_high = 1,
++ .enabled_at_boot = 0,
++ .init_data = &beagle_vmmc2,
++};
++
++static struct platform_device omap_vwlan_device = {
++ .name = "reg-fixed-voltage",
++ .id = 1,
++ .dev = {
++ .platform_data = &beagle_vwlan,
++ },
++};
++#endif
++
++#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
++
++#include <plat/mcspi.h>
++#include <linux/spi/spi.h>
++
++#define OMAP3BEAGLE_GPIO_ENC28J60_IRQ 157
++
++static struct omap2_mcspi_device_config enc28j60_spi_chip_info = {
++ .turbo_mode = 0,
++ .single_channel = 1, /* 0: slave, 1: master */
++};
++
++static struct spi_board_info omap3beagle_zippy_spi_board_info[] __initdata = {
++ {
++ .modalias = "enc28j60",
++ .bus_num = 4,
++ .chip_select = 0,
++ .max_speed_hz = 20000000,
++ .controller_data = &enc28j60_spi_chip_info,
++ },
++};
++
++static void __init omap3beagle_enc28j60_init(void)
++{
++ if ((gpio_request(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, "ENC28J60_IRQ") == 0) &&
++ (gpio_direction_input(OMAP3BEAGLE_GPIO_ENC28J60_IRQ) == 0)) {
++ gpio_export(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, 0);
++ omap3beagle_zippy_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_ENC28J60_IRQ);
++ irq_set_irq_type(omap3beagle_zippy_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING);
++ } else {
++ printk(KERN_ERR "could not obtain gpio for ENC28J60_IRQ\n");
++ return;
++ }
++
++ spi_register_board_info(omap3beagle_zippy_spi_board_info,
++ ARRAY_SIZE(omap3beagle_zippy_spi_board_info));
++}
++
++#else
++static inline void __init omap3beagle_enc28j60_init(void) { return; }
++#endif
++
++#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
++
++#include <plat/mcspi.h>
++#include <linux/spi/spi.h>
++
++#define OMAP3BEAGLE_GPIO_KS8851_IRQ 157
++
++static struct omap2_mcspi_device_config ks8851_spi_chip_info = {
++ .turbo_mode = 0,
++ .single_channel = 1, /* 0: slave, 1: master */
++};
++
++static struct spi_board_info omap3beagle_zippy2_spi_board_info[] __initdata = {
++ {
++ .modalias = "ks8851",
++ .bus_num = 4,
++ .chip_select = 0,
++ .max_speed_hz = 36000000,
++ .controller_data = &ks8851_spi_chip_info,
++ },
++};
++
++static void __init omap3beagle_ks8851_init(void)
++{
++ if ((gpio_request(OMAP3BEAGLE_GPIO_KS8851_IRQ, "KS8851_IRQ") == 0) &&
++ (gpio_direction_input(OMAP3BEAGLE_GPIO_KS8851_IRQ) == 0)) {
++ gpio_export(OMAP3BEAGLE_GPIO_KS8851_IRQ, 0);
++ omap3beagle_zippy2_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_KS8851_IRQ);
++ irq_set_irq_type(omap3beagle_zippy2_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING);
++ } else {
++ printk(KERN_ERR "could not obtain gpio for KS8851_IRQ\n");
++ return;
++ }
++
++ spi_register_board_info(omap3beagle_zippy2_spi_board_info,
++ ARRAY_SIZE(omap3beagle_zippy2_spi_board_info));
++}
++
++#else
++static inline void __init omap3beagle_ks8851_init(void) { return; }
++#endif
++
+ static struct mtd_partition omap3beagle_nand_partitions[] = {
+ /* All the partition sizes are listed in terms of NAND block size */
+ {
+@@ -254,6 +416,12 @@ static struct omap2_hsmmc_info mmc[] = {
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+ .gpio_wp = -EINVAL,
+ },
++ {
++ .mmc = 2,
++ .caps = MMC_CAP_4_BIT_DATA,
++ .transceiver = true,
++ .ocr_mask = 0x00100000, /* 3.3V */
++ },
+ {} /* Terminator */
+ };
+
+@@ -277,7 +445,15 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
+ /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+ mmc[0].gpio_cd = gpio + 0;
++#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++ if(!strcmp(expansionboard_name, "bbtoys-wifi")) {
++ omap2_hsmmc_init(mmcbbt);
++ } else {
++ omap2_hsmmc_init(mmc);
++ }
++#else
+ omap2_hsmmc_init(mmc);
++#endif
+
+ /*
+ * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
+@@ -479,6 +655,15 @@ static struct omap_board_mux board_mux[] __initdata = {
+ };
+ #endif
+
++static int __init expansionboard_setup(char *str)
++{
++ if (!str)
++ return -EINVAL;
++ strncpy(expansionboard_name, str, 16);
++ printk(KERN_INFO "Beagle expansionboard: %s\n", expansionboard_name);
++ return 0;
++}
++
+ static void __init beagle_opp_init(void)
+ {
+ int r = 0;
+@@ -542,6 +727,65 @@ static void __init omap3_beagle_init(void)
+ /* REVISIT leave DVI powered down until it's needed ... */
+ gpio_request_one(170, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
+
++ if(!strcmp(expansionboard_name, "zippy"))
++ {
++ printk(KERN_INFO "Beagle expansionboard: initializing enc28j60\n");
++ omap3beagle_enc28j60_init();
++ printk(KERN_INFO "Beagle expansionboard: assigning GPIO 141 and 162 to MMC1\n");
++ mmc[1].gpio_wp = 141;
++ mmc[1].gpio_cd = 162;
++ }
++
++ if(!strcmp(expansionboard_name, "zippy2"))
++ {
++ printk(KERN_INFO "Beagle expansionboard: initializing ks_8851\n");
++ omap3beagle_ks8851_init();
++ printk(KERN_INFO "Beagle expansionboard: assigning GPIO 141 and 162 to MMC1\n");
++ mmc[1].gpio_wp = 141;
++ mmc[1].gpio_cd = 162;
++ }
++
++ if(!strcmp(expansionboard_name, "trainer"))
++ {
++ printk(KERN_INFO "Beagle expansionboard: exporting GPIOs 130-141,162 to userspace\n");
++ gpio_request(130, "sysfs");
++ gpio_export(130, 1);
++ gpio_request(131, "sysfs");
++ gpio_export(131, 1);
++ gpio_request(132, "sysfs");
++ gpio_export(132, 1);
++ gpio_request(133, "sysfs");
++ gpio_export(133, 1);
++ gpio_request(134, "sysfs");
++ gpio_export(134, 1);
++ gpio_request(135, "sysfs");
++ gpio_export(135, 1);
++ gpio_request(136, "sysfs");
++ gpio_export(136, 1);
++ gpio_request(137, "sysfs");
++ gpio_export(137, 1);
++ gpio_request(138, "sysfs");
++ gpio_export(138, 1);
++ gpio_request(139, "sysfs");
++ gpio_export(139, 1);
++ gpio_request(140, "sysfs");
++ gpio_export(140, 1);
++ gpio_request(141, "sysfs");
++ gpio_export(141, 1);
++ gpio_request(162, "sysfs");
++ gpio_export(162, 1);
++ }
++
++ if(!strcmp(expansionboard_name, "bbtoys-wifi"))
++ {
++ if (wl12xx_set_platform_data(&omap_beagle_wlan_data))
++ pr_err("error setting wl12xx data\n");
++ printk(KERN_INFO "Beagle expansionboard: registering wl12xx bt platform device\n");
++ platform_device_register(&wl12xx_device);
++ printk(KERN_INFO "Beagle expansionboard: registering wl12xx wifi platform device\n");
++ platform_device_register(&omap_vwlan_device);
++ }
++
+ usb_musb_init(NULL);
+ usbhs_init(&usbhs_bdata);
+ omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
+@@ -558,6 +802,8 @@ static void __init omap3_beagle_init(void)
+ beagle_opp_init();
+ }
+
++early_param("buddy", expansionboard_setup);
++
+ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
+ .boot_params = 0x80000100,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/beagle/0003-HACK-OMAP3-beagle-switch-to-GPTIMER1.patch b/recipes-kernel/linux/linux-3.0/beagle/0003-HACK-OMAP3-beagle-switch-to-GPTIMER1.patch
--- /dev/null
@@ -0,0 +1,26 @@
+From dcdb487041d64eab8369b477311553f3c9fc9157 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Thu, 21 Jul 2011 12:59:20 +0200
+Subject: [PATCH 3/3] HACK: OMAP3: beagle: switch to GPTIMER1
+
+Breaks with B3 and older due to clock noise
+
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index e542df0..f4b01a9 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -812,5 +812,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ .init_early = omap3_beagle_init_early,
+ .init_irq = omap3_beagle_init_irq,
+ .init_machine = omap3_beagle_init,
+- .timer = &omap3_secure_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/beagleboard/defconfig b/recipes-kernel/linux/linux-3.0/beagleboard/defconfig
index 6f97d93b4c368b0f132c16a246990976a63823d0..1942725fb7e786cb9c2bd02cc39ad3e1cb51b74f 100644 (file)
CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
# CONFIG_ARCH_OMAP2 is not set
CONFIG_ARCH_OMAP3=y
-# CONFIG_ARCH_OMAP4 is not set
+CONFIG_ARCH_OMAP4=y
CONFIG_SOC_OMAP3430=y
# CONFIG_SOC_OMAPTI816X is not set
CONFIG_OMAP_PACKAGE_CBB=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_HOTPLUG is not set
diff --git a/recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch b/recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch
--- /dev/null
@@ -0,0 +1,93 @@
+From d6bdaaceafadfc31441e8dd14696da5ea683424b Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Wed, 29 Jun 2011 17:25:53 -0700
+Subject: [PATCH 1/8] OMAP3630: PRM: add ABB PRM register definitions
+
+OMAP3630 supports an Adaptive Body-Bias ldo as well as some MPU interrupts
+related to voltage control that are not present on OMAP34XX. This patch
+adds the offsets, register addresses, bitfield shifts and masks to support
+this feature.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/prm-regbits-34xx.h | 34 ++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 +++
+ 2 files changed, 38 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
+index 64c087a..0309ff6 100644
+--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
++++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
+@@ -216,6 +216,12 @@
+ /* PRM_SYSCONFIG specific bits */
+
+ /* PRM_IRQSTATUS_MPU specific bits */
++#define OMAP3630_VC_BYPASS_ACK_ST_SHIFT 28
++#define OMAP3630_VC_BYPASS_ACK_ST_MASK (1 << 28)
++#define OMAP3630_VC_VP1_ACK_ST_SHIFT 27
++#define OMAP3630_VC_VP1_ACK_ST_MASK (1 << 27)
++#define OMAP3630_ABB_LDO_TRANXDONE_ST_SHIFT 26
++#define OMAP3630_ABB_LDO_TRANXDONE_ST_MASK (1 << 26)
+ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
+ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
+ #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
+@@ -248,6 +254,12 @@
+ #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
+
+ /* PRM_IRQENABLE_MPU specific bits */
++#define OMAP3630_VC_BYPASS_ACK_EN_SHIFT 28
++#define OMAP3630_VC_BYPASS_ACK_EN_MASK (1 << 28)
++#define OMAP3630_VC_VP1_ACK_EN_SHIFT 27
++#define OMAP3630_VC_VP1_ACK_EN_MASK (1 << 27)
++#define OMAP3630_ABB_LDO_TRANXDONE_EN_SHIFT 26
++#define OMAP3630_ABB_LDO_TRANXDONE_EN_MASK (1 << 26)
+ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
+ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
+ #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
+@@ -587,6 +599,28 @@
+
+ /* PRM_VP2_STATUS specific bits */
+
++/* PRM_LDO_ABB_SETUP specific bits */
++#define OMAP3630_SR2_IN_TRANSITION_SHIFT 6
++#define OMAP3630_SR2_IN_TRANSITION_MASK (1 << 6)
++#define OMAP3630_SR2_STATUS_SHIFT 3
++#define OMAP3630_SR2_STATUS_MASK (3 << 3)
++#define OMAP3630_OPP_CHANGE_SHIFT 2
++#define OMAP3630_OPP_CHANGE_MASK (1 << 2)
++#define OMAP3630_OPP_SEL_SHIFT 0
++#define OMAP3630_OPP_SEL_MASK (3 << 0)
++
++/* PRM_LDO_ABB_CTRL specific bits */
++#define OMAP3630_SR2_WTCNT_VALUE_SHIFT 8
++#define OMAP3630_SR2_WTCNT_VALUE_MASK (0xff << 8)
++#define OMAP3630_SLEEP_RBB_SEL_SHIFT 3
++#define OMAP3630_SLEEP_RBB_SEL_MASK (1 << 3)
++#define OMAP3630_ACTIVE_FBB_SEL_SHIFT 2
++#define OMAP3630_ACTIVE_FBB_SEL_MASK (1 << 2)
++#define OMAP3630_ACTIVE_RBB_SEL_SHIFT 1
++#define OMAP3630_ACTIVE_RBB_SEL_MASK (1 << 1)
++#define OMAP3630_SR2EN_SHIFT 0
++#define OMAP3630_SR2EN_MASK (1 << 0)
++
+ /* RM_RSTST_NEON specific bits */
+
+ /* PM_WKDEP_NEON specific bits */
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index cef533d..408d1c7 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -167,6 +167,10 @@
+ #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+ #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
+ #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
++#define OMAP3_PRM_LDO_ABB_SETUP_OFFSET 0x00f0
++#define OMAP3630_PRM_LDO_ABB_SETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00f0)
++#define OMAP3_PRM_LDO_ABB_CTRL_OFFSET 0x00f4
++#define OMAP3630_PRM_LDO_ABB_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00f4)
+
+ #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+ #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0002-OMAP3-PM-VP-generalize-PRM-interrupt-helpers.patch b/recipes-kernel/linux/linux-3.0/bias/0002-OMAP3-PM-VP-generalize-PRM-interrupt-helpers.patch
--- /dev/null
@@ -0,0 +1,263 @@
+From 8e6411258660b08ee55b4148cca37f841d9c9568 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Wed, 29 Jun 2011 17:25:54 -0700
+Subject: [PATCH 2/8] OMAP3+: PM: VP: generalize PRM interrupt helpers
+
+We have multiple interrupt status hidden in the PRM interrupt status
+reg. Make this handling generic to allow us to pull out LDO status such
+as those for ABB from it using the same data structure and indexing. We
+hence rename accordingly.
+
+We also fix a trivial warning as the variable does not need exporting:
+arch/arm/mach-omap2/prm2xxx_3xxx.c:172:22: warning: symbol
+'omap3_prm_irqs' was not declared. Should it be static?
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/prm2xxx_3xxx.c | 22 +++++++++++-----------
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 7 +++++--
+ arch/arm/mach-omap2/prm44xx.c | 28 ++++++++++++++--------------
+ arch/arm/mach-omap2/prm44xx.h | 7 +++++--
+ arch/arm/mach-omap2/vp.h | 9 ---------
+ arch/arm/mach-omap2/vp3xxx_data.c | 4 ++--
+ arch/arm/mach-omap2/vp44xx_data.c | 6 +++---
+ 7 files changed, 40 insertions(+), 43 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+index 3b83763..8a20242 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+@@ -162,39 +162,39 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+ /* PRM VP */
+
+ /*
+- * struct omap3_vp - OMAP3 VP register access description.
++ * struct omap3_prm_irq - OMAP3 PRM IRQ register access description.
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+-struct omap3_vp {
++struct omap3_prm_irq {
+ u32 tranxdone_status;
+ };
+
+-struct omap3_vp omap3_vp[] = {
+- [OMAP3_VP_VDD_MPU_ID] = {
++static struct omap3_prm_irq omap3_prm_irqs[] = {
++ [OMAP3_PRM_IRQ_VDD_MPU_ID] = {
+ .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+ },
+- [OMAP3_VP_VDD_CORE_ID] = {
++ [OMAP3_PRM_IRQ_VDD_CORE_ID] = {
+ .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+ },
+ };
+
+ #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
+
+-u32 omap3_prm_vp_check_txdone(u8 vp_id)
++u32 omap3_prm_vp_check_txdone(u8 irq_id)
+ {
+- struct omap3_vp *vp = &omap3_vp[vp_id];
++ struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
+ u32 irqstatus;
+
+ irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+ OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+- return irqstatus & vp->tranxdone_status;
++ return irqstatus & irq->tranxdone_status;
+ }
+
+-void omap3_prm_vp_clear_txdone(u8 vp_id)
++void omap3_prm_vp_clear_txdone(u8 irq_id)
+ {
+- struct omap3_vp *vp = &omap3_vp[vp_id];
++ struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
+
+- omap2_prm_write_mod_reg(vp->tranxdone_status,
++ omap2_prm_write_mod_reg(irq->tranxdone_status,
+ OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ }
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index 408d1c7..d90b23f 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -307,9 +307,12 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+ extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+
++#define OMAP3_PRM_IRQ_VDD_MPU_ID 0
++#define OMAP3_PRM_IRQ_VDD_CORE_ID 1
+ /* OMAP3-specific VP functions */
+-u32 omap3_prm_vp_check_txdone(u8 vp_id);
+-void omap3_prm_vp_clear_txdone(u8 vp_id);
++u32 omap3_prm_vp_check_txdone(u8 irq_id);
++void omap3_prm_vp_clear_txdone(u8 irq_id);
++
+
+ /*
+ * OMAP3 access functions for voltage controller (VC) and
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index 495a31a..b77d331 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -57,49 +57,49 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+ /* PRM VP */
+
+ /*
+- * struct omap4_vp - OMAP4 VP register access description.
++ * struct omap4_prm_irq - OMAP4 VP register access description.
+ * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+-struct omap4_vp {
++struct omap4_prm_irq {
+ u32 irqstatus_mpu;
+ u32 tranxdone_status;
+ };
+
+-static struct omap4_vp omap4_vp[] = {
+- [OMAP4_VP_VDD_MPU_ID] = {
++static struct omap4_prm_irq omap4_prm_irqs[] = {
++ [OMAP4_PRM_IRQ_VDD_MPU_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+ .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+ },
+- [OMAP4_VP_VDD_IVA_ID] = {
++ [OMAP4_PRM_IRQ_VDD_IVA_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+ },
+- [OMAP4_VP_VDD_CORE_ID] = {
++ [OMAP4_PRM_IRQ_VDD_CORE_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+ },
+ };
+
+-u32 omap4_prm_vp_check_txdone(u8 vp_id)
++u32 omap4_prm_vp_check_txdone(u8 irq_id)
+ {
+- struct omap4_vp *vp = &omap4_vp[vp_id];
++ struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
+ u32 irqstatus;
+
+ irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_OCP_SOCKET_INST,
+- vp->irqstatus_mpu);
+- return irqstatus & vp->tranxdone_status;
++ irq->irqstatus_mpu);
++ return irqstatus & irq->tranxdone_status;
+ }
+
+-void omap4_prm_vp_clear_txdone(u8 vp_id)
++void omap4_prm_vp_clear_txdone(u8 irq_id)
+ {
+- struct omap4_vp *vp = &omap4_vp[vp_id];
++ struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
+
+- omap4_prminst_write_inst_reg(vp->tranxdone_status,
++ omap4_prminst_write_inst_reg(irq->tranxdone_status,
+ OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_OCP_SOCKET_INST,
+- vp->irqstatus_mpu);
++ irq->irqstatus_mpu);
+ };
+
+ u32 omap4_prm_vcvp_read(u8 offset)
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 3d66ccd..858ee53 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -751,9 +751,12 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+ extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
++#define OMAP4_PRM_IRQ_VDD_CORE_ID 0
++#define OMAP4_PRM_IRQ_VDD_IVA_ID 1
++#define OMAP4_PRM_IRQ_VDD_MPU_ID 2
+ /* OMAP4-specific VP functions */
+-u32 omap4_prm_vp_check_txdone(u8 vp_id);
+-void omap4_prm_vp_clear_txdone(u8 vp_id);
++u32 omap4_prm_vp_check_txdone(u8 irq_id);
++void omap4_prm_vp_clear_txdone(u8 irq_id);
+
+ /*
+ * OMAP4 access functions for voltage controller (VC) and
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index d9bc4f1..ee31e2f 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -21,15 +21,6 @@
+
+ struct voltagedomain;
+
+-/*
+- * Voltage Processor (VP) identifiers
+- */
+-#define OMAP3_VP_VDD_MPU_ID 0
+-#define OMAP3_VP_VDD_CORE_ID 1
+-#define OMAP4_VP_VDD_CORE_ID 0
+-#define OMAP4_VP_VDD_IVA_ID 1
+-#define OMAP4_VP_VDD_MPU_ID 2
+-
+ /* XXX document */
+ #define VP_IDLE_TIMEOUT 200
+ #define VP_TRANXDONE_TIMEOUT 300
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index 260c554..7bd8181 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -57,7 +57,7 @@ static const struct omap_vp_common omap3_vp_common = {
+ };
+
+ struct omap_vp_instance omap3_vp_mpu = {
+- .id = OMAP3_VP_VDD_MPU_ID,
++ .id = OMAP3_PRM_IRQ_VDD_MPU_ID,
+ .common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+@@ -68,7 +68,7 @@ struct omap_vp_instance omap3_vp_mpu = {
+ };
+
+ struct omap_vp_instance omap3_vp_core = {
+- .id = OMAP3_VP_VDD_CORE_ID,
++ .id = OMAP3_PRM_IRQ_VDD_CORE_ID,
+ .common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index b4e7704..6de8ed6 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -56,7 +56,7 @@ static const struct omap_vp_common omap4_vp_common = {
+ };
+
+ struct omap_vp_instance omap4_vp_mpu = {
+- .id = OMAP4_VP_VDD_MPU_ID,
++ .id = OMAP4_PRM_IRQ_VDD_MPU_ID,
+ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+@@ -67,7 +67,7 @@ struct omap_vp_instance omap4_vp_mpu = {
+ };
+
+ struct omap_vp_instance omap4_vp_iva = {
+- .id = OMAP4_VP_VDD_IVA_ID,
++ .id = OMAP4_PRM_IRQ_VDD_IVA_ID,
+ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+@@ -78,7 +78,7 @@ struct omap_vp_instance omap4_vp_iva = {
+ };
+
+ struct omap_vp_instance omap4_vp_core = {
+- .id = OMAP4_VP_VDD_CORE_ID,
++ .id = OMAP4_PRM_IRQ_VDD_CORE_ID,
+ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0003-OMAP3-PRM-add-tranxdone-IRQ-handlers-for-ABB.patch b/recipes-kernel/linux/linux-3.0/bias/0003-OMAP3-PRM-add-tranxdone-IRQ-handlers-for-ABB.patch
--- /dev/null
@@ -0,0 +1,202 @@
+From 6dd3408940048af572773518f8646226828e7275 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Wed, 29 Jun 2011 17:25:55 -0700
+Subject: [PATCH 3/8] OMAP3+: PRM: add tranxdone IRQ handlers for ABB
+
+OMAP3 and more recent platforms support a PRM interrupt to the MPU for
+Adapative Body-Bias ldo transitions.
+
+Add helpers to the OMAP3 & OMAP4 PRM code to check the status of the
+interrupt and also to clear it. These will be called from the ABB code
+as part of the greater voltage scaling sequence.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/prm2xxx_3xxx.c | 35 ++++++++++++++++++++++++++-----
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 3 ++
+ arch/arm/mach-omap2/prm44xx.c | 40 +++++++++++++++++++++++++++++------
+ arch/arm/mach-omap2/prm44xx.h | 3 ++
+ 4 files changed, 68 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+index 8a20242..49e9719 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+@@ -163,18 +163,23 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+
+ /*
+ * struct omap3_prm_irq - OMAP3 PRM IRQ register access description.
+- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ * @vp_tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ * @abb_tranxdone_status: ABB_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ * (ONLY for OMAP3630)
+ */
+ struct omap3_prm_irq {
+- u32 tranxdone_status;
++ u32 vp_tranxdone_status;
++ u32 abb_tranxdone_status;
+ };
+
+ static struct omap3_prm_irq omap3_prm_irqs[] = {
+ [OMAP3_PRM_IRQ_VDD_MPU_ID] = {
+- .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
++ .vp_tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
++ .abb_tranxdone_status = OMAP3630_ABB_LDO_TRANXDONE_ST_MASK,
+ },
+ [OMAP3_PRM_IRQ_VDD_CORE_ID] = {
+- .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
++ .vp_tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
++ /* no abb for core */
+ },
+ };
+
+@@ -187,14 +192,32 @@ u32 omap3_prm_vp_check_txdone(u8 irq_id)
+
+ irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+ OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+- return irqstatus & irq->tranxdone_status;
++ return irqstatus & irq->vp_tranxdone_status;
+ }
+
+ void omap3_prm_vp_clear_txdone(u8 irq_id)
+ {
+ struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
+
+- omap2_prm_write_mod_reg(irq->tranxdone_status,
++ omap2_prm_write_mod_reg(irq->vp_tranxdone_status,
++ OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
++}
++
++u32 omap36xx_prm_abb_check_txdone(u8 irq_id)
++{
++ struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
++ u32 irqstatus;
++
++ irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
++ OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
++ return irqstatus & irq->abb_tranxdone_status;
++}
++
++void omap36xx_prm_abb_clear_txdone(u8 irq_id)
++{
++ struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
++
++ omap2_prm_write_mod_reg(irq->abb_tranxdone_status,
+ OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ }
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index d90b23f..08d5f1e 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -313,6 +313,9 @@ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+ u32 omap3_prm_vp_check_txdone(u8 irq_id);
+ void omap3_prm_vp_clear_txdone(u8 irq_id);
+
++/* OMAP36xx-specific ABB functions */
++u32 omap36xx_prm_abb_check_txdone(u8 irq_id);
++void omap36xx_prm_abb_clear_txdone(u8 irq_id);
+
+ /*
+ * OMAP3 access functions for voltage controller (VC) and
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index b77d331..dd3776c 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -59,25 +59,30 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+ /*
+ * struct omap4_prm_irq - OMAP4 VP register access description.
+ * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
+- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ * @vp_tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ * @abb_tranxdone_status: ABB_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+ struct omap4_prm_irq {
+ u32 irqstatus_mpu;
+- u32 tranxdone_status;
++ u32 vp_tranxdone_status;
++ u32 abb_tranxdone_status;
+ };
+
+ static struct omap4_prm_irq omap4_prm_irqs[] = {
+ [OMAP4_PRM_IRQ_VDD_MPU_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+- .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
++ .vp_tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
++ .abb_tranxdone_status = OMAP4430_ABB_MPU_DONE_ST_MASK
+ },
+ [OMAP4_PRM_IRQ_VDD_IVA_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+- .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
++ .vp_tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
++ .abb_tranxdone_status = OMAP4430_ABB_IVA_DONE_ST_MASK,
+ },
+ [OMAP4_PRM_IRQ_VDD_CORE_ID] = {
+ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+- .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
++ .vp_tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
++ /* Core has no ABB */
+ },
+ };
+
+@@ -89,19 +94,40 @@ u32 omap4_prm_vp_check_txdone(u8 irq_id)
+ irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_OCP_SOCKET_INST,
+ irq->irqstatus_mpu);
+- return irqstatus & irq->tranxdone_status;
++ return irqstatus & irq->vp_tranxdone_status;
+ }
+
+ void omap4_prm_vp_clear_txdone(u8 irq_id)
+ {
+ struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
+
+- omap4_prminst_write_inst_reg(irq->tranxdone_status,
++ omap4_prminst_write_inst_reg(irq->vp_tranxdone_status,
+ OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_OCP_SOCKET_INST,
+ irq->irqstatus_mpu);
+ };
+
++u32 omap4_prm_abb_check_txdone(u8 irq_id)
++{
++ struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
++ u32 irqstatus;
++
++ irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_OCP_SOCKET_INST,
++ irq->irqstatus_mpu);
++ return irqstatus & irq->abb_tranxdone_status;
++}
++
++void omap4_prm_abb_clear_txdone(u8 irq_id)
++{
++ struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
++
++ omap4_prminst_write_inst_reg(irq->abb_tranxdone_status,
++ OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_OCP_SOCKET_INST,
++ irq->irqstatus_mpu);
++}
++
+ u32 omap4_prm_vcvp_read(u8 offset)
+ {
+ return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 858ee53..8ce3207 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -757,6 +757,9 @@ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+ /* OMAP4-specific VP functions */
+ u32 omap4_prm_vp_check_txdone(u8 irq_id);
+ void omap4_prm_vp_clear_txdone(u8 irq_id);
++/* OMAP4-specific ABB functions */
++u32 omap4_prm_abb_check_txdone(u8 irq_id);
++void omap4_prm_abb_clear_txdone(u8 irq_id);
+
+ /*
+ * OMAP4 access functions for voltage controller (VC) and
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0004-OMAP3-ABB-Adaptive-Body-Bias-structures-data.patch b/recipes-kernel/linux/linux-3.0/bias/0004-OMAP3-ABB-Adaptive-Body-Bias-structures-data.patch
--- /dev/null
@@ -0,0 +1,240 @@
+From cd3d2049b3c59b5b28efe81b91f4051fea51687b Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Wed, 29 Jun 2011 17:25:56 -0700
+Subject: [PATCH 4/8] OMAP3+: ABB: Adaptive Body-Bias structures & data
+
+Due to voltage domain trimming and silicon characterstics some silicon
+may experience instability when operating at a high voltage. To
+compensate for this an Adaptive Body-Bias ldo exists. First featured in
+OMAP3630, the purpose of this ldo is to provide a voltage boost to PMOS
+backgates when a voltage domain is operating at a high OPP. In this
+mode the ldo is said to be in Forward Body-Bias. At OPPs within a
+nominal voltage range the ABB ldo is bypassed.
+
+This patch introduces the data structures needed to represent the ABB
+ldo's in the voltage layer, and populates the appropriate data for 3630
+and OMAP4. Not all voltage domains have an ABB ldo, and OMAP34xx does
+not have it at all; in such cases the voltage data will be marked with
+OMAP_ABB_NO_LDO.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 5 +-
+ arch/arm/mach-omap2/abb.h | 85 ++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/abb36xx_data.c | 38 ++++++++++++++++
+ arch/arm/mach-omap2/abb44xx_data.c | 44 ++++++++++++++++++
+ 4 files changed, 170 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/abb.h
+ create mode 100644 arch/arm/mach-omap2/abb36xx_data.c
+ create mode 100644 arch/arm/mach-omap2/abb44xx_data.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 7927dd6..5bc306c 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -82,14 +82,15 @@ endif
+ # PRCM
+ obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+ obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
+- vc3xxx_data.o vp3xxx_data.o
++ vc3xxx_data.o vp3xxx_data.o \
++ abb36xx_data.o
+ # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
+ # will be removed once the OMAP4 part of the codebase is converted to
+ # use OMAP4-specific PRCM functions.
+ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+ cm44xx.o prcm_mpu44xx.o \
+ prminst44xx.o vc44xx_data.o \
+- vp44xx_data.o
++ vp44xx_data.o abb44xx_data.o
+
+ # OMAP voltage domains
+ ifeq ($(CONFIG_PM),y)
+diff --git a/arch/arm/mach-omap2/abb.h b/arch/arm/mach-omap2/abb.h
+new file mode 100644
+index 0000000..74f2044
+--- /dev/null
++++ b/arch/arm/mach-omap2/abb.h
+@@ -0,0 +1,85 @@
++/*
++ * OMAP Adaptive Body-Bias structure and macro definitions
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc.
++ * Mike Turquette <mturquette@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ARCH_ARM_MACH_OMAP2_ABB_H
++#define __ARCH_ARM_MACH_OMAP2_ABB_H
++
++#include <linux/kernel.h>
++
++#include "voltage.h"
++
++/* NOMINAL_OPP bypasses the ABB ldo, FAST_OPP sets it to Forward Body-Bias */
++#define OMAP_ABB_NOMINAL_OPP 0
++#define OMAP_ABB_FAST_OPP 1
++#define OMAP_ABB_NO_LDO ~0
++
++/* Time for the ABB ldo to settle after transition (in micro-seconds) */
++#define ABB_TRANXDONE_TIMEOUT 50
++
++/*
++ * struct omap_abb_ops - per-OMAP operations needed for ABB transition
++ *
++ * @check_tranxdone: return status of ldo transition from PRM_IRQSTATUS
++ * @clear_tranxdone: clear ABB transition status bit from PRM_IRQSTATUS
++ */
++struct omap_abb_ops {
++ u32 (*check_tranxdone)(u8 irq_id);
++ void (*clear_tranxdone)(u8 irq_id);
++};
++
++/*
++ * struct omap_abb_common - ABB data common to an OMAP family
++ *
++ * @opp_sel_mask: CTRL reg uses this to program next state of ldo
++ * @opp_change_mask: CTRL reg uses this to initiate ldo state change
++ * @sr2_wtcnt_value_mask: SETUP reg uses this to program ldo settling time
++ * @sr2en_mask: SETUP reg uses this to enable/disable ldo
++ * @active_fbb_sel_mask: SETUP reg uses this to enable/disable FBB operation
++ * @settling_time: number of micro-seconds it takes for ldo to transition
++ * @clock_cycles: settling_time is counted in multiples of clock cycles
++ * @ops: pointer to common ops for manipulating PRM_IRQSTATUS bits
++ */
++struct omap_abb_common {
++ u32 opp_sel_mask;
++ u32 opp_change_mask;
++ u32 sr2_wtcnt_value_mask;
++ u32 sr2en_mask;
++ u32 active_fbb_sel_mask;
++ unsigned long settling_time;
++ unsigned long clock_cycles;
++ const struct omap_abb_ops *ops;
++};
++
++/*
++ * struct omap_abb_instance - data for each instance of ABB ldo
++ *
++ * @setup_offs: PRM register offset for initial configuration of ABB ldo
++ * @ctrl_offs: PRM register offset for active programming of ABB ldo
++ * @prm_irq_id: IRQ handle used to resolve IRQSTATUS offset & masks
++ * @enabled: track whether ABB ldo is enabled or disabled
++ * @common: pointer to common data for all ABB ldo's
++ * @_opp_sel: internally track last programmed state of ABB ldo. DO NOT USE
++ */
++struct omap_abb_instance {
++ u8 setup_offs;
++ u8 ctrl_offs;
++ u8 prm_irq_id;
++ bool enabled;
++ const struct omap_abb_common *common;
++ u8 _opp_sel;
++};
++
++extern struct omap_abb_instance omap36xx_abb_mpu;
++
++extern struct omap_abb_instance omap4_abb_mpu;
++extern struct omap_abb_instance omap4_abb_iva;
++
++#endif
+diff --git a/arch/arm/mach-omap2/abb36xx_data.c b/arch/arm/mach-omap2/abb36xx_data.c
+new file mode 100644
+index 0000000..0bcfd66
+--- /dev/null
++++ b/arch/arm/mach-omap2/abb36xx_data.c
+@@ -0,0 +1,38 @@
++/*
++ * OMAP36xx Adaptive Body-Bias (ABB) data
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc.
++ * Mike Turquette <mturquette@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "abb.h"
++#include "prm2xxx_3xxx.h"
++#include "prm-regbits-34xx.h"
++
++static const struct omap_abb_ops omap36xx_abb_ops = {
++ .check_tranxdone = &omap36xx_prm_abb_check_txdone,
++ .clear_tranxdone = &omap36xx_prm_abb_clear_txdone,
++};
++
++static const struct omap_abb_common omap36xx_abb_common = {
++ .opp_sel_mask = OMAP3630_OPP_SEL_MASK,
++ .opp_change_mask = OMAP3630_OPP_CHANGE_MASK,
++ .sr2en_mask = OMAP3630_SR2EN_MASK,
++ .active_fbb_sel_mask = OMAP3630_ACTIVE_FBB_SEL_MASK,
++ .sr2_wtcnt_value_mask = OMAP3630_SR2_WTCNT_VALUE_MASK,
++ .settling_time = 30,
++ .clock_cycles = 8,
++ .ops = &omap36xx_abb_ops,
++};
++
++/* SETUP & CTRL registers swapped names in OMAP4; thus 36xx looks strange */
++struct omap_abb_instance omap36xx_abb_mpu = {
++ .setup_offs = OMAP3_PRM_LDO_ABB_CTRL_OFFSET,
++ .ctrl_offs = OMAP3_PRM_LDO_ABB_SETUP_OFFSET,
++ .prm_irq_id = OMAP3_PRM_IRQ_VDD_MPU_ID,
++ .common = &omap36xx_abb_common,
++};
+diff --git a/arch/arm/mach-omap2/abb44xx_data.c b/arch/arm/mach-omap2/abb44xx_data.c
+new file mode 100644
+index 0000000..a7cf855
+--- /dev/null
++++ b/arch/arm/mach-omap2/abb44xx_data.c
+@@ -0,0 +1,44 @@
++/*
++ * OMAP44xx Adaptive Body-Bias (ABB) data
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc.
++ * Mike Turquette <mturquette@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "abb.h"
++#include "prm44xx.h"
++#include "prm-regbits-44xx.h"
++
++static const struct omap_abb_ops omap4_abb_ops = {
++ .check_tranxdone = &omap4_prm_abb_check_txdone,
++ .clear_tranxdone = &omap4_prm_abb_clear_txdone,
++};
++
++static const struct omap_abb_common omap4_abb_common = {
++ .opp_sel_mask = OMAP4430_OPP_SEL_MASK,
++ .opp_change_mask = OMAP4430_OPP_CHANGE_MASK,
++ .sr2en_mask = OMAP4430_SR2EN_MASK,
++ .active_fbb_sel_mask = OMAP4430_ACTIVE_FBB_SEL_MASK,
++ .sr2_wtcnt_value_mask = OMAP4430_SR2_WTCNT_VALUE_MASK,
++ .settling_time = 50,
++ .clock_cycles = 16,
++ .ops = &omap4_abb_ops,
++};
++
++struct omap_abb_instance omap4_abb_mpu = {
++ .setup_offs = OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET,
++ .ctrl_offs = OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET,
++ .prm_irq_id = OMAP4_PRM_IRQ_VDD_MPU_ID,
++ .common = &omap4_abb_common,
++};
++
++struct omap_abb_instance omap4_abb_iva = {
++ .setup_offs = OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET,
++ .ctrl_offs = OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET,
++ .prm_irq_id = OMAP4_PRM_IRQ_VDD_IVA_ID,
++ .common = &omap4_abb_common,
++};
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0005-OMAP3-OPP-add-ABB-data-to-voltage-tables.patch b/recipes-kernel/linux/linux-3.0/bias/0005-OMAP3-OPP-add-ABB-data-to-voltage-tables.patch
--- /dev/null
@@ -0,0 +1,194 @@
+From dbbe5cde8c8c9b055ba8bd22d329149b2a0a09e2 Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Wed, 29 Jun 2011 17:25:57 -0700
+Subject: [PATCH 5/8] OMAP3+: OPP: add ABB data to voltage tables
+
+The operating mode of the Adaptive Body-Bias ldo maps directly to the
+voltage of its voltage domain. The two modes supported are bypass and
+Forward Body-Bias (FBB).
+
+This patch models this relationship by adding an opp_sel paramter to
+struct omap_volt_data and populates this type in the 3630 and 4430
+voltage tables.
+
+NOMINAL_OPP causes the ABB ldo to be in bypass at that specific voltage.
+FAST_OPP causes the ldo to operate in Forward Body-Bias mode.
+
+Not all voltage domains have an ABB ldo and 3430 doesn't have one at
+all. In such cases voltages are marked with OMAP_ABB_NO_LDO.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/omap_opp_data.h | 5 ++-
+ arch/arm/mach-omap2/opp3xxx_data.c | 37 ++++++++++++++++++-----------------
+ arch/arm/mach-omap2/opp4xxx_data.c | 25 ++++++++++++-----------
+ arch/arm/mach-omap2/voltage.h | 1 +
+ 4 files changed, 36 insertions(+), 32 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
+index c784c12..5dd4dea 100644
+--- a/arch/arm/mach-omap2/omap_opp_data.h
++++ b/arch/arm/mach-omap2/omap_opp_data.h
+@@ -71,12 +71,13 @@ struct omap_opp_def {
+ * Initialization wrapper used to define SmartReflex process data
+ * XXX Is this needed? Just use C99 initializers in data files?
+ */
+-#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
++#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain, _opp_sel) \
+ { \
+ .volt_nominal = _v_nom, \
+ .sr_efuse_offs = _efuse_offs, \
+ .sr_errminlimit = _errminlimit, \
+- .vp_errgain = _errgain \
++ .vp_errgain = _errgain, \
++ .opp_sel = _opp_sel \
+ }
+
+ /* Use this to initialize the default table */
+diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
+index d95f3f9..12fc2da 100644
+--- a/arch/arm/mach-omap2/opp3xxx_data.c
++++ b/arch/arm/mach-omap2/opp3xxx_data.c
+@@ -24,6 +24,7 @@
+ #include "control.h"
+ #include "omap_opp_data.h"
+ #include "pm.h"
++#include "abb.h"
+
+ /* 34xx */
+
+@@ -36,12 +37,12 @@
+ #define OMAP3430_VDD_MPU_OPP5_UV 1350000
+
+ struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ /* VDD2 */
+@@ -51,10 +52,10 @@ struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+ #define OMAP3430_VDD_CORE_OPP3_UV 1150000
+
+ struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ /* 36xx */
+@@ -67,11 +68,11 @@ struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+ #define OMAP3630_VDD_MPU_OPP1G_UV 1375000
+
+ struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ /* VDD2 */
+@@ -80,9 +81,9 @@ struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+ #define OMAP3630_VDD_CORE_OPP100_UV 1200000
+
+ struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ /* OPP data */
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index 2293ba2..efdbf91 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -25,6 +25,7 @@
+ #include "control.h"
+ #include "omap_opp_data.h"
+ #include "pm.h"
++#include "abb.h"
+
+ /*
+ * Structures containing OMAP4430 voltage supported and various
+@@ -37,11 +38,11 @@
+ #define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
+
+ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ #define OMAP4430_VDD_IVA_OPP50_UV 1013000
+@@ -49,19 +50,19 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+ #define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
+
+ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+ #define OMAP4430_VDD_CORE_OPP50_UV 1025000
+ #define OMAP4430_VDD_CORE_OPP100_UV 1200000
+
+ struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16, OMAP_ABB_NO_LDO),
++ VOLT_DATA_DEFINE(0, 0, 0, 0, 0),
+ };
+
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index b4c6259..2aa6c43 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -105,6 +105,7 @@ struct omap_volt_data {
+ u32 sr_efuse_offs;
+ u8 sr_errminlimit;
+ u8 vp_errgain;
++ u32 opp_sel;
+ };
+
+ /**
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0006-OMAP3-Voltage-add-ABB-data-to-voltage-domains.patch b/recipes-kernel/linux/linux-3.0/bias/0006-OMAP3-Voltage-add-ABB-data-to-voltage-domains.patch
--- /dev/null
@@ -0,0 +1,83 @@
+From 25458f46e77c4e816d313126a789d69f98f73af4 Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Thu, 21 Jul 2011 12:31:50 +0200
+Subject: [PATCH 6/8] OMAP3+: Voltage: add ABB data to voltage domains
+
+Starting with OMAP36xx, some voltage domains have an ABB ldo meant to
+insure stability when that voltage domain is operating at a high OPP.
+
+This patch adds struct omap_abb_instance to struct voltagedomain and
+populates the data for those voltage domains that have an ABB ldo on
+both 36xx and 44xx silicon.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/voltage.h | 1 +
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 3 +++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 3 +++
+ 3 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 2aa6c43..4fe35d7 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -69,6 +69,7 @@ struct voltagedomain {
+ struct omap_vc_channel *vc;
+ const struct omap_vfsm_instance *vfsm;
+ struct omap_vp_instance *vp;
++ struct omap_abb_instance *abb;
+ struct omap_voltdm_pmic *pmic;
+
+ /* VC/VP register access functions: SoC specific */
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index b0d0ae1..cdcfbdf 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -26,6 +26,7 @@
+ #include "voltage.h"
+ #include "vc.h"
+ #include "vp.h"
++#include "abb.h"
+
+ /*
+ * VDD data
+@@ -90,6 +91,8 @@ void __init omap3xxx_voltagedomains_init(void)
+ if (cpu_is_omap3630()) {
+ omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
+ omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
++
++ omap3_voltdm_mpu.abb = &omap36xx_abb_mpu;
+ } else {
+ omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
+ omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index c4584e9..11e2458 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -31,6 +31,7 @@
+ #include "omap_opp_data.h"
+ #include "vc.h"
+ #include "vp.h"
++#include "abb.h"
+
+ static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+@@ -53,6 +54,7 @@ static struct voltagedomain omap4_voltdm_mpu = {
+ .vc = &omap4_vc_mpu,
+ .vfsm = &omap4_vdd_mpu_vfsm,
+ .vp = &omap4_vp_mpu,
++ .abb = &omap4_abb_mpu,
+ };
+
+ static struct voltagedomain omap4_voltdm_iva = {
+@@ -64,6 +66,7 @@ static struct voltagedomain omap4_voltdm_iva = {
+ .vc = &omap4_vc_iva,
+ .vfsm = &omap4_vdd_iva_vfsm,
+ .vp = &omap4_vp_iva,
++ .abb = &omap4_abb_iva,
+ };
+
+ static struct voltagedomain omap4_voltdm_core = {
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0007-OMAP3-ABB-initialization-transition-functions.patch b/recipes-kernel/linux/linux-3.0/bias/0007-OMAP3-ABB-initialization-transition-functions.patch
--- /dev/null
@@ -0,0 +1,274 @@
+From d9dd20e6220aa04f17ec44f64a0b1545407ae8f9 Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Wed, 29 Jun 2011 17:25:59 -0700
+Subject: [PATCH 7/8] OMAP3+: ABB: initialization & transition functions
+
+The Adaptive Body-Bias ldo can be set to bypass or Forward Body-Bias
+after voltage scaling is performed.
+
+This patch implements the Adaptive Body-Bias ldo initialization routine
+and the transition sequence which is needed after a vc_bypass or
+vp_forceupdate sequence completes.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/abb.c | 218 ++++++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/abb.h | 5 +
+ 3 files changed, 224 insertions(+), 1 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/abb.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 5bc306c..d0dd488 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -94,7 +94,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+
+ # OMAP voltage domains
+ ifeq ($(CONFIG_PM),y)
+-voltagedomain-common := voltage.o vc.o vp.o
++voltagedomain-common := voltage.o vc.o vp.o abb.o
+ obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
+ voltagedomains2xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
+diff --git a/arch/arm/mach-omap2/abb.c b/arch/arm/mach-omap2/abb.c
+new file mode 100644
+index 0000000..4d42b67
+--- /dev/null
++++ b/arch/arm/mach-omap2/abb.c
+@@ -0,0 +1,218 @@
++/*
++ * OMAP Adaptive Body-Bias core
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc.
++ * Mike Turquette <mturquette@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/delay.h>
++
++#include "abb.h"
++#include "voltage.h"
++
++/*
++ * omap_abb_set_opp - program ABB ldo based on new voltage
++ *
++ * @voltdm - pointer to voltage domain that just finished scaling voltage
++ *
++ * Look up the ABB ldo state for the new voltage that voltdm just finished
++ * transitioning to and compare it to current ldo state. If a change is needed
++ * then clear appropriate PRM_IRQSTATUS bit, transition ldo and then clear
++ * PRM_IRQSTATUS bit again. Returns 0 on success, -EERROR otherwise.
++ */
++int omap_abb_set_opp(struct voltagedomain *voltdm)
++{
++ struct omap_abb_instance *abb = voltdm->abb;
++ struct omap_volt_data *volt_data;
++ int ret, timeout;
++ u8 opp_sel;
++
++ /* fetch the ABB ldo OPP_SEL value for the new voltage */
++ volt_data = omap_voltage_get_voltdata(voltdm, voltdm->nominal_volt);
++
++ if (IS_ERR_OR_NULL(volt_data))
++ return -EINVAL;
++
++ opp_sel = volt_data->opp_sel;
++
++ /* bail early if no transition is necessary */
++ if (opp_sel == abb->_opp_sel)
++ return 0;
++
++ /* clear interrupt status */
++ timeout = 0;
++ while (timeout++ < ABB_TRANXDONE_TIMEOUT) {
++ abb->common->ops->clear_tranxdone(abb->prm_irq_id);
++
++ ret = abb->common->ops->check_tranxdone(abb->prm_irq_id);
++ if (!ret)
++ break;
++
++ udelay(1);
++ }
++
++ if (timeout>= ABB_TRANXDONE_TIMEOUT) {
++ pr_warning("%s: vdd_%s ABB TRANXDONE timeout\n",
++ __func__, voltdm->name);
++ return -ETIMEDOUT;
++ }
++
++ /* program next state of ABB ldo */
++ voltdm->rmw(abb->common->opp_sel_mask,
++ opp_sel << __ffs(abb->common->opp_sel_mask),
++ abb->ctrl_offs);
++
++ /* initiate ABB ldo change */
++ voltdm->rmw(abb->common->opp_change_mask,
++ abb->common->opp_change_mask,
++ abb->ctrl_offs);
++
++ /* clear interrupt status */
++ timeout = 0;
++ while (timeout++ < ABB_TRANXDONE_TIMEOUT) {
++ abb->common->ops->clear_tranxdone(abb->prm_irq_id);
++
++ ret = abb->common->ops->check_tranxdone(abb->prm_irq_id);
++ if (!ret)
++ break;
++
++ udelay(1);
++ }
++
++ if (timeout>= ABB_TRANXDONE_TIMEOUT) {
++ pr_warning("%s: vdd_%s ABB TRANXDONE timeout\n",
++ __func__, voltdm->name);
++ return -ETIMEDOUT;
++ }
++
++ /* track internal state */
++ abb->_opp_sel = opp_sel;
++
++ return 0;
++}
++
++/*
++ * omap_abb_enable - enable ABB ldo on a particular voltage domain
++ *
++ * @voltdm - pointer to particular voltage domain
++ */
++void omap_abb_enable(struct voltagedomain *voltdm)
++{
++ struct omap_abb_instance *abb = voltdm->abb;
++
++ if (abb->enabled)
++ return;
++
++ abb->enabled = true;
++
++ voltdm->rmw(abb->common->sr2en_mask, abb->common->sr2en_mask,
++ abb->setup_offs);
++}
++
++/*
++ * omap_abb_disable - disable ABB ldo on a particular voltage domain
++ *
++ * @voltdm - pointer to particular voltage domain
++ *
++ * Included for completeness. Not currently used but will be needed in the
++ * future if ABB is converted to a loadable module.
++ */
++void omap_abb_disable(struct voltagedomain *voltdm)
++{
++ struct omap_abb_instance *abb = voltdm->abb;
++
++ if (!abb->enabled)
++ return;
++
++ abb->enabled = false;
++
++ voltdm->rmw(abb->common->sr2en_mask,
++ (0 << __ffs(abb->common->sr2en_mask)),
++ abb->setup_offs);
++}
++
++/*
++ * omap_abb_init - Initialize an ABB ldo instance
++ *
++ * @voltdm: voltage domain upon which ABB ldo resides
++ *
++ * Initializes an individual ABB ldo for Forward Body-Bias. FBB is used to
++ * insure stability at higher voltages. Note that some older OMAP chips have a
++ * Reverse Body-Bias mode meant to save power at low voltage, but that mode is
++ * unsupported and phased out on newer chips.
++ */
++void __init omap_abb_init(struct voltagedomain *voltdm)
++{
++ struct omap_abb_instance *abb = voltdm->abb;
++ u32 sys_clk_rate;
++ u32 sr2_wt_cnt_val;
++ u32 clock_cycles;
++ u32 settling_time;
++ u32 val;
++
++ if(IS_ERR_OR_NULL(abb))
++ return;
++
++ /*
++ * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
++ * transition and must be programmed with the correct time at boot.
++ * The value programmed into the register is the number of SYS_CLK
++ * clock cycles that match a given wall time profiled for the ldo.
++ * This value depends on:
++ * settling time of ldo in micro-seconds (varies per OMAP family)
++ * # of clock cycles per SYS_CLK period (varies per OMAP family)
++ * the SYS_CLK frequency in MHz (varies per board)
++ * The formula is:
++ *
++ * ldo settling time (in micro-seconds)
++ * SR2_WTCNT_VALUE = ------------------------------------------
++ * (# system clock cycles) * (sys_clk period)
++ *
++ * Put another way:
++ *
++ * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
++ *
++ * To avoid dividing by zero multiply both "# clock cycles" and
++ * "settling time" by 10 such that the final result is the one we want.
++ */
++
++ /* convert SYS_CLK rate to MHz & prevent divide by zero */
++ sys_clk_rate = DIV_ROUND_CLOSEST(voltdm->sys_clk.rate, 1000000);
++ clock_cycles = abb->common->clock_cycles * 10;
++ settling_time = abb->common->settling_time * 10;
++
++ /* calculate cycle rate */
++ clock_cycles = DIV_ROUND_CLOSEST(clock_cycles, sys_clk_rate);
++
++ /* calulate SR2_WTCNT_VALUE */
++ sr2_wt_cnt_val = DIV_ROUND_CLOSEST(settling_time, clock_cycles);
++
++ voltdm->rmw(abb->common->sr2_wtcnt_value_mask,
++ (sr2_wt_cnt_val << __ffs(abb->common->sr2_wtcnt_value_mask)),
++ abb->setup_offs);
++
++ /* allow Forward Body-Bias */
++ voltdm->rmw(abb->common->active_fbb_sel_mask,
++ abb->common->active_fbb_sel_mask,
++ abb->setup_offs);
++
++ /* did bootloader set OPP_SEL? */
++ val = voltdm->read(abb->ctrl_offs);
++ val &= abb->common->opp_sel_mask;
++ abb->_opp_sel = val >> __ffs(abb->common->opp_sel_mask);
++
++ /* enable the ldo if not done by bootloader */
++ val = voltdm->read(abb->setup_offs);
++ val &= abb->common->sr2en_mask;
++ if (val)
++ abb->enabled = true;
++ else
++ omap_abb_enable(voltdm);
++
++ return;
++}
+diff --git a/arch/arm/mach-omap2/abb.h b/arch/arm/mach-omap2/abb.h
+index 74f2044..c06c7d6 100644
+--- a/arch/arm/mach-omap2/abb.h
++++ b/arch/arm/mach-omap2/abb.h
+@@ -82,4 +82,9 @@ extern struct omap_abb_instance omap36xx_abb_mpu;
+ extern struct omap_abb_instance omap4_abb_mpu;
+ extern struct omap_abb_instance omap4_abb_iva;
+
++void omap_abb_init(struct voltagedomain *voltdm);
++void omap_abb_enable(struct voltagedomain *voltdm);
++void omap_abb_disble(struct voltagedomain *voltdm);
++int omap_abb_set_opp(struct voltagedomain *voltdm);
++
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/bias/0008-OMAP3-Voltage-add-ABB-to-voltage-scaling.patch b/recipes-kernel/linux/linux-3.0/bias/0008-OMAP3-Voltage-add-ABB-to-voltage-scaling.patch
--- /dev/null
@@ -0,0 +1,114 @@
+From 5d8a37a58e5ad0bd385f023453277d9aebd4768a Mon Sep 17 00:00:00 2001
+From: Mike Turquette <mturquette@ti.com>
+Date: Thu, 21 Jul 2011 12:36:37 +0200
+Subject: [PATCH 8/8] OMAP3+: Voltage: add ABB to voltage scaling
+
+Adaptive Body-Bias ldo state should be transitioned (if necessary) after
+a voltage scaling sequence completes via vc_bypass or vp_forceupdate
+methods.
+
+This patch initializes the ABB ldo's as a part of the greater voltage
+initialization function and adds the ABB transition routine to both the
+vc_bypass and vp_forceupdate sequences.
+
+Signed-off-by: Mike Turquette <mturquette@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 10 ++++++++--
+ arch/arm/mach-omap2/voltage.c | 4 ++++
+ arch/arm/mach-omap2/vp.c | 9 +++++++--
+ 3 files changed, 19 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 16fa912..c5d8550 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -6,6 +6,7 @@
+
+ #include "voltage.h"
+ #include "vc.h"
++#include "abb.h"
+ #include "prm-regbits-34xx.h"
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+@@ -153,7 +154,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+ u8 target_vsel, current_vsel;
+- int ret;
++ int ret = 0;
+
+ ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+@@ -191,7 +192,12 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ }
+
+ omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+- return 0;
++
++ /* transition Adaptive Body-Bias ldo */
++ if (voltdm->abb)
++ ret = omap_abb_set_opp(voltdm);
++
++ return ret;
+ }
+
+ static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index cebc8b1..25f8604 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -40,6 +40,7 @@
+
+ #include "vc.h"
+ #include "vp.h"
++#include "abb.h"
+
+ static LIST_HEAD(voltdm_list);
+
+@@ -279,6 +280,9 @@ int __init omap_voltage_late_init(void)
+ voltdm->scale = omap_vp_forceupdate_scale;
+ omap_vp_init(voltdm);
+ }
++
++ if (voltdm->abb)
++ omap_abb_init(voltdm);
+ }
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 66bd700..886be89 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -5,6 +5,7 @@
+
+ #include "voltage.h"
+ #include "vp.h"
++#include "abb.h"
+ #include "prm-regbits-34xx.h"
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+@@ -116,7 +117,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ struct omap_vp_instance *vp = voltdm->vp;
+ u32 vpconfig;
+ u8 target_vsel, current_vsel;
+- int ret, timeout = 0;
++ int ret = 0, timeout = 0;
+
+ ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+@@ -178,7 +179,11 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ /* Clear force bit */
+ voltdm->write(vpconfig, vp->vpconfig);
+
+- return 0;
++ /* transition Adaptive Body-Bias LDO */
++ if (voltdm->abb)
++ ret = omap_abb_set_opp(voltdm);
++
++ return ret;
+ }
+
+ /**
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0004-OMAP3-PM-debug-remove-sleep_while_idle-feature.patch b/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0004-OMAP3-PM-debug-remove-sleep_while_idle-feature.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From e38ec7b32ebb15b1e703743ea14ca7a29675a3ba Mon Sep 17 00:00:00 2001
-From: Kevin Hilman <khilman@ti.com>
-Date: Thu, 26 May 2011 14:48:19 -0700
-Subject: [PATCH 4/7] OMAP3: PM debug: remove sleep_while_idle feature
-
-Remove the OMAP-specific PM debug 'sleep_while_idle' feature which is
-currently available as an OMAP-specific debugfs entry.
-
-This duplicates existing ARM-generic functionality available as a
-boot-time option using the boot cmdline option 'hohlt'.
-
-If runtime configuration of this is needed, then adding a debugfs
-entry for the ARM-generic hlt/nohlt interface should be added.
-
-Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Acked-by: Jean Pihet <j-pihet@ti.com>
-Signed-off-by: Kevin Hilman <khilman@ti.com>
----
- arch/arm/mach-omap2/pm-debug.c | 3 ---
- arch/arm/mach-omap2/pm.h | 2 --
- arch/arm/mach-omap2/pm34xx.c | 2 --
- 3 files changed, 0 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
-index e01da45..d9f0821 100644
---- a/arch/arm/mach-omap2/pm-debug.c
-+++ b/arch/arm/mach-omap2/pm-debug.c
-@@ -40,7 +40,6 @@
-
- int omap2_pm_debug;
- u32 enable_off_mode;
--u32 sleep_while_idle;
- u32 wakeup_timer_seconds;
- u32 wakeup_timer_milliseconds;
-
-@@ -639,8 +638,6 @@ static int pm_dbg_init(void)
-
- (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
- &enable_off_mode, &pm_dbg_option_fops);
-- (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
-- &sleep_while_idle, &pm_dbg_option_fops);
- (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
- &wakeup_timer_seconds, &pm_dbg_option_fops);
- (void) debugfs_create_file("wakeup_timer_milliseconds",
-diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
-index 45bcfce..674eedc 100644
---- a/arch/arm/mach-omap2/pm.h
-+++ b/arch/arm/mach-omap2/pm.h
-@@ -69,13 +69,11 @@ extern void omap2_pm_dump(int mode, int resume, unsigned int us);
- extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
- extern int omap2_pm_debug;
- extern u32 enable_off_mode;
--extern u32 sleep_while_idle;
- #else
- #define omap2_pm_dump(mode, resume, us) do {} while (0);
- #define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
- #define omap2_pm_debug 0
- #define enable_off_mode 0
--#define sleep_while_idle 0
- #endif
-
- #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index c155c9d..cb34244 100644
---- a/arch/arm/mach-omap2/pm34xx.c
-+++ b/arch/arm/mach-omap2/pm34xx.c
-@@ -497,8 +497,6 @@ console_still_active:
-
- int omap3_can_sleep(void)
- {
-- if (!sleep_while_idle)
-- return 0;
- if (!omap_uart_can_sleep())
- return 0;
- return 1;
---
-1.6.6.1
-
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0005-OMAP2-PM-debug-remove-register-dumping.patch b/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0005-OMAP2-PM-debug-remove-register-dumping.patch
--- a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0005-OMAP2-PM-debug-remove-register-dumping.patch
+++ /dev/null
@@ -1,215 +0,0 @@
-From 51ea2570669b64adfaee2c4a757122f0376255dd Mon Sep 17 00:00:00 2001
-From: Kevin Hilman <khilman@ti.com>
-Date: Thu, 26 May 2011 14:07:41 -0700
-Subject: [PATCH 5/7] OMAP2: PM debug: remove register dumping
-
-Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Signed-off-by: Kevin Hilman <khilman@ti.com>
----
- arch/arm/mach-omap2/pm-debug.c | 119 ----------------------------------------
- arch/arm/mach-omap2/pm.h | 4 -
- arch/arm/mach-omap2/pm24xx.c | 6 +-
- 3 files changed, 2 insertions(+), 127 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
-index d9f0821..a8425d6 100644
---- a/arch/arm/mach-omap2/pm-debug.c
-+++ b/arch/arm/mach-omap2/pm-debug.c
-@@ -38,129 +38,10 @@
- #include "prm2xxx_3xxx.h"
- #include "pm.h"
-
--int omap2_pm_debug;
- u32 enable_off_mode;
- u32 wakeup_timer_seconds;
- u32 wakeup_timer_milliseconds;
-
--#define DUMP_PRM_MOD_REG(mod, reg) \
-- regs[reg_count].name = #mod "." #reg; \
-- regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
--#define DUMP_CM_MOD_REG(mod, reg) \
-- regs[reg_count].name = #mod "." #reg; \
-- regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
--#define DUMP_PRM_REG(reg) \
-- regs[reg_count].name = #reg; \
-- regs[reg_count++].val = __raw_readl(reg)
--#define DUMP_CM_REG(reg) \
-- regs[reg_count].name = #reg; \
-- regs[reg_count++].val = __raw_readl(reg)
--#define DUMP_INTC_REG(reg, off) \
-- regs[reg_count].name = #reg; \
-- regs[reg_count++].val = \
-- __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
--
--void omap2_pm_dump(int mode, int resume, unsigned int us)
--{
-- struct reg {
-- const char *name;
-- u32 val;
-- } regs[32];
-- int reg_count = 0, i;
-- const char *s1 = NULL, *s2 = NULL;
--
-- if (!resume) {
--#if 0
-- /* MPU */
-- DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
-- DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
-- DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
-- DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
-- DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
--#endif
--#if 0
-- /* INTC */
-- DUMP_INTC_REG(INTC_MIR0, 0x0084);
-- DUMP_INTC_REG(INTC_MIR1, 0x00a4);
-- DUMP_INTC_REG(INTC_MIR2, 0x00c4);
--#endif
--#if 0
-- DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
-- if (cpu_is_omap24xx()) {
-- DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-- DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
-- OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
-- DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
-- OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
-- }
-- DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
-- DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
-- DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
-- DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
-- DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
-- DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
-- DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
--#endif
--#if 0
-- /* DSP */
-- if (cpu_is_omap24xx()) {
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
-- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
-- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
-- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
-- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
-- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
-- }
--#endif
-- } else {
-- DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
-- if (cpu_is_omap24xx())
-- DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
-- DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
-- DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
--#if 1
-- DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
-- DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
-- DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
--#endif
-- }
--
-- switch (mode) {
-- case 0:
-- s1 = "full";
-- s2 = "retention";
-- break;
-- case 1:
-- s1 = "MPU";
-- s2 = "retention";
-- break;
-- case 2:
-- s1 = "MPU";
-- s2 = "idle";
-- break;
-- }
--
-- if (!resume)
--#ifdef CONFIG_NO_HZ
-- printk(KERN_INFO
-- "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
-- jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
-- jiffies));
--#else
-- printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
--#endif
-- else
-- printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
-- us / 1000, us % 1000);
--
-- for (i = 0; i < reg_count; i++)
-- printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
--}
--
- void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
- {
- u32 tick_rate, cycles;
-diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
-index 674eedc..acac275 100644
---- a/arch/arm/mach-omap2/pm.h
-+++ b/arch/arm/mach-omap2/pm.h
-@@ -65,14 +65,10 @@ extern u32 wakeup_timer_milliseconds;
- extern struct omap_dm_timer *gptimer_wakeup;
-
- #ifdef CONFIG_PM_DEBUG
--extern void omap2_pm_dump(int mode, int resume, unsigned int us);
- extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
--extern int omap2_pm_debug;
- extern u32 enable_off_mode;
- #else
--#define omap2_pm_dump(mode, resume, us) do {} while (0);
- #define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
--#define omap2_pm_debug 0
- #define enable_off_mode 0
- #endif
-
-diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
-index df3ded6..bf089e7 100644
---- a/arch/arm/mach-omap2/pm24xx.c
-+++ b/arch/arm/mach-omap2/pm24xx.c
-@@ -53,6 +53,8 @@
- #include "powerdomain.h"
- #include "clockdomain.h"
-
-+static int omap2_pm_debug;
-+
- #ifdef CONFIG_SUSPEND
- static suspend_state_t suspend_state = PM_SUSPEND_ON;
- static inline bool is_suspending(void)
-@@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
- omap2_gpio_prepare_for_idle(0);
-
- if (omap2_pm_debug) {
-- omap2_pm_dump(0, 0, 0);
- getnstimeofday(&ts_preidle);
- }
-
-@@ -160,7 +161,6 @@ no_sleep:
- getnstimeofday(&ts_postidle);
- ts_idle = timespec_sub(ts_postidle, ts_preidle);
- tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-- omap2_pm_dump(0, 1, tmp);
- }
- omap2_gpio_resume_after_idle();
-
-@@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
- }
-
- if (omap2_pm_debug) {
-- omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
- getnstimeofday(&ts_preidle);
- }
-
-@@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
- getnstimeofday(&ts_postidle);
- ts_idle = timespec_sub(ts_postidle, ts_preidle);
- tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-- omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
- }
- }
-
---
-1.6.6.1
-
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0006-OMAP3-PM-debug-remove-register-dumping.patch b/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0006-OMAP3-PM-debug-remove-register-dumping.patch
--- a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0006-OMAP3-PM-debug-remove-register-dumping.patch
+++ /dev/null
@@ -1,313 +0,0 @@
-From 2cb229bc89ac3f0b369ffcfb375bb1469f77d98b Mon Sep 17 00:00:00 2001
-From: Kevin Hilman <khilman@ti.com>
-Date: Thu, 26 May 2011 15:34:39 -0700
-Subject: [PATCH 6/7] OMAP3: PM debug: remove register dumping
-
-Remove OMAP3-specific register dumping feature from PM debug layer.
-This is removed because:
-
-- it's ugly
-- it's OMAP3-specific, and will obviously not scale to OMAP4+
-- userspace /dev/mem-based tools (like omapconf) can do this much better
-
-Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-Acked-by: Jean Pihet <j-pihet@ti.com>
-Signed-off-by: Kevin Hilman <khilman@ti.com>
----
- arch/arm/mach-omap2/pm-debug.c | 221 ----------------------------------------
- arch/arm/mach-omap2/pm.h | 4 -
- 2 files changed, 0 insertions(+), 225 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
-index a8425d6..3d1cce2 100644
---- a/arch/arm/mach-omap2/pm-debug.c
-+++ b/arch/arm/mach-omap2/pm-debug.c
-@@ -63,10 +63,6 @@ void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
-
--static void pm_dbg_regset_store(u32 *ptr);
--
--static struct dentry *pm_dbg_dir;
--
- static int pm_dbg_init_done;
-
- static int pm_dbg_init(void);
-@@ -76,160 +72,6 @@ enum {
- DEBUG_FILE_TIMERS,
- };
-
--struct pm_module_def {
-- char name[8]; /* Name of the module */
-- short type; /* CM or PRM */
-- unsigned short offset;
-- int low; /* First register address on this module */
-- int high; /* Last register address on this module */
--};
--
--#define MOD_CM 0
--#define MOD_PRM 1
--
--static const struct pm_module_def *pm_dbg_reg_modules;
--static const struct pm_module_def omap3_pm_reg_modules[] = {
-- { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
-- { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
-- { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
-- { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
-- { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
-- { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
-- { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
-- { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
-- { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
-- { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
-- { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
-- { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
-- { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
--
-- { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
-- { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
-- { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
-- { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
-- { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
-- { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
-- { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
-- { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
-- { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
-- { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
-- { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
-- { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
-- { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
-- { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
-- { "", 0, 0, 0, 0 },
--};
--
--#define PM_DBG_MAX_REG_SETS 4
--
--static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
--
--static int pm_dbg_get_regset_size(void)
--{
-- static int regset_size;
--
-- if (regset_size == 0) {
-- int i = 0;
--
-- while (pm_dbg_reg_modules[i].name[0] != 0) {
-- regset_size += pm_dbg_reg_modules[i].high +
-- 4 - pm_dbg_reg_modules[i].low;
-- i++;
-- }
-- }
-- return regset_size;
--}
--
--static int pm_dbg_show_regs(struct seq_file *s, void *unused)
--{
-- int i, j;
-- unsigned long val;
-- int reg_set = (int)s->private;
-- u32 *ptr;
-- void *store = NULL;
-- int regs;
-- int linefeed;
--
-- if (reg_set == 0) {
-- store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
-- ptr = store;
-- pm_dbg_regset_store(ptr);
-- } else {
-- ptr = pm_dbg_reg_set[reg_set - 1];
-- }
--
-- i = 0;
--
-- while (pm_dbg_reg_modules[i].name[0] != 0) {
-- regs = 0;
-- linefeed = 0;
-- if (pm_dbg_reg_modules[i].type == MOD_CM)
-- seq_printf(s, "MOD: CM_%s (%08x)\n",
-- pm_dbg_reg_modules[i].name,
-- (u32)(OMAP3430_CM_BASE +
-- pm_dbg_reg_modules[i].offset));
-- else
-- seq_printf(s, "MOD: PRM_%s (%08x)\n",
-- pm_dbg_reg_modules[i].name,
-- (u32)(OMAP3430_PRM_BASE +
-- pm_dbg_reg_modules[i].offset));
--
-- for (j = pm_dbg_reg_modules[i].low;
-- j <= pm_dbg_reg_modules[i].high; j += 4) {
-- val = *(ptr++);
-- if (val != 0) {
-- regs++;
-- if (linefeed) {
-- seq_printf(s, "\n");
-- linefeed = 0;
-- }
-- seq_printf(s, " %02x => %08lx", j, val);
-- if (regs % 4 == 0)
-- linefeed = 1;
-- }
-- }
-- seq_printf(s, "\n");
-- i++;
-- }
--
-- if (store != NULL)
-- kfree(store);
--
-- return 0;
--}
--
--static void pm_dbg_regset_store(u32 *ptr)
--{
-- int i, j;
-- u32 val;
--
-- i = 0;
--
-- while (pm_dbg_reg_modules[i].name[0] != 0) {
-- for (j = pm_dbg_reg_modules[i].low;
-- j <= pm_dbg_reg_modules[i].high; j += 4) {
-- if (pm_dbg_reg_modules[i].type == MOD_CM)
-- val = omap2_cm_read_mod_reg(
-- pm_dbg_reg_modules[i].offset, j);
-- else
-- val = omap2_prm_read_mod_reg(
-- pm_dbg_reg_modules[i].offset, j);
-- *(ptr++) = val;
-- }
-- i++;
-- }
--}
--
--int pm_dbg_regset_save(int reg_set)
--{
-- if (pm_dbg_reg_set[reg_set-1] == NULL)
-- return -EINVAL;
--
-- pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
--
-- return 0;
--}
--
- static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
- "OFF",
- "RET",
-@@ -349,11 +191,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
- };
- }
-
--static int pm_dbg_reg_open(struct inode *inode, struct file *file)
--{
-- return single_open(file, pm_dbg_show_regs, inode->i_private);
--}
--
- static const struct file_operations debug_fops = {
- .open = pm_dbg_open,
- .read = seq_read,
-@@ -361,40 +198,6 @@ static const struct file_operations debug_fops = {
- .release = single_release,
- };
-
--static const struct file_operations debug_reg_fops = {
-- .open = pm_dbg_reg_open,
-- .read = seq_read,
-- .llseek = seq_lseek,
-- .release = single_release,
--};
--
--int pm_dbg_regset_init(int reg_set)
--{
-- char name[2];
--
-- if (!pm_dbg_init_done)
-- pm_dbg_init();
--
-- if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
-- pm_dbg_reg_set[reg_set-1] != NULL)
-- return -EINVAL;
--
-- pm_dbg_reg_set[reg_set-1] =
-- kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
--
-- if (pm_dbg_reg_set[reg_set-1] == NULL)
-- return -ENOMEM;
--
-- if (pm_dbg_dir != NULL) {
-- sprintf(name, "%d", reg_set);
--
-- (void) debugfs_create_file(name, S_IRUGO,
-- pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
-- }
--
-- return 0;
--}
--
- static int pwrdm_suspend_get(void *data, u64 *val)
- {
- int ret = -EINVAL;
-@@ -477,20 +280,11 @@ DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
-
- static int pm_dbg_init(void)
- {
-- int i;
- struct dentry *d;
-- char name[2];
-
- if (pm_dbg_init_done)
- return 0;
-
-- if (cpu_is_omap34xx())
-- pm_dbg_reg_modules = omap3_pm_reg_modules;
-- else {
-- printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
-- return -ENODEV;
-- }
--
- d = debugfs_create_dir("pm_debug", NULL);
- if (IS_ERR(d))
- return PTR_ERR(d);
-@@ -502,21 +296,6 @@ static int pm_dbg_init(void)
-
- pwrdm_for_each(pwrdms_setup, (void *)d);
-
-- pm_dbg_dir = debugfs_create_dir("registers", d);
-- if (IS_ERR(pm_dbg_dir))
-- return PTR_ERR(pm_dbg_dir);
--
-- (void) debugfs_create_file("current", S_IRUGO,
-- pm_dbg_dir, (void *)0, &debug_reg_fops);
--
-- for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
-- if (pm_dbg_reg_set[i] != NULL) {
-- sprintf(name, "%d", i+1);
-- (void) debugfs_create_file(name, S_IRUGO,
-- pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
--
-- }
--
- (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
- &enable_off_mode, &pm_dbg_option_fops);
- (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
-diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
-index acac275..ea58f5d 100644
---- a/arch/arm/mach-omap2/pm.h
-+++ b/arch/arm/mach-omap2/pm.h
-@@ -74,12 +74,8 @@ extern u32 enable_off_mode;
-
- #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
- extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
--extern int pm_dbg_regset_save(int reg_set);
--extern int pm_dbg_regset_init(int reg_set);
- #else
- #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
--#define pm_dbg_regset_save(reg_set) do {} while (0);
--#define pm_dbg_regset_init(reg_set) do {} while (0);
- #endif /* CONFIG_PM_DEBUG */
-
- extern void omap24xx_idle_loop_suspend(void);
---
-1.6.6.1
-
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0007-OMAP2-PM-fix-section-mismatch-in-pm_dbg_init.patch b/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0007-OMAP2-PM-fix-section-mismatch-in-pm_dbg_init.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 7472bb7b89bfdc6beef83bb6008219158e072975 Mon Sep 17 00:00:00 2001
-From: Sanjeev Premi <premi@ti.com>
-Date: Fri, 17 Jun 2011 02:01:00 +0530
-Subject: [PATCH 7/7] OMAP2+: PM: fix section mismatch in pm_dbg_init()
-
-Fix the section mismatch warning:
-
- WARNING: vmlinux.o(.text+0x21118): Section mismatch
- in reference from the function pm_dbg_init() to the
- function .init.text:pwrdms_setup()
- The function pm_dbg_init() references
- the function __init pwrdms_setup().
- This is often because pm_dbg_init lacks a __init
- annotation or the annotation of pwrdms_setup is wrong.
-
-Signed-off-by: Sanjeev Premi <premi@ti.com>
-Signed-off-by: Kevin Hilman <khilman@ti.com>
----
- arch/arm/mach-omap2/pm-debug.c | 2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
-index 3d1cce2..3feb475 100644
---- a/arch/arm/mach-omap2/pm-debug.c
-+++ b/arch/arm/mach-omap2/pm-debug.c
-@@ -278,7 +278,7 @@ static int option_set(void *data, u64 val)
-
- DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
-
--static int pm_dbg_init(void)
-+static int __init pm_dbg_init(void)
- {
- struct dentry *d;
-
---
-1.6.6.1
-
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0001-PM-OPP-introduce-function-to-free-cpufreq-table.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0001-PM-OPP-introduce-function-to-free-cpufreq-table.patch
index f92c4abcd01c6c802c7f245c41df5bde86c60bdf..2195c588c7c2fc3b9844bcea4f4c3bce05353bb1 100644 (file)
-From e029940bc6c0ff4ad3c8e2b4f31d0a3de78eff32 Mon Sep 17 00:00:00 2001
+From e234cd2e8844589e2836aa67b3adefa0fd332081 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Wed, 25 May 2011 00:43:26 -0700
Subject: [PATCH 01/19] PM: OPP: introduce function to free cpufreq table
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0002-OMAP-CPUfreq-ensure-driver-initializes-after-cpufreq.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0002-OMAP-CPUfreq-ensure-driver-initializes-after-cpufreq.patch
index 5201c81b3f1cf39fd2a2c023dc68923c880928b6..486cd5c308356c52858adc8f58599e77147c6662 100644 (file)
-From 895fc8961297666b46b4cd3f8c01010051d2164e Mon Sep 17 00:00:00 2001
+From c305bd58ba4bd21eae34991684b4f27311c8c12f Mon Sep 17 00:00:00 2001
From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Date: Wed, 11 Aug 2010 17:02:43 -0700
Subject: [PATCH 02/19] OMAP: CPUfreq: ensure driver initializes after cpufreq framework and governors
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0003-OMAP-CPUfreq-ensure-policy-is-fully-initialized.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0003-OMAP-CPUfreq-ensure-policy-is-fully-initialized.patch
index 5447646a2cf5701ac420ac4fcdb910aecb12630f..e011037d22e4d4348931a6ef77581419d93f9088 100644 (file)
-From 62bd1b0f18ee6c6bad1573c2f06e74b0abc418a3 Mon Sep 17 00:00:00 2001
+From 25d01f098bd134113876b8110b2433cd9a37dcf7 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Wed, 11 Aug 2010 17:05:38 -0700
Subject: [PATCH 03/19] OMAP: CPUfreq: ensure policy is fully initialized
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0004-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0004-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch
index c490a1de187d3e5e4eab24e4923b3978b39efbbf..455656e095e550e75d0556875d7872e248a60449 100644 (file)
-From afa9b062a33a9d9d2d9077cc519e1375b8338e39 Mon Sep 17 00:00:00 2001
+From f37fcaec1c8e778ea7c697b8e7d3e771460b2c71 Mon Sep 17 00:00:00 2001
From: Rajendra Nayak <rnayak@ti.com>
Date: Mon, 10 Nov 2008 17:00:25 +0530
Subject: [PATCH 04/19] OMAP3 PM: CPUFreq driver for OMAP3
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
-index e10ff2b..0a07e50 100644
+index 48ac568..8bad1c6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
-@@ -141,7 +141,9 @@ extern const struct clksel_rate gpt_sys_rates[];
+@@ -144,7 +144,9 @@ extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#else
-@@ -149,6 +151,16 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+@@ -152,6 +154,16 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
#define omap2_clk_exit_cpufreq_table 0
#endif
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0005-OMAP-PM-CPUFREQ-Fix-conditional-compilation.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0005-OMAP-PM-CPUFREQ-Fix-conditional-compilation.patch
index 1801c46ca93017919f81413a4f64d278e6305d8e..42ccd697fe65220dc626467212214ec48fd7afa6 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0005-OMAP-PM-CPUFREQ-Fix-conditional-compilation.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0005-OMAP-PM-CPUFREQ-Fix-conditional-compilation.patch
-From c93327d36f0dc4ea6693fcae54c561eb8bafdd1e Mon Sep 17 00:00:00 2001
+From b432446c907e4352babda2d380136ba42a5089d0 Mon Sep 17 00:00:00 2001
From: Silesh C V <silesh@ti.com>
Date: Wed, 29 Sep 2010 14:52:54 +0530
Subject: [PATCH 05/19] OMAP: PM: CPUFREQ: Fix conditional compilation
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0006-cpufreq-fixup-after-new-OPP-layer-merged.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0006-cpufreq-fixup-after-new-OPP-layer-merged.patch
index 9c035fab6925d53e940ef89ea30d86d14713f39e..634b6734cbc0db1fc0c15e4643e3896f26850fd5 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0006-cpufreq-fixup-after-new-OPP-layer-merged.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0006-cpufreq-fixup-after-new-OPP-layer-merged.patch
-From b8246b5d5edc98155628ba88510bc7e67baf7acf Mon Sep 17 00:00:00 2001
+From f04b9a76326121cb8e42e486a77a6bf098d87ecc Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Tue, 16 Nov 2010 11:48:41 -0800
Subject: [PATCH 06/19] cpufreq: fixup after new OPP layer merged
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0007-OMAP-cpufreq-Split-OMAP1-and-OMAP2PLUS-CPUfreq-drive.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0007-OMAP-cpufreq-Split-OMAP1-and-OMAP2PLUS-CPUfreq-drive.patch
index 3eafe76cda01a23b157085c479b89e7dc3b52330..69ac50a032d783500e222ef24111f1b0eacdfe8b 100644 (file)
-From 9f9061d3e98aa6db7d5c3feabd5a2d93eb3cb737 Mon Sep 17 00:00:00 2001
+From 0dce78bb4a6d7d65a7c5c34a7d0dd085dccae72f Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 14 Mar 2011 17:08:48 +0530
Subject: [PATCH 07/19] OMAP: cpufreq: Split OMAP1 and OMAP2PLUS CPUfreq drivers.
+module_init(omap_cpufreq_init);
+module_exit(omap_cpufreq_exit);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index b148077..5024064 100644
+index 8e79ca5..7927dd6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -56,6 +56,9 @@ obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0008-OMAP2PLUS-cpufreq-Add-SMP-support-to-cater-OMAP4430.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0008-OMAP2PLUS-cpufreq-Add-SMP-support-to-cater-OMAP4430.patch
index b47934f2510daf3689062e3b2016ab9bad176cc1..a4aad2ef12293c924c557e861e11e5289cdb4929 100644 (file)
-From f5dc16c8178d0c0bcad795f8ebc71934c4028472 Mon Sep 17 00:00:00 2001
+From 6f0a749e22140520fa67c46d7cb2c020b8678df4 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 14 Mar 2011 17:08:49 +0530
Subject: [PATCH 08/19] OMAP2PLUS: cpufreq: Add SMP support to cater OMAP4430
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0009-OMAP2PLUS-cpufreq-Fix-typo-when-attempting-to-set-mp.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0009-OMAP2PLUS-cpufreq-Fix-typo-when-attempting-to-set-mp.patch
index b7ea956da9df8c888f80c19a9354a782631fb7f8..bc106b2c7f09d7bb777604bcd67c322383c81202 100644 (file)
-From 07367b4c3afd8e881c4cf50ef35d081c4ac252b8 Mon Sep 17 00:00:00 2001
+From eb0279c52c74abcb0475b70115667a351bcae4e0 Mon Sep 17 00:00:00 2001
From: Jarkko Nikula <jhnikula@gmail.com>
Date: Thu, 14 Apr 2011 16:21:58 +0300
Subject: [PATCH 09/19] OMAP2PLUS: cpufreq: Fix typo when attempting to set mpu_clk for OMAP4
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0010-OMAP2-cpufreq-move-clk-name-decision-to-init.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0010-OMAP2-cpufreq-move-clk-name-decision-to-init.patch
index fe892e37abb7211f69f7f6d281294bd07d4e57c0..cc3f7c0192804872a122527cb1a99756b9efdd37 100644 (file)
-From 4d3e024c2f7f0334874bbb2a168b62e91cb2517a Mon Sep 17 00:00:00 2001
+From a81a661b40c6ca792f1cc8de46d529603b93215d Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Wed, 25 May 2011 16:38:46 -0700
Subject: [PATCH 10/19] OMAP2+: cpufreq: move clk name decision to init
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0011-OMAP2-cpufreq-deny-initialization-if-no-mpudev.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0011-OMAP2-cpufreq-deny-initialization-if-no-mpudev.patch
index 4138e3fe97ec69808ba93bd0ea08aa62c9c80af8..5b29e510bc9c141c2585d9fee7ea5e6fe0b63b86 100644 (file)
-From 85afa12ad2a6e7a23ddf4b25e78e0ce5b9f18a64 Mon Sep 17 00:00:00 2001
+From 7f50ad4eb8465fd74115f67bbf3c5a1bc884d902 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Wed, 25 May 2011 16:38:47 -0700
Subject: [PATCH 11/19] OMAP2+: cpufreq: deny initialization if no mpudev
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0012-OMAP2-cpufreq-dont-support-freq_table.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0012-OMAP2-cpufreq-dont-support-freq_table.patch
index b57031a05a604be9176a2d024d873d4255c2df3d..679d78b5bbe8dc3d8d728bac116b05c0cbafbe01 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0012-OMAP2-cpufreq-dont-support-freq_table.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0012-OMAP2-cpufreq-dont-support-freq_table.patch
-From 345f93655f425c87ba01e949dc038e04542d8cd4 Mon Sep 17 00:00:00 2001
+From 229d046050abc04e56ecdc6fd500e37359a70e8c Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 26 May 2011 19:39:17 -0700
Subject: [PATCH 12/19] OMAP2+: cpufreq: dont support !freq_table
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0013-OMAP2-cpufreq-only-supports-OPP-library.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0013-OMAP2-cpufreq-only-supports-OPP-library.patch
index 71c4fe64541927c66c6738d83db8e82f2a2bfee6..9702b47a64f111825d891784da0f2c93f7283c6a 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0013-OMAP2-cpufreq-only-supports-OPP-library.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0013-OMAP2-cpufreq-only-supports-OPP-library.patch
-From 1e5757cbc79685c6294a178d1bea76a52cffcae9 Mon Sep 17 00:00:00 2001
+From 515c4e841924e69dba0a0af5d5ed0ead23d768e6 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 26 May 2011 19:39:18 -0700
Subject: [PATCH 13/19] OMAP2+: cpufreq: only supports OPP library
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0014-OMAP2-cpufreq-put-clk-if-cpu_init-failed.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0014-OMAP2-cpufreq-put-clk-if-cpu_init-failed.patch
index fffbcc90656234a967c382f754fc5f110a7a19c8..120a7dd7692421c5926c3d04f209c00a45c5c090 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0014-OMAP2-cpufreq-put-clk-if-cpu_init-failed.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0014-OMAP2-cpufreq-put-clk-if-cpu_init-failed.patch
-From bec0338ead64cdd8515ae4c94462ffbfd6ae6418 Mon Sep 17 00:00:00 2001
+From a97cfd4b3ba13e6c165ac67e97476b9b3c3f0df7 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 26 May 2011 19:39:19 -0700
Subject: [PATCH 14/19] OMAP2+: cpufreq: put clk if cpu_init failed
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0015-OMAP2-cpufreq-fix-freq_table-leak.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0015-OMAP2-cpufreq-fix-freq_table-leak.patch
index 8257a17db1660a1b3a2492ca2a9dfa28efd81e7c..e331389c8cd8c180e2eed6fb5c3644a39297c57c 100644 (file)
-From 0054f5049a4e65a359eca6fa8c6668fb047c9270 Mon Sep 17 00:00:00 2001
+From 27481c729129c20a2550d8f99831146ca6260622 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 26 May 2011 19:39:20 -0700
Subject: [PATCH 15/19] OMAP2+: cpufreq: fix freq_table leak
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0016-OMAP2-CPUfreq-Remove-superfluous-check-in-target-for.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0016-OMAP2-CPUfreq-Remove-superfluous-check-in-target-for.patch
index 478b7691995148be0ffd2d47f293013cebdee862..5059cf340878908c23836544a18207073cf0b9e7 100644 (file)
-From 255f1830ab71e130bbdffd84e61fc7a8c3791120 Mon Sep 17 00:00:00 2001
+From b25da32f52df4e31a535e28397f73b37711b6cfa Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 3 Jun 2011 17:46:57 +0530
Subject: [PATCH 16/19] OMAP2+: CPUfreq: Remove superfluous check in target() for online CPU's.
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0017-OMAP2-cpufreq-notify-even-with-bad-boot-frequency.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0017-OMAP2-cpufreq-notify-even-with-bad-boot-frequency.patch
index 42ca787ae66d76d1f59499e61e3f99ce3577f950..ba0457c333f62fe54576ae240ffb40a55e1164b1 100644 (file)
-From 3bf92d672cb3ee7c1ec39f1f0fcf6e8dbde2ceb9 Mon Sep 17 00:00:00 2001
+From 600d2adf94d6df2fa5e4517b4dfa03c736c45055 Mon Sep 17 00:00:00 2001
From: Colin Cross <ccross@google.com>
Date: Mon, 6 Jun 2011 21:05:29 -0500
Subject: [PATCH 17/19] OMAP2+: cpufreq: notify even with bad boot frequency
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0018-OMAP2-cpufreq-Enable-all-CPUs-in-shared-policy-mask.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0018-OMAP2-cpufreq-Enable-all-CPUs-in-shared-policy-mask.patch
index 57cec0f1b596665179396cabe84d8306cfa31acb..294658446677f7c2f7c019d2b9189bed88cca340 100644 (file)
-From 6e092f78e67d722be6036131df6aa0b8b2fec879 Mon Sep 17 00:00:00 2001
+From 3b3f823cf6049824ad754dc92260212134f01e94 Mon Sep 17 00:00:00 2001
From: Todd Poynor <toddpoynor@google.com>
Date: Tue, 7 Jun 2011 13:57:52 -0700
Subject: [PATCH 18/19] OMAP2+: cpufreq: Enable all CPUs in shared policy mask
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0019-OMAP2-CPUfreq-update-lpj-with-reference-value-to-avo.patch b/recipes-kernel/linux/linux-3.0/pm-wip/cpufreq/0019-OMAP2-CPUfreq-update-lpj-with-reference-value-to-avo.patch
index b5f69d162e8aeacc31be73daf19596219cd83d9c..921170255db6a8d6ba6630831b7eccf71ade6820 100644 (file)
-From e8fa6ffc7822b7c7e81fafb112f3064f31c5c0e3 Mon Sep 17 00:00:00 2001
+From 27225a42d66fe1650949857d98d8f58c6cf7c26f Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 11 Jul 2011 23:10:04 +0530
Subject: [PATCH 19/19] OMAP2+: CPUfreq: update lpj with reference value to avoid progressive error.
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0001-cleanup-regulator-supply-definitions-in-mach-omap2.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0001-cleanup-regulator-supply-definitions-in-mach-omap2.patch
--- /dev/null
@@ -0,0 +1,1083 @@
+From cb5d2a594f46d4020101d562978cf12fcdbabf28 Mon Sep 17 00:00:00 2001
+From: Oleg Drokin <green@linuxhacker.ru>
+Date: Mon, 6 Jun 2011 18:57:07 +0000
+Subject: [PATCH 001/149] cleanup regulator supply definitions in mach-omap2
+
+to use REGULATOR_SUPPLY arrays.
+
+CC: Mark Brown <broonie@opensource.wolfsonmicro.com>
+CC: Mike Rapoport <mike@compulab.co.il>
+CC: Nishant Kamat <nskamat@ti.com>
+CC: Steve Sakoman <steve@sakoman.com>
+CC: Felipe Balbi <balbi@ti.com>
+CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
+CC: peter.barada@logicpd.com
+Signed-off-by: Oleg Drokin <green@linuxhacker.ru>
+Acked-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 13 ++----
+ arch/arm/mach-omap2/board-cm-t35.c | 34 +++++++-------
+ arch/arm/mach-omap2/board-devkit8000.c | 28 ++++++-----
+ arch/arm/mach-omap2/board-igep0020.c | 27 ++++++-----
+ arch/arm/mach-omap2/board-ldp.c | 8 ++--
+ arch/arm/mach-omap2/board-omap3beagle.c | 25 +++++-----
+ arch/arm/mach-omap2/board-omap3evm.c | 41 +++++++++--------
+ arch/arm/mach-omap2/board-omap3logic.c | 8 ++--
+ arch/arm/mach-omap2/board-omap3pandora.c | 63 ++++++++++++++-----------
+ arch/arm/mach-omap2/board-omap3stalker.c | 25 +++++-----
+ arch/arm/mach-omap2/board-omap3touchbook.c | 32 +++++++------
+ arch/arm/mach-omap2/board-omap4panda.c | 16 +++----
+ arch/arm/mach-omap2/board-overo.c | 26 ++++++-----
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 29 +++++++-----
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 42 +++++++++---------
+ 15 files changed, 218 insertions(+), 199 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 63de2d3..39a8062 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -333,16 +333,11 @@ static struct omap2_hsmmc_info mmc[] = {
+ };
+
+ static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
+- {
+- .supply = "vmmc",
+- .dev_name = "omap_hsmmc.1",
+- },
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
++
+ static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
+- {
+- .supply = "vmmc",
+- .dev_name = "omap_hsmmc.0",
+- },
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+@@ -399,7 +394,7 @@ static struct regulator_init_data sdp4430_vaux1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
++ .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
+ .consumer_supplies = sdp4430_vaux_supply,
+ };
+
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 77456de..e7bf32d 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -337,19 +337,21 @@ static void __init cm_t35_init_display(void)
+ }
+ }
+
+-static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply cm_t35_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply cm_t35_vdac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply cm_t35_vdac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+-static struct regulator_consumer_supply cm_t35_vdvi_supply =
+- REGULATOR_SUPPLY("vdvi", "omapdss");
++static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
++ REGULATOR_SUPPLY("vdvi", "omapdss"),
++};
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+ static struct regulator_init_data cm_t35_vmmc1 = {
+@@ -362,8 +364,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &cm_t35_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
++ .consumer_supplies = cm_t35_vmmc1_supply,
+ };
+
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+@@ -377,8 +379,8 @@ static struct regulator_init_data cm_t35_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &cm_t35_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
++ .consumer_supplies = cm_t35_vsim_supply,
+ };
+
+ /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+@@ -391,8 +393,8 @@ static struct regulator_init_data cm_t35_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &cm_t35_vdac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdac_supply),
++ .consumer_supplies = cm_t35_vdac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+@@ -406,8 +408,8 @@ static struct regulator_init_data cm_t35_vpll2 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &cm_t35_vdvi_supply,
++ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdvi_supply),
++ .consumer_supplies = cm_t35_vdvi_supply,
+ };
+
+ static struct twl4030_usb_data cm_t35_usb_data = {
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 34956ec..ead9c1d 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -130,13 +130,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
+ gpio_set_value_cansleep(dssdev->reset_gpio, 0);
+ }
+
+-static struct regulator_consumer_supply devkit8000_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+-
++static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
++};
+
+ /* ads7846 on SPI */
+-static struct regulator_consumer_supply devkit8000_vio_supply =
+- REGULATOR_SUPPLY("vcc", "spi2.0");
++static struct regulator_consumer_supply devkit8000_vio_supply[] = {
++ REGULATOR_SUPPLY("vcc", "spi2.0"),
++};
+
+ static struct panel_generic_dpi_data lcd_panel = {
+ .name = "generic",
+@@ -186,8 +187,9 @@ static struct omap_dss_board_info devkit8000_dss_data = {
+ .default_device = &devkit8000_lcd_device,
+ };
+
+-static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply devkit8000_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ static uint32_t board_keymap[] = {
+ KEY(0, 0, KEY_1),
+@@ -284,8 +286,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &devkit8000_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vmmc1_supply),
++ .consumer_supplies = devkit8000_vmmc1_supply,
+ };
+
+ /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+@@ -298,8 +300,8 @@ static struct regulator_init_data devkit8000_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &devkit8000_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vdda_dac_supply),
++ .consumer_supplies = devkit8000_vdda_dac_supply,
+ };
+
+ /* VPLL1 for digital video outputs */
+@@ -327,8 +329,8 @@ static struct regulator_init_data devkit8000_vio = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &devkit8000_vio_supply,
++ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supply),
++ .consumer_supplies = devkit8000_vio_supply,
+ };
+
+ static struct twl4030_usb_data devkit8000_usb_data = {
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 0c1bfca..84d2846 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
+ static inline void __init igep2_init_smsc911x(void) { }
+ #endif
+
+-static struct regulator_consumer_supply igep_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
++static struct regulator_consumer_supply igep_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
++};
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+ static struct regulator_init_data igep_vmmc1 = {
+@@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &igep_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
++ .consumer_supplies = igep_vmmc1_supply,
+ };
+
+-static struct regulator_consumer_supply igep_vio_supply =
+- REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
++static struct regulator_consumer_supply igep_vio_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
++};
+
+ static struct regulator_init_data igep_vio = {
+ .constraints = {
+@@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &igep_vio_supply,
++ .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
++ .consumer_supplies = igep_vio_supply,
+ };
+
+-static struct regulator_consumer_supply igep_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++static struct regulator_consumer_supply igep_vmmc2_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
++};
+
+ static struct regulator_init_data igep_vmmc2 = {
+ .constraints = {
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .always_on = 1,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &igep_vmmc2_supply,
++ .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
++ .consumer_supplies = igep_vmmc2_supply,
+ };
+
+ static struct fixed_voltage_config igep_vwlan = {
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index f7d6038..069bc9f 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -213,8 +213,8 @@ static struct twl4030_madc_platform_data ldp_madc_data = {
+ .irq_line = 1,
+ };
+
+-static struct regulator_consumer_supply ldp_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+@@ -228,8 +228,8 @@ static struct regulator_init_data ldp_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &ldp_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
++ .consumer_supplies = ldp_vmmc1_supply,
+ };
+
+ /* ads7846 on SPI */
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 7f21d24..4cf7c19 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -210,8 +210,9 @@ static struct omap_dss_board_info beagle_dss_data = {
+ .default_device = &beagle_dvi_device,
+ };
+
+-static struct regulator_consumer_supply beagle_vdac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply beagle_vdac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+@@ -239,12 +240,12 @@ static struct omap2_hsmmc_info mmc[] = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply beagle_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply beagle_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply beagle_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+ static struct gpio_led gpio_leds[];
+@@ -336,8 +337,8 @@ static struct regulator_init_data beagle_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &beagle_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
++ .consumer_supplies = beagle_vmmc1_supply,
+ };
+
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+@@ -351,8 +352,8 @@ static struct regulator_init_data beagle_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &beagle_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
++ .consumer_supplies = beagle_vsim_supply,
+ };
+
+ /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+@@ -365,8 +366,8 @@ static struct regulator_init_data beagle_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &beagle_vdac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(beagle_vdac_supply),
++ .consumer_supplies = beagle_vdac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index b4d4346..fc7a23a 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
+ .default_device = &omap3_evm_lcd_device,
+ };
+
+-static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply omap3evm_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+@@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3evm_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
++ .consumer_supplies = omap3evm_vmmc1_supply,
+ };
+
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+@@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3evm_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
++ .consumer_supplies = omap3evm_vsim_supply,
+ };
+
+ static struct omap2_hsmmc_info mmc[] = {
+@@ -449,8 +449,9 @@ static struct twl4030_codec_data omap3evm_codec_data = {
+ .audio = &omap3evm_audio_data,
+ };
+
+-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply omap3_evm_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ /* VDAC for DSS driving S-Video */
+ static struct regulator_init_data omap3_evm_vdac = {
+@@ -463,8 +464,8 @@ static struct regulator_init_data omap3_evm_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3_evm_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vdda_dac_supply),
++ .consumer_supplies = omap3_evm_vdda_dac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+@@ -488,8 +489,9 @@ static struct regulator_init_data omap3_evm_vpll2 = {
+ };
+
+ /* ads7846 on SPI */
+-static struct regulator_consumer_supply omap3evm_vio_supply =
+- REGULATOR_SUPPLY("vcc", "spi1.0");
++static struct regulator_consumer_supply omap3evm_vio_supply[] = {
++ REGULATOR_SUPPLY("vcc", "spi1.0"),
++};
+
+ /* VIO for ads7846 */
+ static struct regulator_init_data omap3evm_vio = {
+@@ -502,8 +504,8 @@ static struct regulator_init_data omap3evm_vio = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3evm_vio_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
++ .consumer_supplies = omap3evm_vio_supply,
+ };
+
+ #ifdef CONFIG_WL12XX_PLATFORM_DATA
+@@ -511,16 +513,17 @@ static struct regulator_init_data omap3evm_vio = {
+ #define OMAP3EVM_WLAN_PMENA_GPIO (150)
+ #define OMAP3EVM_WLAN_IRQ_GPIO (149)
+
+-static struct regulator_consumer_supply omap3evm_vmmc2_supply =
++static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++};
+
+ /* VMMC2 for driving the WL12xx module */
+ static struct regulator_init_data omap3evm_vmmc2 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3evm_vmmc2_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply);,
++ .consumer_supplies = omap3evm_vmmc2_supply,
+ };
+
+ static struct fixed_voltage_config omap3evm_vwlan = {
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index 60d9be4..ec18435 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -55,8 +55,8 @@
+ #define OMAP3_TORPEDO_MMC_GPIO_CD 127
+ #define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
+
+-static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+@@ -71,8 +71,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3logic_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
++ .consumer_supplies = omap3logic_vmmc1_supply,
+ };
+
+ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index 23f71d4..130a278 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -320,17 +320,21 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
+ .setup = omap3pandora_twl_gpio_setup,
+ };
+
+-static struct regulator_consumer_supply pandora_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
++static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
++};
+
+-static struct regulator_consumer_supply pandora_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
++};
+
+-static struct regulator_consumer_supply pandora_vmmc3_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
++static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
++};
+
+-static struct regulator_consumer_supply pandora_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply pandora_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
+ REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+@@ -338,11 +342,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+ };
+
+-static struct regulator_consumer_supply pandora_vcc_lcd_supply =
+- REGULATOR_SUPPLY("vcc", "display0");
++static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
++ REGULATOR_SUPPLY("vcc", "display0"),
++};
+
+-static struct regulator_consumer_supply pandora_usb_phy_supply =
+- REGULATOR_SUPPLY("hsusb0", "ehci-omap.0");
++static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
++ REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
++};
+
+ /* ads7846 on SPI and 2 nub controllers on I2C */
+ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
+@@ -351,8 +357,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
+ REGULATOR_SUPPLY("vcc", "3-0067"),
+ };
+
+-static struct regulator_consumer_supply pandora_adac_supply =
+- REGULATOR_SUPPLY("vcc", "soc-audio");
++static struct regulator_consumer_supply pandora_adac_supply[] = {
++ REGULATOR_SUPPLY("vcc", "soc-audio"),
++};
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+ static struct regulator_init_data pandora_vmmc1 = {
+@@ -365,8 +372,8 @@ static struct regulator_init_data pandora_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply),
++ .consumer_supplies = pandora_vmmc1_supply,
+ };
+
+ /* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
+@@ -380,8 +387,8 @@ static struct regulator_init_data pandora_vmmc2 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_vmmc2_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply),
++ .consumer_supplies = pandora_vmmc2_supply,
+ };
+
+ /* VDAC for DSS driving S-Video */
+@@ -395,8 +402,8 @@ static struct regulator_init_data pandora_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_vdda_dac_supply),
++ .consumer_supplies = pandora_vdda_dac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+@@ -425,8 +432,8 @@ static struct regulator_init_data pandora_vaux1 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_vcc_lcd_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply),
++ .consumer_supplies = pandora_vcc_lcd_supply,
+ };
+
+ /* VAUX2 for USB host PHY */
+@@ -440,8 +447,8 @@ static struct regulator_init_data pandora_vaux2 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_usb_phy_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply),
++ .consumer_supplies = pandora_usb_phy_supply,
+ };
+
+ /* VAUX4 for ads7846 and nubs */
+@@ -470,8 +477,8 @@ static struct regulator_init_data pandora_vsim = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_adac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply),
++ .consumer_supplies = pandora_adac_supply,
+ };
+
+ /* Fixed regulator internal to Wifi module */
+@@ -479,8 +486,8 @@ static struct regulator_init_data pandora_vmmc3 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &pandora_vmmc3_supply,
++ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
++ .consumer_supplies = pandora_vmmc3_supply,
+ };
+
+ static struct fixed_voltage_config pandora_vwlan = {
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 0c108a2..99be540 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -206,12 +206,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
+ .default_device = &omap3_stalker_dvi_device,
+ };
+
+-static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply omap3stalker_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+@@ -224,8 +224,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3stalker_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vmmc1_supply),
++ .consumer_supplies = omap3stalker_vmmc1_supply,
+ };
+
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+@@ -238,8 +238,8 @@ static struct regulator_init_data omap3stalker_vsim = {
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3stalker_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vsim_supply),
++ .consumer_supplies = omap3stalker_vsim_supply,
+ };
+
+ static struct omap2_hsmmc_info mmc[] = {
+@@ -403,8 +403,9 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
+ .audio = &omap3stalker_audio_data,
+ };
+
+-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ /* VDAC for DSS driving S-Video */
+ static struct regulator_init_data omap3_stalker_vdac = {
+@@ -417,8 +418,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap3_stalker_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vdda_dac_supply),
++ .consumer_supplies = omap3_stalker_vdda_dac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 5f649fa..ab5c37d 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -114,12 +114,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
+ .ctrl_name = "internal",
+ };
+
+-static struct regulator_consumer_supply touchbook_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply touchbook_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply touchbook_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+ static struct gpio_led gpio_leds[];
+@@ -167,14 +167,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
+ .setup = touchbook_twl_gpio_setup,
+ };
+
+-static struct regulator_consumer_supply touchbook_vdac_supply = {
++static struct regulator_consumer_supply touchbook_vdac_supply[] = {
++{
+ .supply = "vdac",
+ .dev = &omap3_touchbook_lcd_device.dev,
++},
+ };
+
+-static struct regulator_consumer_supply touchbook_vdvi_supply = {
++static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
++{
+ .supply = "vdvi",
+ .dev = &omap3_touchbook_lcd_device.dev,
++},
+ };
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+@@ -188,8 +192,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &touchbook_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(touchbook_vmmc1_supply),
++ .consumer_supplies = touchbook_vmmc1_supply,
+ };
+
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+@@ -203,8 +207,8 @@ static struct regulator_init_data touchbook_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &touchbook_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(touchbook_vsim_supply),
++ .consumer_supplies = touchbook_vsim_supply,
+ };
+
+ /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+@@ -217,8 +221,8 @@ static struct regulator_init_data touchbook_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &touchbook_vdac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(touchbook_vdac_supply),
++ .consumer_supplies = touchbook_vdac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+@@ -232,8 +236,8 @@ static struct regulator_init_data touchbook_vpll2 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &touchbook_vdvi_supply,
++ .num_consumer_supplies = ARRAY_SIZE(touchbook_vdvi_supply),
++ .consumer_supplies = touchbook_vdvi_supply,
+ };
+
+ static struct twl4030_usb_data touchbook_usb_data = {
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 0cfe200..6d2372b 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -183,23 +183,19 @@ static struct omap2_hsmmc_info mmc[] = {
+ };
+
+ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
+- {
+- .supply = "vmmc",
+- .dev_name = "omap_hsmmc.0",
+- },
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
+- .supply = "vmmc",
+- .dev_name = "omap_hsmmc.4",
++static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
+ };
+
+ static struct regulator_init_data panda_vmmc5 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &omap4_panda_vmmc5_supply,
++ .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
++ .consumer_supplies = omap4_panda_vmmc5_supply,
+ };
+
+ static struct fixed_voltage_config panda_vwlan = {
+@@ -312,7 +308,7 @@ static struct regulator_init_data omap4_panda_vmmc = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
++ .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc_supply),
+ .consumer_supplies = omap4_panda_vmmc_supply,
+ };
+
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 175e1ab..30c7556 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -74,15 +74,16 @@
+ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+ /* fixed regulator for ads7846 */
+-static struct regulator_consumer_supply ads7846_supply =
+- REGULATOR_SUPPLY("vcc", "spi1.0");
++static struct regulator_consumer_supply ads7846_supply[] = {
++ REGULATOR_SUPPLY("vcc", "spi1.0"),
++};
+
+ static struct regulator_init_data vads7846_regulator = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &ads7846_supply,
++ .num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
++ .consumer_supplies = ads7846_supply,
+ };
+
+ static struct fixed_voltage_config vads7846 = {
+@@ -264,8 +265,9 @@ static struct omap_dss_board_info overo_dss_data = {
+ .default_device = &overo_dvi_device,
+ };
+
+-static struct regulator_consumer_supply overo_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply overo_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+@@ -319,8 +321,8 @@ static struct omap2_hsmmc_info mmc[] = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply overo_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply overo_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+@@ -447,8 +449,8 @@ static struct regulator_init_data overo_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &overo_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
++ .consumer_supplies = overo_vmmc1_supply,
+ };
+
+ /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+@@ -461,8 +463,8 @@ static struct regulator_init_data overo_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &overo_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(overo_vdda_dac_supply),
++ .consumer_supplies = overo_vdda_dac_supply,
+ };
+
+ /* VPLL2 for digital video outputs */
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index 88bd6f7..7810b1e 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -358,14 +358,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply rx51_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
++static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
++};
+
+-static struct regulator_consumer_supply rx51_vaux3_supply =
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++static struct regulator_consumer_supply rx51_vaux3_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
++};
+
+-static struct regulator_consumer_supply rx51_vsim_supply =
+- REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
++static struct regulator_consumer_supply rx51_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
++};
+
+ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
+ /* tlv320aic3x analog supplies */
+@@ -452,8 +455,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &rx51_vaux3_supply,
++ .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
++ .consumer_supplies = rx51_vaux3_supply,
+ };
+
+ static struct regulator_init_data rx51_vaux4 = {
+@@ -479,8 +482,8 @@ static struct regulator_init_data rx51_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &rx51_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
++ .consumer_supplies = rx51_vmmc1_supply,
+ };
+
+ static struct regulator_init_data rx51_vmmc2 = {
+@@ -511,8 +514,8 @@ static struct regulator_init_data rx51_vsim = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &rx51_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
++ .consumer_supplies = rx51_vsim_supply,
+ };
+
+ static struct regulator_init_data rx51_vdac = {
+@@ -526,7 +529,7 @@ static struct regulator_init_data rx51_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
++ .num_consumer_supplies = ARRAY_SIZE(rx51_vdac_supply),
+ .consumer_supplies = rx51_vdac_supply,
+ };
+
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index 118c6f5..cb012e1 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
+ .rep = 1,
+ };
+
+-static struct regulator_consumer_supply zoom_vmmc1_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply zoom_vsim_supply = {
+- .supply = "vmmc_aux",
++static struct regulator_consumer_supply zoom_vsim_supply[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply zoom_vmmc2_supply = {
+- .supply = "vmmc",
++static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+-static struct regulator_consumer_supply zoom_vmmc3_supply = {
+- .supply = "vmmc",
+- .dev_name = "omap_hsmmc.2",
++static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
+ };
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+@@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &zoom_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
++ .consumer_supplies = zoom_vmmc1_supply,
+ };
+
+ /* VMMC2 for MMC2 card */
+@@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &zoom_vmmc2_supply,
++ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
++ .consumer_supplies = zoom_vmmc2_supply,
+ };
+
+ /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
+@@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &zoom_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
++ .consumer_supplies = zoom_vsim_supply,
+ };
+
+ static struct regulator_init_data zoom_vmmc3 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &zoom_vmmc3_supply,
++ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
++ .consumer_supplies = zoom_vmmc3_supply,
+ };
+
+ static struct fixed_voltage_config zoom_vwlan = {
+@@ -232,8 +231,9 @@ static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+ };
+
+-static struct regulator_consumer_supply zoom_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
++static struct regulator_consumer_supply zoom_vdda_dac_supply[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
+
+ static struct regulator_init_data zoom_vpll2 = {
+ .constraints = {
+@@ -257,8 +257,8 @@ static struct regulator_init_data zoom_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &zoom_vdda_dac_supply,
++ .num_consumer_supplies = ARRAY_SIZE(zoom_vdda_dac_supply),
++ .consumer_supplies = zoom_vdda_dac_supply,
+ };
+
+ static int zoom_twl_gpio_setup(struct device *dev,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0002-Remove-old-style-supply.dev-assignments-common-in-hs.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0002-Remove-old-style-supply.dev-assignments-common-in-hs.patch
--- /dev/null
@@ -0,0 +1,160 @@
+From e2f6d2c10498469246ca0f4dbdc1909f6b919262 Mon Sep 17 00:00:00 2001
+From: Oleg Drokin <green@linuxhacker.ru>
+Date: Mon, 6 Jun 2011 18:57:08 +0000
+Subject: [PATCH 002/149] Remove old-style supply.dev assignments common in hsmmc init
+
+CC: Mark Brown <broonie@opensource.wolfsonmicro.com>
+CC: Mike Rapoport <mike@compulab.co.il>
+CC: Nishant Kamat <nskamat@ti.com>
+CC: Steve Sakoman <steve@sakoman.com>
+CC: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Oleg Drokin <green@linuxhacker.ru>
+Acked-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-cm-t35.c | 4 ----
+ arch/arm/mach-omap2/board-ldp.c | 2 --
+ arch/arm/mach-omap2/board-omap3beagle.c | 4 ----
+ arch/arm/mach-omap2/board-omap3evm.c | 4 ----
+ arch/arm/mach-omap2/board-omap3logic.c | 2 --
+ arch/arm/mach-omap2/board-omap3stalker.c | 4 ----
+ arch/arm/mach-omap2/board-omap3touchbook.c | 4 ----
+ arch/arm/mach-omap2/board-overo.c | 2 --
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 7 -------
+ 9 files changed, 0 insertions(+), 33 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index e7bf32d..ceb581e 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -483,10 +483,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters */
+- cm_t35_vmmc1_supply.dev = mmc[0].dev;
+- cm_t35_vsim_supply.dev = mmc[0].dev;
+-
+ return 0;
+ }
+
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index 069bc9f..2d7e0ae 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -341,8 +341,6 @@ static void __init omap_ldp_init(void)
+ ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+
+ omap2_hsmmc_init(mmc);
+- /* link regulators to MMC adapters */
+- ldp_vmmc1_supply.dev = mmc[0].dev;
+ }
+
+ MACHINE_START(OMAP_LDP, "OMAP LDP board")
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 4cf7c19..8ef0e19 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -268,10 +268,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters */
+- beagle_vmmc1_supply.dev = mmc[0].dev;
+- beagle_vsim_supply.dev = mmc[0].dev;
+-
+ /*
+ * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
+ * high / others active low)
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index fc7a23a..e2202dd 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters */
+- omap3evm_vmmc1_supply.dev = mmc[0].dev;
+- omap3evm_vsim_supply.dev = mmc[0].dev;
+-
+ /*
+ * Most GPIOs are for USB OTG. Some are mostly sent to
+ * the P2 connector; notably LEDA for the LCD backlight.
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index ec18435..eaefb59 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -130,8 +130,6 @@ static void __init board_mmc_init(void)
+ }
+
+ omap2_hsmmc_init(board_mmc_info);
+- /* link regulators to MMC adapters */
+- omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
+ }
+
+ static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 99be540..63d12a3 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -321,10 +321,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters */
+- omap3stalker_vmmc1_supply.dev = mmc[0].dev;
+- omap3stalker_vsim_supply.dev = mmc[0].dev;
+-
+ /*
+ * Most GPIOs are for USB OTG. Some are mostly sent to
+ * the P2 connector; notably LEDA for the LCD backlight.
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index ab5c37d..c80e2c3 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -137,10 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters */
+- touchbook_vmmc1_supply.dev = mmc[0].dev;
+- touchbook_vsim_supply.dev = mmc[0].dev;
+-
+ /* REVISIT: need ehci-omap hooks for external VBUS
+ * power switch and overcurrent detect
+ */
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 30c7556..031a9a6 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -417,8 +417,6 @@ static int overo_twl_gpio_setup(struct device *dev,
+ {
+ omap2_hsmmc_init(mmc);
+
+- overo_vmmc1_supply.dev = mmc[0].dev;
+-
+ #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+ /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+ gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index cb012e1..8495f82 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -270,13 +270,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters ... we "know" the
+- * regulators will be set up only *after* we return.
+- */
+- zoom_vmmc1_supply.dev = mmc[0].dev;
+- zoom_vsim_supply.dev = mmc[0].dev;
+- zoom_vmmc2_supply.dev = mmc[1].dev;
+-
+ ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
+ "lcd enable");
+ if (ret)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0003-omap-Use-separate-init_irq-functions-to-avoid-cpu_is.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0003-omap-Use-separate-init_irq-functions-to-avoid-cpu_is.patch
--- /dev/null
@@ -0,0 +1,802 @@
+From 15c991d632814077f7dbc6ec0d6ca19433a95986 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 17 May 2011 03:51:26 -0700
+Subject: [PATCH 003/149] omap: Use separate init_irq functions to avoid cpu_is_omap tests early
+
+This allows us to remove cpu_is_omap calls from init_irq functions.
+There should not be any need for cpu_is_omap calls as at this point.
+During the timer init we only care about SoC generation, and not about
+subrevisions.
+
+The main reason for the patch is that we want to initialize only
+minimal omap specific code from the init_early call.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap1/board-ams-delta.c | 2 +-
+ arch/arm/mach-omap1/board-fsample.c | 2 +-
+ arch/arm/mach-omap1/board-generic.c | 2 +-
+ arch/arm/mach-omap1/board-h2.c | 2 +-
+ arch/arm/mach-omap1/board-h3.c | 2 +-
+ arch/arm/mach-omap1/board-htcherald.c | 2 +-
+ arch/arm/mach-omap1/board-innovator.c | 2 +-
+ arch/arm/mach-omap1/board-nokia770.c | 2 +-
+ arch/arm/mach-omap1/board-osk.c | 2 +-
+ arch/arm/mach-omap1/board-palmte.c | 2 +-
+ arch/arm/mach-omap1/board-palmtt.c | 2 +-
+ arch/arm/mach-omap1/board-palmz71.c | 2 +-
+ arch/arm/mach-omap1/board-perseus2.c | 2 +-
+ arch/arm/mach-omap1/board-sx1.c | 2 +-
+ arch/arm/mach-omap1/board-voiceblue.c | 2 +-
+ arch/arm/mach-omap1/irq.c | 2 +-
+ arch/arm/mach-omap2/board-2430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3630sdp.c | 2 +-
+ arch/arm/mach-omap2/board-am3517crane.c | 2 +-
+ arch/arm/mach-omap2/board-am3517evm.c | 2 +-
+ arch/arm/mach-omap2/board-apollon.c | 2 +-
+ arch/arm/mach-omap2/board-cm-t35.c | 2 +-
+ arch/arm/mach-omap2/board-cm-t3517.c | 2 +-
+ arch/arm/mach-omap2/board-devkit8000.c | 2 +-
+ arch/arm/mach-omap2/board-generic.c | 2 +-
+ arch/arm/mach-omap2/board-h4.c | 2 +-
+ arch/arm/mach-omap2/board-igep0020.c | 4 +-
+ arch/arm/mach-omap2/board-ldp.c | 2 +-
+ arch/arm/mach-omap2/board-n8x0.c | 6 ++--
+ arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
+ arch/arm/mach-omap2/board-omap3evm.c | 2 +-
+ arch/arm/mach-omap2/board-omap3logic.c | 4 +-
+ arch/arm/mach-omap2/board-omap3pandora.c | 2 +-
+ arch/arm/mach-omap2/board-omap3stalker.c | 2 +-
+ arch/arm/mach-omap2/board-omap3touchbook.c | 2 +-
+ arch/arm/mach-omap2/board-overo.c | 2 +-
+ arch/arm/mach-omap2/board-rm680.c | 2 +-
+ arch/arm/mach-omap2/board-rx51.c | 2 +-
+ arch/arm/mach-omap2/board-ti8168evm.c | 7 +-----
+ arch/arm/mach-omap2/board-zoom.c | 4 +-
+ arch/arm/mach-omap2/io.c | 17 +--------------
+ arch/arm/mach-omap2/irq.c | 32 ++++++++++++++++++---------
+ arch/arm/mach-omap2/omap4-common.c | 10 ++++----
+ arch/arm/plat-omap/include/plat/irqs.h | 6 ++++-
+ 45 files changed, 78 insertions(+), 84 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
+index f49ce85..e3caef8 100644
+--- a/arch/arm/mach-omap1/board-ams-delta.c
++++ b/arch/arm/mach-omap1/board-ams-delta.c
+@@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
+ static void __init ams_delta_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static struct map_desc ams_delta_io_desc[] __initdata = {
+diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
+index 87f173d..eaff305 100644
+--- a/arch/arm/mach-omap1/board-fsample.c
++++ b/arch/arm/mach-omap1/board-fsample.c
+@@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
+ static void __init omap_fsample_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ /* Only FPGA needs to be mapped here. All others are done with ioremap */
+diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
+index 23f4ab9..3fd6b40 100644
+--- a/arch/arm/mach-omap1/board-generic.c
++++ b/arch/arm/mach-omap1/board-generic.c
+@@ -31,7 +31,7 @@
+ static void __init omap_generic_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ /* assume no Mini-AB port */
+diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
+index ba3bd09..8147b04 100644
+--- a/arch/arm/mach-omap1/board-h2.c
++++ b/arch/arm/mach-omap1/board-h2.c
+@@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
+ static void __init h2_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static struct omap_usb_config h2_usb_config __initdata = {
+diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
+index ac48677..1b448f6 100644
+--- a/arch/arm/mach-omap1/board-h3.c
++++ b/arch/arm/mach-omap1/board-h3.c
+@@ -439,7 +439,7 @@ static void __init h3_init(void)
+ static void __init h3_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static void __init h3_map_io(void)
+diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
+index ba05a51..1bd4d8e 100644
+--- a/arch/arm/mach-omap1/board-htcherald.c
++++ b/arch/arm/mach-omap1/board-htcherald.c
+@@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
+ {
+ printk(KERN_INFO "htcherald_init_irq.\n");
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ MACHINE_START(HERALD, "HTC Herald")
+diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
+index 2d9b8cb..5926b0c 100644
+--- a/arch/arm/mach-omap1/board-innovator.c
++++ b/arch/arm/mach-omap1/board-innovator.c
+@@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
+ static void __init innovator_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ #ifdef CONFIG_ARCH_OMAP15XX
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index cfd0849..e3cf21d 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
+ omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
+
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static const unsigned int nokia770_keymap[] = {
+diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
+index e68dfde..1e7823d 100644
+--- a/arch/arm/mach-omap1/board-osk.c
++++ b/arch/arm/mach-omap1/board-osk.c
+@@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
+ static void __init osk_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static struct omap_usb_config osk_usb_config __initdata = {
+diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
+index c9d38f4..8b6a881 100644
+--- a/arch/arm/mach-omap1/board-palmte.c
++++ b/arch/arm/mach-omap1/board-palmte.c
+@@ -62,7 +62,7 @@
+ static void __init omap_palmte_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static const unsigned int palmte_keymap[] = {
+diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
+index f04f2d3..f2de43d 100644
+--- a/arch/arm/mach-omap1/board-palmtt.c
++++ b/arch/arm/mach-omap1/board-palmtt.c
+@@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
+ static void __init omap_palmtt_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static struct omap_usb_config palmtt_usb_config __initdata = {
+diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
+index 45f01d2..6665d2d 100644
+--- a/arch/arm/mach-omap1/board-palmz71.c
++++ b/arch/arm/mach-omap1/board-palmz71.c
+@@ -61,7 +61,7 @@ static void __init
+ omap_palmz71_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static const unsigned int palmz71_keymap[] = {
+diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
+index 3c8ee84..7f019e5 100644
+--- a/arch/arm/mach-omap1/board-perseus2.c
++++ b/arch/arm/mach-omap1/board-perseus2.c
+@@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
+ static void __init omap_perseus2_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+ /* Only FPGA needs to be mapped here. All others are done with ioremap */
+ static struct map_desc omap_perseus2_io_desc[] __initdata = {
+diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
+index 0ad781d..24f0f7b 100644
+--- a/arch/arm/mach-omap1/board-sx1.c
++++ b/arch/arm/mach-omap1/board-sx1.c
+@@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
+ static void __init omap_sx1_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+ /*----------------------------------------*/
+
+diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
+index 65d2420..98826e2 100644
+--- a/arch/arm/mach-omap1/board-voiceblue.c
++++ b/arch/arm/mach-omap1/board-voiceblue.c
+@@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
+ static void __init voiceblue_init_irq(void)
+ {
+ omap1_init_common_hw();
+- omap_init_irq();
++ omap1_init_irq();
+ }
+
+ static void __init voiceblue_map_io(void)
+diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
+index 5d3da7a..e2b9c90 100644
+--- a/arch/arm/mach-omap1/irq.c
++++ b/arch/arm/mach-omap1/irq.c
+@@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
+ .irq_set_wake = omap_wake_irq,
+ };
+
+-void __init omap_init_irq(void)
++void __init omap1_init_irq(void)
+ {
+ int i, j;
+
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index 5de6eac..45cabc5 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
+ .reserve = omap_reserve,
+ .map_io = omap_2430sdp_map_io,
+ .init_early = omap_2430sdp_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = omap_2430sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 5dac974..85b207f 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -804,7 +804,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap_3430sdp_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap_3430sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
+index a5933cc..2ec2d76 100644
+--- a/arch/arm/mach-omap2/board-3630sdp.c
++++ b/arch/arm/mach-omap2/board-3630sdp.c
+@@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap_sdp_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap_sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
+index 5e438a7..0bed0a4 100644
+--- a/arch/arm/mach-omap2/board-am3517crane.c
++++ b/arch/arm/mach-omap2/board-am3517crane.c
+@@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = am3517_crane_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = am3517_crane_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index 63af417..0db0fb8 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = am3517_evm_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = am3517_evm_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
+index b124bdf..93576c8 100644
+--- a/arch/arm/mach-omap2/board-apollon.c
++++ b/arch/arm/mach-omap2/board-apollon.c
+@@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
+ .reserve = omap_reserve,
+ .map_io = omap_apollon_map_io,
+ .init_early = omap_apollon_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = omap_apollon_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index ceb581e..43b1de5 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -644,7 +644,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = cm_t35_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = cm_t35_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index c3a9fd3..8f15222 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -304,7 +304,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = cm_t3517_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = cm_t3517_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index ead9c1d..73f3a22 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -440,7 +440,7 @@ static void __init devkit8000_init_early(void)
+
+ static void __init devkit8000_init_irq(void)
+ {
+- omap_init_irq();
++ omap3_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+ #endif
+diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
+index 73e3c31..ccd503a 100644
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+ .reserve = omap_reserve,
+ .map_io = omap_generic_map_io,
+ .init_early = omap_generic_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = omap_generic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
+index bac7933..2e16d6c 100644
+--- a/arch/arm/mach-omap2/board-h4.c
++++ b/arch/arm/mach-omap2/board-h4.c
+@@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
+
+ static void __init omap_h4_init_irq(void)
+ {
+- omap_init_irq();
++ omap2_init_irq();
+ }
+
+ static struct at24_platform_data m24c01 = {
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 84d2846..f22a76a 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -706,7 +706,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = igep_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = igep_init,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -716,7 +716,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = igep_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = igep_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index 2d7e0ae..9671843 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -348,7 +348,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap_ldp_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap_ldp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
+index 8d74318..9c791a2 100644
+--- a/arch/arm/mach-omap2/board-n8x0.c
++++ b/arch/arm/mach-omap2/board-n8x0.c
+@@ -699,7 +699,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
+ .reserve = omap_reserve,
+ .map_io = n8x0_map_io,
+ .init_early = n8x0_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -709,7 +709,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
+ .reserve = omap_reserve,
+ .map_io = n8x0_map_io,
+ .init_early = n8x0_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
+ .reserve = omap_reserve,
+ .map_io = n8x0_map_io,
+ .init_early = n8x0_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 8ef0e19..eaead5e 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -483,7 +483,7 @@ static void __init omap3_beagle_init_early(void)
+
+ static void __init omap3_beagle_init_irq(void)
+ {
+- omap_init_irq();
++ omap3_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+ #endif
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index e2202dd..d39f53f 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -739,7 +739,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3_evm_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap3_evm_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index eaefb59..b63f1c2 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -213,7 +213,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+ .init_early = omap3logic_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap3logic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -222,7 +222,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+ .init_early = omap3logic_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap3logic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index 130a278..1d90b90 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -650,7 +650,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3pandora_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap3pandora_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 63d12a3..dfa1401 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -491,7 +491,7 @@ static void __init omap3_stalker_init_early(void)
+
+ static void __init omap3_stalker_init_irq(void)
+ {
+- omap_init_irq();
++ omap3_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+ #endif
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index c80e2c3..ae97910 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -371,7 +371,7 @@ static void __init omap3_touchbook_init_early(void)
+
+ static void __init omap3_touchbook_init_irq(void)
+ {
+- omap_init_irq();
++ omap3_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+ #endif
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 031a9a6..e3928f2 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -615,7 +615,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = overo_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = overo_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
+index 42d10b1..9c3d115 100644
+--- a/arch/arm/mach-omap2/board-rm680.c
++++ b/arch/arm/mach-omap2/board-rm680.c
+@@ -163,7 +163,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+ .reserve = omap_reserve,
+ .map_io = rm680_map_io,
+ .init_early = rm680_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = rm680_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
+index fec4cac..ee35e4e 100644
+--- a/arch/arm/mach-omap2/board-rx51.c
++++ b/arch/arm/mach-omap2/board-rx51.c
+@@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
+ .reserve = rx51_reserve,
+ .map_io = rx51_map_io,
+ .init_early = rx51_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = rx51_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
+index 09fa7bf..713c20f 100644
+--- a/arch/arm/mach-omap2/board-ti8168evm.c
++++ b/arch/arm/mach-omap2/board-ti8168evm.c
+@@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
+ omap2_init_common_devices(NULL, NULL);
+ }
+
+-static void __init ti8168_evm_init_irq(void)
+-{
+- omap_init_irq();
+-}
+-
+ static void __init ti8168_evm_init(void)
+ {
+ omap_serial_init();
+@@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
+ .boot_params = 0x80000100,
+ .map_io = ti8168_evm_map_io,
+ .init_early = ti8168_init_early,
+- .init_irq = ti8168_evm_init_irq,
++ .init_irq = ti816x_init_irq,
+ .timer = &omap_timer,
+ .init_machine = ti8168_evm_init,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
+index 4b133d7..97a3f0b 100644
+--- a/arch/arm/mach-omap2/board-zoom.c
++++ b/arch/arm/mach-omap2/board-zoom.c
+@@ -137,7 +137,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap_zoom_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap_zoom_init,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap_zoom_init_early,
+- .init_irq = omap_init_irq,
++ .init_irq = omap3_init_irq,
+ .init_machine = omap_zoom_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 441e79d..2ce1ce6 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
+ return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
+ }
+
++/* See irq.c, omap4-common.c and entry-macro.S */
+ void __iomem *omap_irq_base;
+
+-/*
+- * Initialize asm_irq_base for entry-macro.S
+- */
+-static inline void omap_irq_base_init(void)
+-{
+- if (cpu_is_omap24xx())
+- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+- else if (cpu_is_omap34xx())
+- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+- else if (cpu_is_omap44xx())
+- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+- else
+- pr_err("Could not initialize omap_irq_base\n");
+-}
+-
+ void __init omap2_init_common_infrastructure(void)
+ {
+ u8 postsetup_state;
+@@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+ _omap2_init_reprogram_sdrc();
+ }
+
+- omap_irq_base_init();
+ }
+
+ /*
+diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
+index 3af2b7a..3a12f75 100644
+--- a/arch/arm/mach-omap2/irq.c
++++ b/arch/arm/mach-omap2/irq.c
+@@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+ }
+
+-void __init omap_init_irq(void)
++static void __init omap_init_irq(u32 base, int nr_irqs)
+ {
+ unsigned long nr_of_irqs = 0;
+ unsigned int nr_banks = 0;
+ int i, j;
+
++ omap_irq_base = ioremap(base, SZ_4K);
++ if (WARN_ON(!omap_irq_base))
++ return;
++
+ for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+- unsigned long base = 0;
+ struct omap_irq_bank *bank = irq_banks + i;
+
+- if (cpu_is_omap24xx())
+- base = OMAP24XX_IC_BASE;
+- else if (cpu_is_omap34xx())
+- base = OMAP34XX_IC_BASE;
+-
+- BUG_ON(!base);
+-
+- if (cpu_is_ti816x())
+- bank->nr_irqs = 128;
++ bank->nr_irqs = nr_irqs;
+
+ /* Static mapping, never released */
+ bank->base_reg = ioremap(base, SZ_4K);
+@@ -181,6 +176,21 @@ void __init omap_init_irq(void)
+ nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+ }
+
++void __init omap2_init_irq(void)
++{
++ omap_init_irq(OMAP24XX_IC_BASE, 96);
++}
++
++void __init omap3_init_irq(void)
++{
++ omap_init_irq(OMAP34XX_IC_BASE, 96);
++}
++
++void __init ti816x_init_irq(void)
++{
++ omap_init_irq(OMAP34XX_IC_BASE, 128);
++}
++
+ #ifdef CONFIG_ARCH_OMAP3
+ static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
+
+diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
+index 9ef8c29..35ac3e5 100644
+--- a/arch/arm/mach-omap2/omap4-common.c
++++ b/arch/arm/mach-omap2/omap4-common.c
+@@ -19,6 +19,8 @@
+ #include <asm/hardware/gic.h>
+ #include <asm/hardware/cache-l2x0.h>
+
++#include <plat/irqs.h>
++
+ #include <mach/hardware.h>
+ #include <mach/omap4-common.h>
+
+@@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
+
+ void __init gic_init_irq(void)
+ {
+- void __iomem *gic_cpu_base;
+-
+ /* Static mapping, never released */
+ gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
+ BUG_ON(!gic_dist_base_addr);
+
+ /* Static mapping, never released */
+- gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+- BUG_ON(!gic_cpu_base);
++ omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
++ BUG_ON(!omap_irq_base);
+
+- gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
++ gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
+ }
+
+ #ifdef CONFIG_CACHE_L2X0
+diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
+index 5a25098..c884320 100644
+--- a/arch/arm/plat-omap/include/plat/irqs.h
++++ b/arch/arm/plat-omap/include/plat/irqs.h
+@@ -428,7 +428,11 @@
+ #define INTCPS_NR_IRQS 96
+
+ #ifndef __ASSEMBLY__
+-extern void omap_init_irq(void);
++extern void __iomem *omap_irq_base;
++void omap1_init_irq(void);
++void omap2_init_irq(void);
++void omap3_init_irq(void);
++void ti816x_init_irq(void);
+ extern int omap_irq_pending(void);
+ void omap_intc_save_context(void);
+ void omap_intc_restore_context(void);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0004-omap-Set-separate-timer-init-functions-to-avoid-cpu_.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0004-omap-Set-separate-timer-init-functions-to-avoid-cpu_.patch
--- /dev/null
@@ -0,0 +1,689 @@
+From 9eb6982ba830b50a9d3759609633341aff91a6ec Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:48 -0700
+Subject: [PATCH 004/149] omap: Set separate timer init functions to avoid cpu_is_omap tests
+
+This is needed for the following patches so we can initialize the
+rest of the hardware timers later on.
+
+As with the init_irq calls, there's no need to do cpu_is_omap calls
+during the timer init as we only care about the major omap generation.
+This means that we can initialize the sys_timer with the .timer
+entries alone.
+
+Note that for now we just set stubs for the various sys_timer entries
+that will get populated in a later patch. The following patches will
+also remove the omap_dm_timer_init calls and change the init for the
+rest of the hardware timers to happen with an arch_initcall.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap1/board-ams-delta.c | 2 +-
+ arch/arm/mach-omap1/board-fsample.c | 2 +-
+ arch/arm/mach-omap1/board-generic.c | 2 +-
+ arch/arm/mach-omap1/board-h2.c | 2 +-
+ arch/arm/mach-omap1/board-h3.c | 2 +-
+ arch/arm/mach-omap1/board-htcherald.c | 2 +-
+ arch/arm/mach-omap1/board-innovator.c | 2 +-
+ arch/arm/mach-omap1/board-nokia770.c | 2 +-
+ arch/arm/mach-omap1/board-osk.c | 2 +-
+ arch/arm/mach-omap1/board-palmte.c | 2 +-
+ arch/arm/mach-omap1/board-palmtt.c | 2 +-
+ arch/arm/mach-omap1/board-palmz71.c | 2 +-
+ arch/arm/mach-omap1/board-perseus2.c | 2 +-
+ arch/arm/mach-omap1/board-sx1.c | 2 +-
+ arch/arm/mach-omap1/board-voiceblue.c | 2 +-
+ arch/arm/mach-omap1/time.c | 6 ++--
+ arch/arm/mach-omap2/board-2430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3630sdp.c | 2 +-
+ arch/arm/mach-omap2/board-4430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-am3517crane.c | 2 +-
+ arch/arm/mach-omap2/board-am3517evm.c | 2 +-
+ arch/arm/mach-omap2/board-apollon.c | 2 +-
+ arch/arm/mach-omap2/board-cm-t35.c | 2 +-
+ arch/arm/mach-omap2/board-cm-t3517.c | 2 +-
+ arch/arm/mach-omap2/board-devkit8000.c | 2 +-
+ arch/arm/mach-omap2/board-generic.c | 2 +-
+ arch/arm/mach-omap2/board-h4.c | 2 +-
+ arch/arm/mach-omap2/board-igep0020.c | 4 +-
+ arch/arm/mach-omap2/board-ldp.c | 2 +-
+ arch/arm/mach-omap2/board-n8x0.c | 6 ++--
+ arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
+ arch/arm/mach-omap2/board-omap3evm.c | 2 +-
+ arch/arm/mach-omap2/board-omap3logic.c | 4 +-
+ arch/arm/mach-omap2/board-omap3pandora.c | 2 +-
+ arch/arm/mach-omap2/board-omap3stalker.c | 2 +-
+ arch/arm/mach-omap2/board-omap3touchbook.c | 2 +-
+ arch/arm/mach-omap2/board-omap4panda.c | 2 +-
+ arch/arm/mach-omap2/board-overo.c | 2 +-
+ arch/arm/mach-omap2/board-rm680.c | 2 +-
+ arch/arm/mach-omap2/board-rx51.c | 2 +-
+ arch/arm/mach-omap2/board-ti8168evm.c | 2 +-
+ arch/arm/mach-omap2/board-zoom.c | 4 +-
+ arch/arm/mach-omap2/timer-gp.c | 41 +++++++++++++++++++++-------
+ arch/arm/plat-omap/include/plat/common.h | 6 +++-
+ arch/arm/plat-omap/include/plat/dmtimer.h | 1 -
+ 46 files changed, 86 insertions(+), 62 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
+index e3caef8..312ea6b 100644
+--- a/arch/arm/mach-omap1/board-ams-delta.c
++++ b/arch/arm/mach-omap1/board-ams-delta.c
+@@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
+ .reserve = omap_reserve,
+ .init_irq = ams_delta_init_irq,
+ .init_machine = ams_delta_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+
+ EXPORT_SYMBOL(ams_delta_latch1_write);
+diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
+index eaff305..a6b1bea 100644
+--- a/arch/arm/mach-omap1/board-fsample.c
++++ b/arch/arm/mach-omap1/board-fsample.c
+@@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
+ .reserve = omap_reserve,
+ .init_irq = omap_fsample_init_irq,
+ .init_machine = omap_fsample_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
+index 3fd6b40..04fc356 100644
+--- a/arch/arm/mach-omap1/board-generic.c
++++ b/arch/arm/mach-omap1/board-generic.c
+@@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
+ .reserve = omap_reserve,
+ .init_irq = omap_generic_init_irq,
+ .init_machine = omap_generic_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
+index 8147b04..cb7fb1a 100644
+--- a/arch/arm/mach-omap1/board-h2.c
++++ b/arch/arm/mach-omap1/board-h2.c
+@@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
+ .reserve = omap_reserve,
+ .init_irq = h2_init_irq,
+ .init_machine = h2_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
+index 1b448f6..31f3487 100644
+--- a/arch/arm/mach-omap1/board-h3.c
++++ b/arch/arm/mach-omap1/board-h3.c
+@@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
+ .reserve = omap_reserve,
+ .init_irq = h3_init_irq,
+ .init_machine = h3_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
+index 1bd4d8e..36e06ea 100644
+--- a/arch/arm/mach-omap1/board-htcherald.c
++++ b/arch/arm/mach-omap1/board-htcherald.c
+@@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
+ .reserve = omap_reserve,
+ .init_irq = htcherald_init_irq,
+ .init_machine = htcherald_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
+index 5926b0c..0b1ba46 100644
+--- a/arch/arm/mach-omap1/board-innovator.c
++++ b/arch/arm/mach-omap1/board-innovator.c
+@@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
+ .reserve = omap_reserve,
+ .init_irq = innovator_init_irq,
+ .init_machine = innovator_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index e3cf21d..5469ce2 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
+ .reserve = omap_reserve,
+ .init_irq = omap_nokia770_init_irq,
+ .init_machine = omap_nokia770_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
+index 1e7823d..b08a213 100644
+--- a/arch/arm/mach-omap1/board-osk.c
++++ b/arch/arm/mach-omap1/board-osk.c
+@@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
+ .reserve = omap_reserve,
+ .init_irq = osk_init_irq,
+ .init_machine = osk_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
+index 8b6a881..459cb6b 100644
+--- a/arch/arm/mach-omap1/board-palmte.c
++++ b/arch/arm/mach-omap1/board-palmte.c
+@@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
+ .reserve = omap_reserve,
+ .init_irq = omap_palmte_init_irq,
+ .init_machine = omap_palmte_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
+index f2de43d..b214f45 100644
+--- a/arch/arm/mach-omap1/board-palmtt.c
++++ b/arch/arm/mach-omap1/board-palmtt.c
+@@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
+ .reserve = omap_reserve,
+ .init_irq = omap_palmtt_init_irq,
+ .init_machine = omap_palmtt_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
+index 6665d2d..9b0ea48 100644
+--- a/arch/arm/mach-omap1/board-palmz71.c
++++ b/arch/arm/mach-omap1/board-palmz71.c
+@@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
+ .reserve = omap_reserve,
+ .init_irq = omap_palmz71_init_irq,
+ .init_machine = omap_palmz71_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
+index 7f019e5..67acd41 100644
+--- a/arch/arm/mach-omap1/board-perseus2.c
++++ b/arch/arm/mach-omap1/board-perseus2.c
+@@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
+ .reserve = omap_reserve,
+ .init_irq = omap_perseus2_init_irq,
+ .init_machine = omap_perseus2_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
+index 24f0f7b..9c3b7c5 100644
+--- a/arch/arm/mach-omap1/board-sx1.c
++++ b/arch/arm/mach-omap1/board-sx1.c
+@@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
+ .reserve = omap_reserve,
+ .init_irq = omap_sx1_init_irq,
+ .init_machine = omap_sx1_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
+index 98826e2..036edc0 100644
+--- a/arch/arm/mach-omap1/board-voiceblue.c
++++ b/arch/arm/mach-omap1/board-voiceblue.c
+@@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
+ .reserve = omap_reserve,
+ .init_irq = voiceblue_init_irq,
+ .init_machine = voiceblue_init,
+- .timer = &omap_timer,
++ .timer = &omap1_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
+index 03e1e10..a183777 100644
+--- a/arch/arm/mach-omap1/time.c
++++ b/arch/arm/mach-omap1/time.c
+@@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
+ * Timer initialization
+ * ---------------------------------------------------------------------------
+ */
+-static void __init omap_timer_init(void)
++static void __init omap1_timer_init(void)
+ {
+ if (omap_32k_timer_usable()) {
+ preferred_sched_clock_init(1);
+@@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
+ }
+ }
+
+-struct sys_timer omap_timer = {
+- .init = omap_timer_init,
++struct sys_timer omap1_timer = {
++ .init = omap1_timer_init,
+ };
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index 45cabc5..2028464 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -262,5 +262,5 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
+ .init_early = omap_2430sdp_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = omap_2430sdp_init,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 85b207f..12fae21 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -806,5 +806,5 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
+ .init_early = omap_3430sdp_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap_3430sdp_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
+index 2ec2d76..e4f37b5 100644
+--- a/arch/arm/mach-omap2/board-3630sdp.c
++++ b/arch/arm/mach-omap2/board-3630sdp.c
+@@ -221,5 +221,5 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
+ .init_early = omap_sdp_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap_sdp_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 39a8062..e8caced 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -768,5 +768,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
+ .init_early = omap_4430sdp_init_early,
+ .init_irq = gic_init_irq,
+ .init_machine = omap_4430sdp_init,
+- .timer = &omap_timer,
++ .timer = &omap4_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
+index 0bed0a4..5f2b55f 100644
+--- a/arch/arm/mach-omap2/board-am3517crane.c
++++ b/arch/arm/mach-omap2/board-am3517crane.c
+@@ -106,5 +106,5 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+ .init_early = am3517_crane_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = am3517_crane_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index 0db0fb8..f3006c3 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -496,5 +496,5 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
+ .init_early = am3517_evm_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = am3517_evm_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
+index 93576c8..7021170 100644
+--- a/arch/arm/mach-omap2/board-apollon.c
++++ b/arch/arm/mach-omap2/board-apollon.c
+@@ -356,5 +356,5 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
+ .init_early = omap_apollon_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = omap_apollon_init,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 43b1de5..1a18d3b 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -646,5 +646,5 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
+ .init_early = cm_t35_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = cm_t35_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index 8f15222..aa67240 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -306,5 +306,5 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
+ .init_early = cm_t3517_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = cm_t3517_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 73f3a22..46d144d 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -709,5 +709,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
+ .init_early = devkit8000_init_early,
+ .init_irq = devkit8000_init_irq,
+ .init_machine = devkit8000_init,
+- .timer = &omap_timer,
++ .timer = &omap3_secure_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
+index ccd503a..c6ecf60 100644
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -72,5 +72,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+ .init_early = omap_generic_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = omap_generic_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
+index 2e16d6c..45de2b3 100644
+--- a/arch/arm/mach-omap2/board-h4.c
++++ b/arch/arm/mach-omap2/board-h4.c
+@@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
+ .init_early = omap_h4_init_early,
+ .init_irq = omap_h4_init_irq,
+ .init_machine = omap_h4_init,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index f22a76a..f683835 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -708,7 +708,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
+ .init_early = igep_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = igep_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+
+ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+@@ -718,5 +718,5 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+ .init_early = igep_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = igep_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index 9671843..5d4328f 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -350,5 +350,5 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
+ .init_early = omap_ldp_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap_ldp_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
+index 9c791a2..e11f0c5 100644
+--- a/arch/arm/mach-omap2/board-n8x0.c
++++ b/arch/arm/mach-omap2/board-n8x0.c
+@@ -701,7 +701,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
+ .init_early = n8x0_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+
+ MACHINE_START(NOKIA_N810, "Nokia N810")
+@@ -711,7 +711,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
+ .init_early = n8x0_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+
+ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
+@@ -721,5 +721,5 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
+ .init_early = n8x0_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = n8x0_init_machine,
+- .timer = &omap_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index eaead5e..9ee16f6 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -596,5 +596,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ .init_early = omap3_beagle_init_early,
+ .init_irq = omap3_beagle_init_irq,
+ .init_machine = omap3_beagle_init,
+- .timer = &omap_timer,
++ .timer = &omap3_secure_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index d39f53f..6f957ed 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -741,5 +741,5 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
+ .init_early = omap3_evm_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap3_evm_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index b63f1c2..469259a 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -215,7 +215,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+ .init_early = omap3logic_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap3logic_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+
+ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+@@ -224,5 +224,5 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+ .init_early = omap3logic_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap3logic_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index 1d90b90..d4ea940 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -652,5 +652,5 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
+ .init_early = omap3pandora_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap3pandora_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index dfa1401..2fa8fae 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -557,5 +557,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
+ .init_early = omap3_stalker_init_early,
+ .init_irq = omap3_stalker_init_irq,
+ .init_machine = omap3_stalker_init,
+- .timer = &omap_timer,
++ .timer = &omap3_secure_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index ae97910..8c71fd2 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -449,5 +449,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
+ .init_early = omap3_touchbook_init_early,
+ .init_irq = omap3_touchbook_init_irq,
+ .init_machine = omap3_touchbook_init,
+- .timer = &omap_timer,
++ .timer = &omap3_secure_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 6d2372b..dc1d6dc 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -712,5 +712,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
+ .init_early = omap4_panda_init_early,
+ .init_irq = gic_init_irq,
+ .init_machine = omap4_panda_init,
+- .timer = &omap_timer,
++ .timer = &omap4_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index e3928f2..1bf2f39 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -617,5 +617,5 @@ MACHINE_START(OVERO, "Gumstix Overo")
+ .init_early = overo_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = overo_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
+index 9c3d115..54dceb1 100644
+--- a/arch/arm/mach-omap2/board-rm680.c
++++ b/arch/arm/mach-omap2/board-rm680.c
+@@ -165,5 +165,5 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+ .init_early = rm680_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = rm680_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
+index ee35e4e..5ea142f 100644
+--- a/arch/arm/mach-omap2/board-rx51.c
++++ b/arch/arm/mach-omap2/board-rx51.c
+@@ -162,5 +162,5 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
+ .init_early = rx51_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = rx51_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
+index 713c20f..a85d5b0 100644
+--- a/arch/arm/mach-omap2/board-ti8168evm.c
++++ b/arch/arm/mach-omap2/board-ti8168evm.c
+@@ -52,6 +52,6 @@ MACHINE_START(TI8168EVM, "ti8168evm")
+ .map_io = ti8168_evm_map_io,
+ .init_early = ti8168_init_early,
+ .init_irq = ti816x_init_irq,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ .init_machine = ti8168_evm_init,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
+index 97a3f0b..8a98c3c 100644
+--- a/arch/arm/mach-omap2/board-zoom.c
++++ b/arch/arm/mach-omap2/board-zoom.c
+@@ -139,7 +139,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+ .init_early = omap_zoom_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap_zoom_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+
+ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
+@@ -149,5 +149,5 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
+ .init_early = omap_zoom_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = omap_zoom_init,
+- .timer = &omap_timer,
++ .timer = &omap3_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 3b9cf85..a0d8e83 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -247,20 +247,41 @@ static void __init omap2_gp_clocksource_init(void)
+ }
+ #endif
+
+-static void __init omap2_gp_timer_init(void)
++#define OMAP_SYS_TIMER_INIT(name) \
++static void __init omap##name##_timer_init(void) \
++{ \
++ omap_dm_timer_init(); \
++ omap2_gp_clockevent_init(); \
++ omap2_gp_clocksource_init(); \
++}
++
++#define OMAP_SYS_TIMER(name) \
++struct sys_timer omap##name##_timer = { \
++ .init = omap##name##_timer_init, \
++};
++
++#ifdef CONFIG_ARCH_OMAP2
++OMAP_SYS_TIMER_INIT(2)
++OMAP_SYS_TIMER(2)
++#endif
++
++#ifdef CONFIG_ARCH_OMAP3
++OMAP_SYS_TIMER_INIT(3)
++OMAP_SYS_TIMER(3)
++OMAP_SYS_TIMER_INIT(3_secure)
++OMAP_SYS_TIMER(3_secure)
++#endif
++
++#ifdef CONFIG_ARCH_OMAP4
++static void __init omap4_timer_init(void)
+ {
+ #ifdef CONFIG_LOCAL_TIMERS
+- if (cpu_is_omap44xx()) {
+- twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+- BUG_ON(!twd_base);
+- }
++ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
++ BUG_ON(!twd_base);
+ #endif
+ omap_dm_timer_init();
+-
+ omap2_gp_clockevent_init();
+ omap2_gp_clocksource_init();
+ }
+-
+-struct sys_timer omap_timer = {
+- .init = omap2_gp_timer_init,
+-};
++OMAP_SYS_TIMER(4)
++#endif
+diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
+index 5288130..4564cc6 100644
+--- a/arch/arm/plat-omap/include/plat/common.h
++++ b/arch/arm/plat-omap/include/plat/common.h
+@@ -34,7 +34,11 @@
+ struct sys_timer;
+
+ extern void omap_map_common_io(void);
+-extern struct sys_timer omap_timer;
++extern struct sys_timer omap1_timer;
++extern struct sys_timer omap2_timer;
++extern struct sys_timer omap3_timer;
++extern struct sys_timer omap3_secure_timer;
++extern struct sys_timer omap4_timer;
+ extern bool omap_32k_timer_init(void);
+ extern int __init omap_init_clocksource_32k(void);
+ extern unsigned long long notrace omap_32k_sched_clock(void);
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index d6c70d2..330bd17 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -57,7 +57,6 @@
+ #define OMAP_TIMER_IP_VERSION_1 0x1
+ struct omap_dm_timer;
+ extern struct omap_dm_timer *gptimer_wakeup;
+-extern struct sys_timer omap_timer;
+ struct clk;
+
+ int omap_dm_timer_init(void);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0005-omap-Move-dmtimer-defines-to-dmtimer.h.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0005-omap-Move-dmtimer-defines-to-dmtimer.h.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0005-omap-Move-dmtimer-defines-to-dmtimer.h.patch
@@ -0,0 +1,287 @@
+From 77203d7fdc186db617c03d3ef28981b77af3b077 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:48 -0700
+Subject: [PATCH 005/149] omap: Move dmtimer defines to dmtimer.h
+
+These will be needed when dmtimer platform init code gets split
+for omap1 and omap2+. These will also be needed for separate
+sys_timer init and driver init for the rest of the hardware timers
+in the following patches. No functional changes.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/plat-omap/dmtimer.c | 121 ----------------------------
+ arch/arm/plat-omap/include/plat/dmtimer.h | 125 +++++++++++++++++++++++++++++
+ 2 files changed, 125 insertions(+), 121 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
+index ee9f6eb..dfdc3b2 100644
+--- a/arch/arm/plat-omap/dmtimer.c
++++ b/arch/arm/plat-omap/dmtimer.c
+@@ -41,127 +41,6 @@
+ #include <plat/dmtimer.h>
+ #include <mach/irqs.h>
+
+-/* register offsets */
+-#define _OMAP_TIMER_ID_OFFSET 0x00
+-#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
+-#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
+-#define _OMAP_TIMER_STAT_OFFSET 0x18
+-#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
+-#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
+-#define _OMAP_TIMER_CTRL_OFFSET 0x24
+-#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
+-#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
+-#define OMAP_TIMER_CTRL_PT (1 << 12)
+-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
+-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
+-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
+-#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
+-#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
+-#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
+-#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
+-#define OMAP_TIMER_CTRL_POSTED (1 << 2)
+-#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
+-#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
+-#define _OMAP_TIMER_COUNTER_OFFSET 0x28
+-#define _OMAP_TIMER_LOAD_OFFSET 0x2c
+-#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
+-#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
+-#define WP_NONE 0 /* no write pending bit */
+-#define WP_TCLR (1 << 0)
+-#define WP_TCRR (1 << 1)
+-#define WP_TLDR (1 << 2)
+-#define WP_TTGR (1 << 3)
+-#define WP_TMAR (1 << 4)
+-#define WP_TPIR (1 << 5)
+-#define WP_TNIR (1 << 6)
+-#define WP_TCVR (1 << 7)
+-#define WP_TOCR (1 << 8)
+-#define WP_TOWR (1 << 9)
+-#define _OMAP_TIMER_MATCH_OFFSET 0x38
+-#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
+-#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
+-#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
+-#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
+-#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
+-#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
+-#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
+-#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
+-
+-/* register offsets with the write pending bit encoded */
+-#define WPSHIFT 16
+-
+-#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
+- | (WP_TCLR << WPSHIFT))
+-
+-#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
+- | (WP_TCRR << WPSHIFT))
+-
+-#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
+- | (WP_TLDR << WPSHIFT))
+-
+-#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
+- | (WP_TTGR << WPSHIFT))
+-
+-#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
+- | (WP_TMAR << WPSHIFT))
+-
+-#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
+- | (WP_NONE << WPSHIFT))
+-
+-#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
+- | (WP_TPIR << WPSHIFT))
+-
+-#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
+- | (WP_TNIR << WPSHIFT))
+-
+-#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
+- | (WP_TCVR << WPSHIFT))
+-
+-#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
+- (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+-
+-#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
+- (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+-
+-struct omap_dm_timer {
+- unsigned long phys_base;
+- int irq;
+-#ifdef CONFIG_ARCH_OMAP2PLUS
+- struct clk *iclk, *fclk;
+-#endif
+- void __iomem *io_base;
+- unsigned reserved:1;
+- unsigned enabled:1;
+- unsigned posted:1;
+-};
+-
+ static int dm_timer_count;
+
+ #ifdef CONFIG_ARCH_OMAP1
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index 330bd17..3203105 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -92,5 +92,130 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
+
+ int omap_dm_timers_active(void);
+
++/*
++ * Do not use the defines below, they are not needed. They should be only
++ * used by dmtimer.c and sys_timer related code.
++ */
++
++/* register offsets */
++#define _OMAP_TIMER_ID_OFFSET 0x00
++#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
++#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
++#define _OMAP_TIMER_STAT_OFFSET 0x18
++#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
++#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
++#define _OMAP_TIMER_CTRL_OFFSET 0x24
++#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
++#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
++#define OMAP_TIMER_CTRL_PT (1 << 12)
++#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
++#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
++#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
++#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
++#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
++#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
++#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
++#define OMAP_TIMER_CTRL_POSTED (1 << 2)
++#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
++#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
++#define _OMAP_TIMER_COUNTER_OFFSET 0x28
++#define _OMAP_TIMER_LOAD_OFFSET 0x2c
++#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
++#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
++#define WP_NONE 0 /* no write pending bit */
++#define WP_TCLR (1 << 0)
++#define WP_TCRR (1 << 1)
++#define WP_TLDR (1 << 2)
++#define WP_TTGR (1 << 3)
++#define WP_TMAR (1 << 4)
++#define WP_TPIR (1 << 5)
++#define WP_TNIR (1 << 6)
++#define WP_TCVR (1 << 7)
++#define WP_TOCR (1 << 8)
++#define WP_TOWR (1 << 9)
++#define _OMAP_TIMER_MATCH_OFFSET 0x38
++#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
++#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
++#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
++#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
++#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
++#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
++#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
++#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
++
++/* register offsets with the write pending bit encoded */
++#define WPSHIFT 16
++
++#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
++ | (WP_TCLR << WPSHIFT))
++
++#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
++ | (WP_TCRR << WPSHIFT))
++
++#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
++ | (WP_TLDR << WPSHIFT))
++
++#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
++ | (WP_TTGR << WPSHIFT))
++
++#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
++ | (WP_TMAR << WPSHIFT))
++
++#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
++ | (WP_NONE << WPSHIFT))
++
++#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
++ | (WP_TPIR << WPSHIFT))
++
++#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
++ | (WP_TNIR << WPSHIFT))
++
++#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
++ | (WP_TCVR << WPSHIFT))
++
++#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
++ (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
++
++#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
++ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
++
++struct omap_dm_timer {
++ unsigned long phys_base;
++ int irq;
++#ifdef CONFIG_ARCH_OMAP2PLUS
++ struct clk *iclk, *fclk;
++#endif
++ void __iomem *io_base;
++ unsigned reserved:1;
++ unsigned enabled:1;
++ unsigned posted:1;
++};
+
+ #endif /* __ASM_ARCH_DMTIMER_H */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0006-omap-Make-a-subset-of-dmtimer-functions-into-inline-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0006-omap-Make-a-subset-of-dmtimer-functions-into-inline-.patch
--- /dev/null
@@ -0,0 +1,323 @@
+From e37c3d49a7642a25996d86d97d4e6f36e4c7ed8a Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:48 -0700
+Subject: [PATCH 006/149] omap: Make a subset of dmtimer functions into inline functions
+
+This will allow us to share the code between system timer and
+dmtimer device driver code without having to initialize all the
+dmtimers early. This change will also make the timer_set_next_event
+more efficient as the inline functions will optimize the code
+better for the timer reprogramming.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/plat-omap/dmtimer.c | 78 ++++---------------
+ arch/arm/plat-omap/include/plat/dmtimer.h | 119 +++++++++++++++++++++++++++++
+ 2 files changed, 136 insertions(+), 61 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
+index dfdc3b2..7c5cb4e 100644
+--- a/arch/arm/plat-omap/dmtimer.c
++++ b/arch/arm/plat-omap/dmtimer.c
+@@ -170,11 +170,7 @@ static spinlock_t dm_timer_lock;
+ */
+ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
+ {
+- if (timer->posted)
+- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+- & (reg >> WPSHIFT))
+- cpu_relax();
+- return readl(timer->io_base + (reg & 0xff));
++ return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
+ }
+
+ /*
+@@ -186,11 +182,7 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
+ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
+ u32 value)
+ {
+- if (timer->posted)
+- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+- & (reg >> WPSHIFT))
+- cpu_relax();
+- writel(value, timer->io_base + (reg & 0xff));
++ __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
+ }
+
+ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+@@ -209,7 +201,7 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+
+ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+ {
+- u32 l;
++ int autoidle = 0, wakeup = 0;
+
+ if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+@@ -217,28 +209,21 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+ }
+ omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
+
+- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
+- l |= 0x02 << 3; /* Set to smart-idle mode */
+- l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
+-
+ /* Enable autoidle on OMAP2 / OMAP3 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+- l |= 0x1 << 0;
++ autoidle = 1;
+
+ /*
+ * Enable wake-up on OMAP2 CPUs.
+ */
+ if (cpu_class_is_omap2())
+- l |= 1 << 2;
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
++ wakeup = 1;
+
+- /* Match hardware reset default of posted mode */
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+- OMAP_TIMER_CTRL_POSTED);
++ __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
+ timer->posted = 1;
+ }
+
+-static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
++void omap_dm_timer_prepare(struct omap_dm_timer *timer)
+ {
+ omap_dm_timer_enable(timer);
+ omap_dm_timer_reset(timer);
+@@ -410,25 +395,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
+
+ void omap_dm_timer_stop(struct omap_dm_timer *timer)
+ {
+- u32 l;
++ unsigned long rate = 0;
+
+- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+- if (l & OMAP_TIMER_CTRL_ST) {
+- l &= ~0x1;
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ #ifdef CONFIG_ARCH_OMAP2PLUS
+- /* Readback to make sure write has completed */
+- omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+- /*
+- * Wait for functional clock period x 3.5 to make sure that
+- * timer is stopped
+- */
+- udelay(3500000 / clk_get_rate(timer->fclk) + 1);
++ rate = clk_get_rate(timer->fclk);
+ #endif
+- }
+- /* Ack possibly pending interrupt */
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+- OMAP_TIMER_INT_OVERFLOW);
++
++ __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
+
+@@ -451,22 +424,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
+
+ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
+ {
+- int ret = -EINVAL;
+-
+ if (source < 0 || source >= 3)
+ return -EINVAL;
+
+- clk_disable(timer->fclk);
+- ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
+- clk_enable(timer->fclk);
+-
+- /*
+- * When the functional clock disappears, too quick writes seem
+- * to cause an abort. XXX Is this still necessary?
+- */
+- __delay(300000);
+-
+- return ret;
++ return __omap_dm_timer_set_source(timer->fclk,
++ dm_source_clocks[source]);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
+
+@@ -504,8 +466,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+ }
+ l |= OMAP_TIMER_CTRL_ST;
+
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
++ __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
+
+@@ -558,8 +519,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
+ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
+ unsigned int value)
+ {
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
++ __omap_dm_timer_int_enable(timer->io_base, value);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
+
+@@ -575,17 +535,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
+
+ void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
+ {
+- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
++ __omap_dm_timer_write_status(timer->io_base, value);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
+
+ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
+ {
+- unsigned int l;
+-
+- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
+-
+- return l;
++ return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
+
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index 3203105..54664a7 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -32,6 +32,9 @@
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
++#include <linux/clk.h>
++#include <linux/delay.h>
++
+ #ifndef __ASM_ARCH_DMTIMER_H
+ #define __ASM_ARCH_DMTIMER_H
+
+@@ -218,4 +221,120 @@ struct omap_dm_timer {
+ unsigned posted:1;
+ };
+
++void omap_dm_timer_prepare(struct omap_dm_timer *timer);
++
++static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
++ int posted)
++{
++ if (posted)
++ while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
++ & (reg >> WPSHIFT))
++ cpu_relax();
++
++ return __raw_readl(base + (reg & 0xff));
++}
++
++static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
++ int posted)
++{
++ if (posted)
++ while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
++ & (reg >> WPSHIFT))
++ cpu_relax();
++
++ __raw_writel(val, base + (reg & 0xff));
++}
++
++/* Assumes the source clock has been set by caller */
++static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
++ int wakeup)
++{
++ u32 l;
++
++ l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
++ l |= 0x02 << 3; /* Set to smart-idle mode */
++ l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
++
++ if (autoidle)
++ l |= 0x1 << 0;
++
++ if (wakeup)
++ l |= 1 << 2;
++
++ __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
++
++ /* Match hardware reset default of posted mode */
++ __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
++ OMAP_TIMER_CTRL_POSTED, 0);
++}
++
++static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
++ struct clk *parent)
++{
++ int ret;
++
++ clk_disable(timer_fck);
++ ret = clk_set_parent(timer_fck, parent);
++ clk_enable(timer_fck);
++
++ /*
++ * When the functional clock disappears, too quick writes seem
++ * to cause an abort. XXX Is this still necessary?
++ */
++ __delay(300000);
++
++ return ret;
++}
++
++static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
++ unsigned long rate)
++{
++ u32 l;
++
++ l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
++ if (l & OMAP_TIMER_CTRL_ST) {
++ l &= ~0x1;
++ __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
++#ifdef CONFIG_ARCH_OMAP2PLUS
++ /* Readback to make sure write has completed */
++ __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
++ /*
++ * Wait for functional clock period x 3.5 to make sure that
++ * timer is stopped
++ */
++ udelay(3500000 / rate + 1);
++#endif
++ }
++
++ /* Ack possibly pending interrupt */
++ __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
++ OMAP_TIMER_INT_OVERFLOW, 0);
++}
++
++static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
++ unsigned int load, int posted)
++{
++ __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
++ __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
++}
++
++static inline void __omap_dm_timer_int_enable(void __iomem *base,
++ unsigned int value)
++{
++ __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
++ __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
++}
++
++static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
++ int posted)
++{
++ return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
++}
++
++static inline void __omap_dm_timer_write_status(void __iomem *base,
++ unsigned int value)
++{
++ __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
++}
++
+ #endif /* __ASM_ARCH_DMTIMER_H */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0007-omap2-Use-dmtimer-macros-for-clockevent.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0007-omap2-Use-dmtimer-macros-for-clockevent.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0007-omap2-Use-dmtimer-macros-for-clockevent.patch
@@ -0,0 +1,279 @@
+From 8f20e73dc841e924d8e9cb97b83119f2b45c9dbb Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:48 -0700
+Subject: [PATCH 007/149] omap2+: Use dmtimer macros for clockevent
+
+This patch makes timer-gp.c to use only a subset of dmtimer
+functions without the need to initialize dmtimer code early.
+
+Also note that now with the inline functions, timer_set_next_event
+becomes more efficient in the lines of assembly code.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/timer-gp.c | 147 ++++++++++++++++++++++-------
+ arch/arm/plat-omap/include/plat/dmtimer.h | 1 +
+ 2 files changed, 113 insertions(+), 35 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index a0d8e83..62c0d5c 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -45,10 +45,33 @@
+
+ #include "timer-gp.h"
+
++/* Parent clocks, eventually these will come from the clock framework */
++
++#define OMAP2_MPU_SOURCE "sys_ck"
++#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
++#define OMAP4_MPU_SOURCE "sys_clkin_ck"
++#define OMAP2_32K_SOURCE "func_32k_ck"
++#define OMAP3_32K_SOURCE "omap_32k_fck"
++#define OMAP4_32K_SOURCE "sys_32k_ck"
++
++#ifdef CONFIG_OMAP_32K_TIMER
++#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
++#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
++#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
++#define OMAP3_SECURE_TIMER 12
++#else
++#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
++#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
++#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
++#define OMAP3_SECURE_TIMER 1
++#endif
+
+ /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+ #define MAX_GPTIMER_ID 12
+
++/* Clockevent code */
++
++static struct omap_dm_timer clkev;
+ static struct omap_dm_timer *gptimer;
+ static struct clock_event_device clockevent_gpt;
+ static u8 __initdata gptimer_id = 1;
+@@ -57,10 +80,9 @@ struct omap_dm_timer *gptimer_wakeup;
+
+ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+ {
+- struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+ struct clock_event_device *evt = &clockevent_gpt;
+
+- omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
++ __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+
+ evt->event_handler(evt);
+ return IRQ_HANDLED;
+@@ -75,7 +97,8 @@ static struct irqaction omap2_gp_timer_irq = {
+ static int omap2_gp_timer_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+ {
+- omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
++ __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
++ 0xffffffff - cycles, 1);
+
+ return 0;
+ }
+@@ -85,13 +108,18 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+ {
+ u32 period;
+
+- omap_dm_timer_stop(gptimer);
++ __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+- period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
++ period = clkev.rate / HZ;
+ period -= 1;
+- omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
++ /* Looks like we need to first set the load value separately */
++ __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
++ 0xffffffff - period, 1);
++ __omap_dm_timer_load_start(clkev.io_base,
++ OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
++ 0xffffffff - period, 1);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ break;
+@@ -130,43 +158,89 @@ int __init omap2_gp_clockevent_set_gptimer(u8 id)
+ return 0;
+ }
+
+-static void __init omap2_gp_clockevent_init(void)
++static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
++ int gptimer_id,
++ const char *fck_source)
+ {
+- u32 tick_rate;
+- int src;
+- char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
++ char name[10]; /* 10 = sizeof("gptXX_Xck0") */
++ struct omap_hwmod *oh;
++ size_t size;
++ int res = 0;
++
++ sprintf(name, "timer%d", gptimer_id);
++ omap_hwmod_setup_one(name);
++ oh = omap_hwmod_lookup(name);
++ if (!oh)
++ return -ENODEV;
++
++ timer->irq = oh->mpu_irqs[0].irq;
++ timer->phys_base = oh->slaves[0]->addr->pa_start;
++ size = oh->slaves[0]->addr->pa_end - timer->phys_base;
++
++ /* Static mapping, never released */
++ timer->io_base = ioremap(timer->phys_base, size);
++ if (!timer->io_base)
++ return -ENXIO;
++
++ /* After the dmtimer is using hwmod these clocks won't be needed */
++ sprintf(name, "gpt%d_fck", gptimer_id);
++ timer->fclk = clk_get(NULL, name);
++ if (IS_ERR(timer->fclk))
++ return -ENODEV;
++
++ sprintf(name, "gpt%d_ick", gptimer_id);
++ timer->iclk = clk_get(NULL, name);
++ if (IS_ERR(timer->iclk)) {
++ clk_put(timer->fclk);
++ return -ENODEV;
++ }
+
+- inited = 1;
++ omap_hwmod_enable(oh);
++
++ if (gptimer_id != 12) {
++ struct clk *src;
++
++ src = clk_get(NULL, fck_source);
++ if (IS_ERR(src)) {
++ res = -EINVAL;
++ } else {
++ res = __omap_dm_timer_set_source(timer->fclk, src);
++ if (IS_ERR_VALUE(res))
++ pr_warning("%s: timer%i cannot set source\n",
++ __func__, gptimer_id);
++ clk_put(src);
++ }
++ }
++ __omap_dm_timer_reset(timer->io_base, 1, 1);
++ timer->posted = 1;
++
++ timer->rate = clk_get_rate(timer->fclk);
+
+- sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
+- omap_hwmod_setup_one(clockevent_hwmod_name);
++ timer->reserved = 1;
+
+ gptimer = omap_dm_timer_request_specific(gptimer_id);
+ BUG_ON(gptimer == NULL);
+ gptimer_wakeup = gptimer;
+
+-#if defined(CONFIG_OMAP_32K_TIMER)
+- src = OMAP_TIMER_SRC_32_KHZ;
+-#else
+- src = OMAP_TIMER_SRC_SYS_CLK;
+- WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
+- "secure 32KiHz clock source\n");
+-#endif
++ return res;
++}
+
+- if (gptimer_id != 12)
+- WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
+- "timer-gp: omap_dm_timer_set_source() failed\n");
++static void __init omap2_gp_clockevent_init(int gptimer_id,
++ const char *fck_source)
++{
++ int res;
+
+- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
++ inited = 1;
+
+- pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
+- gptimer_id, tick_rate);
++ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
++ BUG_ON(res);
+
+ omap2_gp_timer_irq.dev_id = (void *)gptimer;
+- setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
+- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
++ setup_irq(clkev.irq, &omap2_gp_timer_irq);
+
+- clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
++ __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
++
++ clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
+ clockevent_gpt.shift);
+ clockevent_gpt.max_delta_ns =
+ clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+@@ -176,6 +250,9 @@ static void __init omap2_gp_clockevent_init(void)
+
+ clockevent_gpt.cpumask = cpumask_of(0);
+ clockevents_register_device(&clockevent_gpt);
++
++ pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
++ gptimer_id, clkev.rate);
+ }
+
+ /* Clocksource code */
+@@ -247,11 +324,11 @@ static void __init omap2_gp_clocksource_init(void)
+ }
+ #endif
+
+-#define OMAP_SYS_TIMER_INIT(name) \
++#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src) \
+ static void __init omap##name##_timer_init(void) \
+ { \
+ omap_dm_timer_init(); \
+- omap2_gp_clockevent_init(); \
++ omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+ omap2_gp_clocksource_init(); \
+ }
+
+@@ -261,14 +338,14 @@ struct sys_timer omap##name##_timer = { \
+ };
+
+ #ifdef CONFIG_ARCH_OMAP2
+-OMAP_SYS_TIMER_INIT(2)
++OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE)
+ OMAP_SYS_TIMER(2)
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP3
+-OMAP_SYS_TIMER_INIT(3)
++OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE)
+ OMAP_SYS_TIMER(3)
+-OMAP_SYS_TIMER_INIT(3_secure)
++OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE)
+ OMAP_SYS_TIMER(3_secure)
+ #endif
+
+@@ -280,7 +357,7 @@ static void __init omap4_timer_init(void)
+ BUG_ON(!twd_base);
+ #endif
+ omap_dm_timer_init();
+- omap2_gp_clockevent_init();
++ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+ omap2_gp_clocksource_init();
+ }
+ OMAP_SYS_TIMER(4)
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index 54664a7..dd8b3ff 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -216,6 +216,7 @@ struct omap_dm_timer {
+ struct clk *iclk, *fclk;
+ #endif
+ void __iomem *io_base;
++ unsigned long rate;
+ unsigned reserved:1;
+ unsigned enabled:1;
+ unsigned posted:1;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0008-omap2-Remove-gptimer_wakeup-for-now.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0008-omap2-Remove-gptimer_wakeup-for-now.patch
--- /dev/null
@@ -0,0 +1,177 @@
+From 426a4d3d331abef9fb16e9207885bda1db8c7d69 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:49 -0700
+Subject: [PATCH 008/149] omap2+: Remove gptimer_wakeup for now
+
+This removes the support for setting the wake-up timer for debugging.
+
+Later on we can reserve gptimer1 for PM code only and have similar
+functionality.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/pm-debug.c | 28 ----------------------------
+ arch/arm/mach-omap2/pm.h | 6 ------
+ arch/arm/mach-omap2/pm34xx.c | 4 ----
+ arch/arm/mach-omap2/timer-gp.c | 8 +-------
+ arch/arm/plat-omap/include/plat/dmtimer.h | 1 -
+ 5 files changed, 1 insertions(+), 46 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
+index e01da45..2c35bd3 100644
+--- a/arch/arm/mach-omap2/pm-debug.c
++++ b/arch/arm/mach-omap2/pm-debug.c
+@@ -31,7 +31,6 @@
+ #include <plat/board.h>
+ #include "powerdomain.h"
+ #include "clockdomain.h"
+-#include <plat/dmtimer.h>
+ #include <plat/omap-pm.h>
+
+ #include "cm2xxx_3xxx.h"
+@@ -41,8 +40,6 @@
+ int omap2_pm_debug;
+ u32 enable_off_mode;
+ u32 sleep_while_idle;
+-u32 wakeup_timer_seconds;
+-u32 wakeup_timer_milliseconds;
+
+ #define DUMP_PRM_MOD_REG(mod, reg) \
+ regs[reg_count].name = #mod "." #reg; \
+@@ -162,23 +159,6 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
+ printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
+ }
+
+-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+-{
+- u32 tick_rate, cycles;
+-
+- if (!seconds && !milliseconds)
+- return;
+-
+- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+- cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+- omap_dm_timer_stop(gptimer_wakeup);
+- omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+-
+- pr_info("PM: Resume timer in %u.%03u secs"
+- " (%d ticks at %d ticks/sec.)\n",
+- seconds, milliseconds, cycles, tick_rate);
+-}
+-
+ #ifdef CONFIG_DEBUG_FS
+ #include <linux/debugfs.h>
+ #include <linux/seq_file.h>
+@@ -576,9 +556,6 @@ static int option_set(void *data, u64 val)
+ {
+ u32 *option = data;
+
+- if (option == &wakeup_timer_milliseconds && val >= 1000)
+- return -EINVAL;
+-
+ *option = val;
+
+ if (option == &enable_off_mode) {
+@@ -641,11 +618,6 @@ static int pm_dbg_init(void)
+ &enable_off_mode, &pm_dbg_option_fops);
+ (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
+ &sleep_while_idle, &pm_dbg_option_fops);
+- (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
+- &wakeup_timer_seconds, &pm_dbg_option_fops);
+- (void) debugfs_create_file("wakeup_timer_milliseconds",
+- S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
+- &pm_dbg_option_fops);
+ pm_dbg_init_done = 1;
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
+index 45bcfce..c3a367e 100644
+--- a/arch/arm/mach-omap2/pm.h
++++ b/arch/arm/mach-omap2/pm.h
+@@ -60,19 +60,13 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
+ extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
+ extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+
+-extern u32 wakeup_timer_seconds;
+-extern u32 wakeup_timer_milliseconds;
+-extern struct omap_dm_timer *gptimer_wakeup;
+-
+ #ifdef CONFIG_PM_DEBUG
+ extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+-extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
+ extern int omap2_pm_debug;
+ extern u32 enable_off_mode;
+ extern u32 sleep_while_idle;
+ #else
+ #define omap2_pm_dump(mode, resume, us) do {} while (0);
+-#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
+ #define omap2_pm_debug 0
+ #define enable_off_mode 0
+ #define sleep_while_idle 0
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index c155c9d..4cb636a 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -534,10 +534,6 @@ static int omap3_pm_suspend(void)
+ struct power_state *pwrst;
+ int state, ret = 0;
+
+- if (wakeup_timer_seconds || wakeup_timer_milliseconds)
+- omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
+- wakeup_timer_milliseconds);
+-
+ /* Read current next_pwrsts */
+ list_for_each_entry(pwrst, &pwrst_list, node)
+ pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 62c0d5c..578e9df 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -72,11 +72,9 @@
+ /* Clockevent code */
+
+ static struct omap_dm_timer clkev;
+-static struct omap_dm_timer *gptimer;
+ static struct clock_event_device clockevent_gpt;
+ static u8 __initdata gptimer_id = 1;
+ static u8 __initdata inited;
+-struct omap_dm_timer *gptimer_wakeup;
+
+ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+ {
+@@ -218,10 +216,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+
+ timer->reserved = 1;
+
+- gptimer = omap_dm_timer_request_specific(gptimer_id);
+- BUG_ON(gptimer == NULL);
+- gptimer_wakeup = gptimer;
+-
+ return res;
+ }
+
+@@ -235,7 +229,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+ BUG_ON(res);
+
+- omap2_gp_timer_irq.dev_id = (void *)gptimer;
++ omap2_gp_timer_irq.dev_id = (void *)&clkev;
+ setup_irq(clkev.irq, &omap2_gp_timer_irq);
+
+ __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index dd8b3ff..8adcb18 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -59,7 +59,6 @@
+ */
+ #define OMAP_TIMER_IP_VERSION_1 0x1
+ struct omap_dm_timer;
+-extern struct omap_dm_timer *gptimer_wakeup;
+ struct clk;
+
+ int omap_dm_timer_init(void);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0009-OMAP3-SR-make-notify-independent-of-class.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0009-OMAP3-SR-make-notify-independent-of-class.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0009-OMAP3-SR-make-notify-independent-of-class.patch
@@ -0,0 +1,47 @@
+From 492d2ffec3453c8fc887c73963d8e77ef9677189 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Mon, 14 Feb 2011 12:16:36 +0530
+Subject: [PATCH 009/149] OMAP3+: SR: make notify independent of class
+
+Interrupt notification mechanism of SmartReflex can be used by the
+choice of implementation of the class driver. For example, Class 2 and
+Class 1.5 of SmartReflex can both use the interrupt notification to
+identify the transition of voltage or other events.
+
+Hence, the actual class does not matter for notifier. Let the class
+driver's handling decide how it should be used. SmartReflex driver
+should provide just the primitives.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/smartreflex.c | 6 ++----
+ 1 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index fb7dc52..3ee7261 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
+ sr_write_reg(sr_info, IRQSTATUS, status);
+ }
+
+- if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
++ if (sr_class->notify)
+ sr_class->notify(sr_info->voltdm, status);
+
+ return IRQ_HANDLED;
+@@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
+ struct resource *mem;
+ int ret = 0;
+
+- if (sr_class->class_type == SR_CLASS2 &&
+- sr_class->notify_flags && sr_info->irq) {
+-
++ if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
+ name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
+ if (name == NULL) {
+ ret = -ENOMEM;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0001-OMAP3-SR-disable-interrupt-by-default.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0010-OMAP3-SR-disable-interrupt-by-default.patch
similarity index 82%
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0001-OMAP3-SR-disable-interrupt-by-default.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0010-OMAP3-SR-disable-interrupt-by-default.patch
index ebb1f14e71cbeba06d950da53056cf44586982ee..447d242423eecaf8c508f73c054eb3fc0e346d11 100644 (file)
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0001-OMAP3-SR-disable-interrupt-by-default.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0010-OMAP3-SR-disable-interrupt-by-default.patch
index ebb1f14e71cbeba06d950da53056cf44586982ee..447d242423eecaf8c508f73c054eb3fc0e346d11 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0001-OMAP3-SR-disable-interrupt-by-default.patch
-From 0c06ec8074efa965a12ce79122ab64cebbb27dc9 Mon Sep 17 00:00:00 2001
+From 7810a0932b5e0d4fdf6c34cff735e227f5af8392 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Mon, 14 Feb 2011 12:41:10 +0530
-Subject: [PATCH 1/7] OMAP3+: SR: disable interrupt by default
+Subject: [PATCH 010/149] OMAP3+: SR: disable interrupt by default
We will enable and disable interrupt on a need basis in the class
driver. We need to keep the IRQ disabled by default else the
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index fb7dc52..998b57f 100644
+index 3ee7261..616ef62 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -270,6 +270,7 @@ static int sr_late_init(struct omap_sr *sr_info)
+@@ -268,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
0, name, (void *)sr_info);
if (ret)
goto error;
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0002-OMAP3-SR-enable-disable-SR-only-on-need.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0011-OMAP3-SR-enable-disable-SR-only-on-need.patch
similarity index 81%
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0002-OMAP3-SR-enable-disable-SR-only-on-need.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0011-OMAP3-SR-enable-disable-SR-only-on-need.patch
index 761e56db38f621a5fb7d6f7a111a8759815ddd51..d50e3ad1c528c5f3f9743081ea11573f4ef53a02 100644 (file)
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0002-OMAP3-SR-enable-disable-SR-only-on-need.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0011-OMAP3-SR-enable-disable-SR-only-on-need.patch
index 761e56db38f621a5fb7d6f7a111a8759815ddd51..d50e3ad1c528c5f3f9743081ea11573f4ef53a02 100644 (file)
--- a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0002-OMAP3-SR-enable-disable-SR-only-on-need.patch
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0011-OMAP3-SR-enable-disable-SR-only-on-need.patch
-From 2c555d8ee3544326033cb3b0ead6c0eb48cb4919 Mon Sep 17 00:00:00 2001
+From 50c59ea316d283dddb432ed03cffcb42a25bf7b9 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Mon, 14 Feb 2011 21:14:17 +0530
-Subject: [PATCH 2/7] OMAP3+: SR: enable/disable SR only on need
+Subject: [PATCH 011/149] OMAP3+: SR: enable/disable SR only on need
Since we already know the state of the autocomp enablement, we can
see if the requested state is different from the current state and
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index 998b57f..a4b4319 100644
+index 616ef62..3bd9fac 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -809,10 +809,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
+@@ -807,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
return -EINVAL;
}
diff --git a/recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0003-OMAP3-SR-fix-cosmetic-indentation.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0012-OMAP3-SR-fix-cosmetic-indentation.patch
similarity index 86%
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0003-OMAP3-SR-fix-cosmetic-indentation.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0012-OMAP3-SR-fix-cosmetic-indentation.patch
index b528a9e744c960244e117af4c20f4fb6e138e16e..3a0cb6b8ac4baa0adf5fd46fddf3de892c01ac9e 100644 (file)
rename from recipes-kernel/linux/linux-3.0/for_3.1/pm-misc/0003-OMAP3-SR-fix-cosmetic-indentation.patch
rename to recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0012-OMAP3-SR-fix-cosmetic-indentation.patch
index b528a9e744c960244e117af4c20f4fb6e138e16e..3a0cb6b8ac4baa0adf5fd46fddf3de892c01ac9e 100644 (file)
-From 60b31f5fad1dda709f3e38ad88dcc8d1496db52d Mon Sep 17 00:00:00 2001
+From 0871e261feec9b1e02efc91201aeab9f11bc5ce3 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Mon, 14 Feb 2011 12:33:13 +0530
-Subject: [PATCH 3/7] OMAP3+: SR: fix cosmetic indentation
+Subject: [PATCH 012/149] OMAP3+: SR: fix cosmetic indentation
Error label case seems to have a 2 tab indentation when just 1 is
necessary.
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index a4b4319..931879d 100644
+index 3bd9fac..2ce2fb7 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -279,16 +279,16 @@ static int sr_late_init(struct omap_sr *sr_info)
+@@ -277,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
return ret;
error:
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0013-omap2-Reserve-clocksource-and-timesource-and-initial.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0013-omap2-Reserve-clocksource-and-timesource-and-initial.patch
--- /dev/null
@@ -0,0 +1,125 @@
+From c3c0bfa5bf8ccbea4189cb76b842c51b8e3756c7 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:49 -0700
+Subject: [PATCH 013/149] omap2+: Reserve clocksource and timesource and initialize dmtimer later
+
+There's no need to initialize the dmtimer framework early.
+Just mark the clocksource and timesource as reserved, and
+initialize dmtimer with an arch_initcall.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap1/timer32k.c | 4 ----
+ arch/arm/mach-omap2/timer-gp.c | 6 ++++--
+ arch/arm/plat-omap/dmtimer.c | 10 +++++++++-
+ arch/arm/plat-omap/include/plat/dmtimer.h | 3 +--
+ 4 files changed, 14 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
+index 13d7b8f..96604a5 100644
+--- a/arch/arm/mach-omap1/timer32k.c
++++ b/arch/arm/mach-omap1/timer32k.c
+@@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
+ bool __init omap_32k_timer_init(void)
+ {
+ omap_init_clocksource_32k();
+-
+-#ifdef CONFIG_OMAP_DM_TIMER
+- omap_dm_timer_init();
+-#endif
+ omap_init_32k_timer();
+
+ return true;
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 578e9df..cf2ec85 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -69,6 +69,8 @@
+ /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+ #define MAX_GPTIMER_ID 12
+
++u32 sys_timer_reserved;
++
+ /* Clockevent code */
+
+ static struct omap_dm_timer clkev;
+@@ -195,6 +197,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+
+ omap_hwmod_enable(oh);
+
++ sys_timer_reserved |= (1 << (gptimer_id - 1));
++
+ if (gptimer_id != 12) {
+ struct clk *src;
+
+@@ -321,7 +325,6 @@ static void __init omap2_gp_clocksource_init(void)
+ #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src) \
+ static void __init omap##name##_timer_init(void) \
+ { \
+- omap_dm_timer_init(); \
+ omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+ omap2_gp_clocksource_init(); \
+ }
+@@ -350,7 +353,6 @@ static void __init omap4_timer_init(void)
+ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+ BUG_ON(!twd_base);
+ #endif
+- omap_dm_timer_init();
+ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+ omap2_gp_clocksource_init();
+ }
+diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
+index 7c5cb4e..8dfb818 100644
+--- a/arch/arm/plat-omap/dmtimer.c
++++ b/arch/arm/plat-omap/dmtimer.c
+@@ -572,7 +572,7 @@ int omap_dm_timers_active(void)
+ }
+ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
+
+-int __init omap_dm_timer_init(void)
++static int __init omap_dm_timer_init(void)
+ {
+ struct omap_dm_timer *timer;
+ int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
+@@ -625,8 +625,16 @@ int __init omap_dm_timer_init(void)
+ sprintf(clk_name, "gpt%d_fck", i + 1);
+ timer->fclk = clk_get(NULL, clk_name);
+ }
++
++ /* One or two timers may be set up early for sys_timer */
++ if (sys_timer_reserved & (1 << i)) {
++ timer->reserved = 1;
++ timer->posted = 1;
++ }
+ #endif
+ }
+
+ return 0;
+ }
++
++arch_initcall(omap_dm_timer_init);
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index 8adcb18..d0f3a2d 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -61,8 +61,6 @@
+ struct omap_dm_timer;
+ struct clk;
+
+-int omap_dm_timer_init(void);
+-
+ struct omap_dm_timer *omap_dm_timer_request(void);
+ struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+ void omap_dm_timer_free(struct omap_dm_timer *timer);
+@@ -221,6 +219,7 @@ struct omap_dm_timer {
+ unsigned posted:1;
+ };
+
++extern u32 sys_timer_reserved;
+ void omap_dm_timer_prepare(struct omap_dm_timer *timer);
+
+ static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0014-omap2-Use-dmtimer-macros-for-clocksource.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0014-omap2-Use-dmtimer-macros-for-clocksource.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0014-omap2-Use-dmtimer-macros-for-clocksource.patch
@@ -0,0 +1,163 @@
+From 939c8d3b49f31a6e88d36a9915e1393d26533ba8 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:49 -0700
+Subject: [PATCH 014/149] omap2+: Use dmtimer macros for clocksource
+
+Use dmtimer macros for clocksource. As with the clockevent,
+this allows us to initialize the rest of dmtimer code later on.
+
+Note that eventually we will be initializing the timesource
+from init_early so sched_clock will work properly for
+CONFIG_PRINTK_TIME.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/timer-gp.c | 64 +++++++++++++++++++++----------------
+ arch/arm/plat-omap/counter_32k.c | 2 +-
+ 2 files changed, 37 insertions(+), 29 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index cf2ec85..2b8cb70 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -262,20 +262,22 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
+ * sync counter. See clocksource setup in plat-omap/counter_32k.c
+ */
+
+-static void __init omap2_gp_clocksource_init(void)
++static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
+ {
+ omap_init_clocksource_32k();
+ }
+
+ #else
++
++static struct omap_dm_timer clksrc;
++
+ /*
+ * clocksource
+ */
+ static DEFINE_CLOCK_DATA(cd);
+-static struct omap_dm_timer *gpt_clocksource;
+ static cycle_t clocksource_read_cycles(struct clocksource *cs)
+ {
+- return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
++ return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+ }
+
+ static struct clocksource clocksource_gpt = {
+@@ -290,43 +292,48 @@ static void notrace dmtimer_update_sched_clock(void)
+ {
+ u32 cyc;
+
+- cyc = omap_dm_timer_read_counter(gpt_clocksource);
++ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+ update_sched_clock(&cd, cyc, (u32)~0);
+ }
+
+-/* Setup free-running counter for clocksource */
+-static void __init omap2_gp_clocksource_init(void)
++unsigned long long notrace sched_clock(void)
+ {
+- static struct omap_dm_timer *gpt;
+- u32 tick_rate;
+- static char err1[] __initdata = KERN_ERR
+- "%s: failed to request dm-timer\n";
+- static char err2[] __initdata = KERN_ERR
+- "%s: can't register clocksource!\n";
++ u32 cyc = 0;
+
+- gpt = omap_dm_timer_request();
+- if (!gpt)
+- printk(err1, clocksource_gpt.name);
+- gpt_clocksource = gpt;
++ if (clksrc.reserved)
++ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+- omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
++ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
++}
++
++/* Setup free-running counter for clocksource */
++static void __init omap2_gp_clocksource_init(int gptimer_id,
++ const char *fck_source)
++{
++ int res;
++
++ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
++ BUG_ON(res);
+
+- omap_dm_timer_set_load_start(gpt, 1, 0);
++ pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
++ gptimer_id, clksrc.rate);
+
+- init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
++ __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
++ init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+
+- if (clocksource_register_hz(&clocksource_gpt, tick_rate))
+- printk(err2, clocksource_gpt.name);
++ if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
++ pr_err("Could not register clocksource %s\n",
++ clocksource_gpt.name);
+ }
+ #endif
+
+-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src) \
++#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
++ clksrc_nr, clksrc_src) \
+ static void __init omap##name##_timer_init(void) \
+ { \
+ omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+- omap2_gp_clocksource_init(); \
++ omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
+ }
+
+ #define OMAP_SYS_TIMER(name) \
+@@ -335,14 +342,15 @@ struct sys_timer omap##name##_timer = { \
+ };
+
+ #ifdef CONFIG_ARCH_OMAP2
+-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE)
++OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+ OMAP_SYS_TIMER(2)
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP3
+-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE)
++OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+ OMAP_SYS_TIMER(3)
+-OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE)
++OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
++ 2, OMAP3_MPU_SOURCE)
+ OMAP_SYS_TIMER(3_secure)
+ #endif
+
+@@ -354,7 +362,7 @@ static void __init omap4_timer_init(void)
+ BUG_ON(!twd_base);
+ #endif
+ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+- omap2_gp_clocksource_init();
++ omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+ }
+ OMAP_SYS_TIMER(4)
+ #endif
+diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
+index f7fed60..c13bc3d 100644
+--- a/arch/arm/plat-omap/counter_32k.c
++++ b/arch/arm/plat-omap/counter_32k.c
+@@ -126,7 +126,7 @@ static inline unsigned long long notrace _omap_32k_sched_clock(void)
+ return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+ }
+
+-#ifndef CONFIG_OMAP_MPU_TIMER
++#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
+ unsigned long long notrace sched_clock(void)
+ {
+ return _omap_32k_sched_clock();
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0015-omap2-Remove-omap2_gp_clockevent_set_gptimer.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0015-omap2-Remove-omap2_gp_clockevent_set_gptimer.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0015-omap2-Remove-omap2_gp_clockevent_set_gptimer.patch
@@ -0,0 +1,240 @@
+From ccf883ffc7c3bfcdf80ecb20e4015986e7b91d0e Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:49 -0700
+Subject: [PATCH 015/149] omap2+: Remove omap2_gp_clockevent_set_gptimer
+
+This is no longer needed as we now just set the desired
+.timer in MACHINE_START. We can now also remove timer-gp.h.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 4 ----
+ arch/arm/mach-omap2/board-devkit8000.c | 4 ----
+ arch/arm/mach-omap2/board-omap3beagle.c | 4 ----
+ arch/arm/mach-omap2/board-omap3logic.c | 1 -
+ arch/arm/mach-omap2/board-omap3stalker.c | 4 ----
+ arch/arm/mach-omap2/board-omap3touchbook.c | 4 ----
+ arch/arm/mach-omap2/board-omap4panda.c | 1 -
+ arch/arm/mach-omap2/timer-gp.c | 26 --------------------------
+ arch/arm/mach-omap2/timer-gp.h | 16 ----------------
+ 9 files changed, 0 insertions(+), 64 deletions(-)
+ delete mode 100644 arch/arm/mach-omap2/timer-gp.h
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index e8caced..d7df07e 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -40,7 +40,6 @@
+
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "control.h"
+ #include "common-board-devices.h"
+
+@@ -295,9 +294,6 @@ static void __init omap_4430sdp_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+-#ifdef CONFIG_OMAP_32K_TIMER
+- omap2_gp_clockevent_set_gptimer(1);
+-#endif
+ }
+
+ static struct omap_musb_board_data musb_board_data = {
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 46d144d..949dbea 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -58,7 +58,6 @@
+
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "common-board-devices.h"
+
+ #define OMAP_DM9000_GPIO_IRQ 25
+@@ -441,9 +440,6 @@ static void __init devkit8000_init_early(void)
+ static void __init devkit8000_init_irq(void)
+ {
+ omap3_init_irq();
+-#ifdef CONFIG_OMAP_32K_TIMER
+- omap2_gp_clockevent_set_gptimer(12);
+-#endif
+ }
+
+ #define OMAP_DM9000_BASE 0x2c000000
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 9ee16f6..2d8dfb3 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -50,7 +50,6 @@
+
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "pm.h"
+ #include "common-board-devices.h"
+
+@@ -484,9 +483,6 @@ static void __init omap3_beagle_init_early(void)
+ static void __init omap3_beagle_init_irq(void)
+ {
+ omap3_init_irq();
+-#ifdef CONFIG_OMAP_32K_TIMER
+- omap2_gp_clockevent_set_gptimer(12);
+-#endif
+ }
+
+ static struct platform_device *omap3_beagle_devices[] __initdata = {
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index 469259a..703aeb5 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -35,7 +35,6 @@
+
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "control.h"
+ #include "common-board-devices.h"
+
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 2fa8fae..b8ad4dd 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -52,7 +52,6 @@
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "common-board-devices.h"
+
+ #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+@@ -492,9 +491,6 @@ static void __init omap3_stalker_init_early(void)
+ static void __init omap3_stalker_init_irq(void)
+ {
+ omap3_init_irq();
+-#ifdef CONFIG_OMAP_32K_TIMER
+- omap2_gp_clockevent_set_gptimer(12);
+-#endif
+ }
+
+ static struct platform_device *omap3_stalker_devices[] __initdata = {
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 8c71fd2..57e6ed3 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -51,7 +51,6 @@
+
+ #include "mux.h"
+ #include "hsmmc.h"
+-#include "timer-gp.h"
+ #include "common-board-devices.h"
+
+ #include <asm/setup.h>
+@@ -372,9 +371,6 @@ static void __init omap3_touchbook_init_early(void)
+ static void __init omap3_touchbook_init_irq(void)
+ {
+ omap3_init_irq();
+-#ifdef CONFIG_OMAP_32K_TIMER
+- omap2_gp_clockevent_set_gptimer(12);
+-#endif
+ }
+
+ static struct platform_device *omap3_touchbook_devices[] __initdata = {
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index dc1d6dc..ee2034e 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -41,7 +41,6 @@
+ #include <plat/usb.h>
+ #include <plat/mmc.h>
+ #include <video/omap-panel-generic-dpi.h>
+-#include "timer-gp.h"
+
+ #include "hsmmc.h"
+ #include "control.h"
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 2b8cb70..ab1931c 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -43,8 +43,6 @@
+ #include <plat/common.h>
+ #include <plat/omap_hwmod.h>
+
+-#include "timer-gp.h"
+-
+ /* Parent clocks, eventually these will come from the clock framework */
+
+ #define OMAP2_MPU_SOURCE "sys_ck"
+@@ -75,8 +73,6 @@ u32 sys_timer_reserved;
+
+ static struct omap_dm_timer clkev;
+ static struct clock_event_device clockevent_gpt;
+-static u8 __initdata gptimer_id = 1;
+-static u8 __initdata inited;
+
+ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+ {
+@@ -138,26 +134,6 @@ static struct clock_event_device clockevent_gpt = {
+ .set_mode = omap2_gp_timer_set_mode,
+ };
+
+-/**
+- * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
+- * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
+- *
+- * Define the GPTIMER that the system should use for the tick timer.
+- * Meant to be called from board-*.c files in the event that GPTIMER1, the
+- * default, is unsuitable. Returns -EINVAL on error or 0 on success.
+- */
+-int __init omap2_gp_clockevent_set_gptimer(u8 id)
+-{
+- if (id < 1 || id > MAX_GPTIMER_ID)
+- return -EINVAL;
+-
+- BUG_ON(inited);
+-
+- gptimer_id = id;
+-
+- return 0;
+-}
+-
+ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+ int gptimer_id,
+ const char *fck_source)
+@@ -228,8 +204,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
+ {
+ int res;
+
+- inited = 1;
+-
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+ BUG_ON(res);
+
+diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
+deleted file mode 100644
+index 5c1072c..0000000
+--- a/arch/arm/mach-omap2/timer-gp.h
++++ /dev/null
+@@ -1,16 +0,0 @@
+-/*
+- * OMAP2/3 GPTIMER support.headers
+- *
+- * Copyright (C) 2009 Nokia Corporation
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file "COPYING" in the main directory of this archive
+- * for more details.
+- */
+-
+-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+-
+-extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
+-
+-#endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0016-omap2-Rename-timer-gp.c-into-timer.c-to-combine-time.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0016-omap2-Rename-timer-gp.c-into-timer.c-to-combine-time.patch
--- /dev/null
@@ -0,0 +1,737 @@
+From e8ffcfc15d3d23b8bb3e96a7cf6e4147645c4b9a Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Tue, 29 Mar 2011 15:54:50 -0700
+Subject: [PATCH 016/149] omap2+: Rename timer-gp.c into timer.c to combine timer init functions
+
+We can keep everything sys_timer and gptimer.c related code in
+timer.c as the code will be very minimal.
+
+Later on we can also remove timer-mpu.c, as it can be called from
+omap4_timer_init function.
+
+This allows us to get rid of confusing existing files. We currently
+have timer-gp.c, timer-mpu.c, and patches have been posted to add
+dmtimer.c. There's no need to have these multiple files, we can
+put everything into timer.c.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/timer-gp.c | 342 ----------------------------------------
+ arch/arm/mach-omap2/timer.c | 342 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 343 insertions(+), 343 deletions(-)
+ delete mode 100644 arch/arm/mach-omap2/timer-gp.c
+ create mode 100644 arch/arm/mach-omap2/timer.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index b148077..adbe82d 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -3,7 +3,7 @@
+ #
+
+ # Common support
+-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
++obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
+ common.o gpio.o dma.o wd_timer.o
+
+ omap-2-3-common = irq.o sdrc.o
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+deleted file mode 100644
+index ab1931c..0000000
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ /dev/null
+@@ -1,342 +0,0 @@
+-/*
+- * linux/arch/arm/mach-omap2/timer-gp.c
+- *
+- * OMAP2 GP timer support.
+- *
+- * Copyright (C) 2009 Nokia Corporation
+- *
+- * Update to use new clocksource/clockevent layers
+- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+- * Copyright (C) 2007 MontaVista Software, Inc.
+- *
+- * Original driver:
+- * Copyright (C) 2005 Nokia Corporation
+- * Author: Paul Mundt <paul.mundt@nokia.com>
+- * Juha Yrjölä <juha.yrjola@nokia.com>
+- * OMAP Dual-mode timer framework support by Timo Teras
+- *
+- * Some parts based off of TI's 24xx code:
+- *
+- * Copyright (C) 2004-2009 Texas Instruments, Inc.
+- *
+- * Roughly modelled after the OMAP1 MPU timer code.
+- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file "COPYING" in the main directory of this archive
+- * for more details.
+- */
+-#include <linux/init.h>
+-#include <linux/time.h>
+-#include <linux/interrupt.h>
+-#include <linux/err.h>
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <linux/irq.h>
+-#include <linux/clocksource.h>
+-#include <linux/clockchips.h>
+-
+-#include <asm/mach/time.h>
+-#include <plat/dmtimer.h>
+-#include <asm/localtimer.h>
+-#include <asm/sched_clock.h>
+-#include <plat/common.h>
+-#include <plat/omap_hwmod.h>
+-
+-/* Parent clocks, eventually these will come from the clock framework */
+-
+-#define OMAP2_MPU_SOURCE "sys_ck"
+-#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
+-#define OMAP4_MPU_SOURCE "sys_clkin_ck"
+-#define OMAP2_32K_SOURCE "func_32k_ck"
+-#define OMAP3_32K_SOURCE "omap_32k_fck"
+-#define OMAP4_32K_SOURCE "sys_32k_ck"
+-
+-#ifdef CONFIG_OMAP_32K_TIMER
+-#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
+-#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
+-#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
+-#define OMAP3_SECURE_TIMER 12
+-#else
+-#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
+-#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
+-#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
+-#define OMAP3_SECURE_TIMER 1
+-#endif
+-
+-/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+-#define MAX_GPTIMER_ID 12
+-
+-u32 sys_timer_reserved;
+-
+-/* Clockevent code */
+-
+-static struct omap_dm_timer clkev;
+-static struct clock_event_device clockevent_gpt;
+-
+-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+-{
+- struct clock_event_device *evt = &clockevent_gpt;
+-
+- __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+-
+- evt->event_handler(evt);
+- return IRQ_HANDLED;
+-}
+-
+-static struct irqaction omap2_gp_timer_irq = {
+- .name = "gp timer",
+- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+- .handler = omap2_gp_timer_interrupt,
+-};
+-
+-static int omap2_gp_timer_set_next_event(unsigned long cycles,
+- struct clock_event_device *evt)
+-{
+- __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
+- 0xffffffff - cycles, 1);
+-
+- return 0;
+-}
+-
+-static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+- struct clock_event_device *evt)
+-{
+- u32 period;
+-
+- __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+-
+- switch (mode) {
+- case CLOCK_EVT_MODE_PERIODIC:
+- period = clkev.rate / HZ;
+- period -= 1;
+- /* Looks like we need to first set the load value separately */
+- __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
+- 0xffffffff - period, 1);
+- __omap_dm_timer_load_start(clkev.io_base,
+- OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+- 0xffffffff - period, 1);
+- break;
+- case CLOCK_EVT_MODE_ONESHOT:
+- break;
+- case CLOCK_EVT_MODE_UNUSED:
+- case CLOCK_EVT_MODE_SHUTDOWN:
+- case CLOCK_EVT_MODE_RESUME:
+- break;
+- }
+-}
+-
+-static struct clock_event_device clockevent_gpt = {
+- .name = "gp timer",
+- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+- .shift = 32,
+- .set_next_event = omap2_gp_timer_set_next_event,
+- .set_mode = omap2_gp_timer_set_mode,
+-};
+-
+-static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+- int gptimer_id,
+- const char *fck_source)
+-{
+- char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+- struct omap_hwmod *oh;
+- size_t size;
+- int res = 0;
+-
+- sprintf(name, "timer%d", gptimer_id);
+- omap_hwmod_setup_one(name);
+- oh = omap_hwmod_lookup(name);
+- if (!oh)
+- return -ENODEV;
+-
+- timer->irq = oh->mpu_irqs[0].irq;
+- timer->phys_base = oh->slaves[0]->addr->pa_start;
+- size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+-
+- /* Static mapping, never released */
+- timer->io_base = ioremap(timer->phys_base, size);
+- if (!timer->io_base)
+- return -ENXIO;
+-
+- /* After the dmtimer is using hwmod these clocks won't be needed */
+- sprintf(name, "gpt%d_fck", gptimer_id);
+- timer->fclk = clk_get(NULL, name);
+- if (IS_ERR(timer->fclk))
+- return -ENODEV;
+-
+- sprintf(name, "gpt%d_ick", gptimer_id);
+- timer->iclk = clk_get(NULL, name);
+- if (IS_ERR(timer->iclk)) {
+- clk_put(timer->fclk);
+- return -ENODEV;
+- }
+-
+- omap_hwmod_enable(oh);
+-
+- sys_timer_reserved |= (1 << (gptimer_id - 1));
+-
+- if (gptimer_id != 12) {
+- struct clk *src;
+-
+- src = clk_get(NULL, fck_source);
+- if (IS_ERR(src)) {
+- res = -EINVAL;
+- } else {
+- res = __omap_dm_timer_set_source(timer->fclk, src);
+- if (IS_ERR_VALUE(res))
+- pr_warning("%s: timer%i cannot set source\n",
+- __func__, gptimer_id);
+- clk_put(src);
+- }
+- }
+- __omap_dm_timer_reset(timer->io_base, 1, 1);
+- timer->posted = 1;
+-
+- timer->rate = clk_get_rate(timer->fclk);
+-
+- timer->reserved = 1;
+-
+- return res;
+-}
+-
+-static void __init omap2_gp_clockevent_init(int gptimer_id,
+- const char *fck_source)
+-{
+- int res;
+-
+- res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+- BUG_ON(res);
+-
+- omap2_gp_timer_irq.dev_id = (void *)&clkev;
+- setup_irq(clkev.irq, &omap2_gp_timer_irq);
+-
+- __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+-
+- clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
+- clockevent_gpt.shift);
+- clockevent_gpt.max_delta_ns =
+- clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+- clockevent_gpt.min_delta_ns =
+- clockevent_delta2ns(3, &clockevent_gpt);
+- /* Timer internal resynch latency. */
+-
+- clockevent_gpt.cpumask = cpumask_of(0);
+- clockevents_register_device(&clockevent_gpt);
+-
+- pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
+- gptimer_id, clkev.rate);
+-}
+-
+-/* Clocksource code */
+-
+-#ifdef CONFIG_OMAP_32K_TIMER
+-/*
+- * When 32k-timer is enabled, don't use GPTimer for clocksource
+- * instead, just leave default clocksource which uses the 32k
+- * sync counter. See clocksource setup in plat-omap/counter_32k.c
+- */
+-
+-static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
+-{
+- omap_init_clocksource_32k();
+-}
+-
+-#else
+-
+-static struct omap_dm_timer clksrc;
+-
+-/*
+- * clocksource
+- */
+-static DEFINE_CLOCK_DATA(cd);
+-static cycle_t clocksource_read_cycles(struct clocksource *cs)
+-{
+- return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+-}
+-
+-static struct clocksource clocksource_gpt = {
+- .name = "gp timer",
+- .rating = 300,
+- .read = clocksource_read_cycles,
+- .mask = CLOCKSOURCE_MASK(32),
+- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+-};
+-
+-static void notrace dmtimer_update_sched_clock(void)
+-{
+- u32 cyc;
+-
+- cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+-
+- update_sched_clock(&cd, cyc, (u32)~0);
+-}
+-
+-unsigned long long notrace sched_clock(void)
+-{
+- u32 cyc = 0;
+-
+- if (clksrc.reserved)
+- cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+-
+- return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+-}
+-
+-/* Setup free-running counter for clocksource */
+-static void __init omap2_gp_clocksource_init(int gptimer_id,
+- const char *fck_source)
+-{
+- int res;
+-
+- res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+- BUG_ON(res);
+-
+- pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+- gptimer_id, clksrc.rate);
+-
+- __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
+- init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+-
+- if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
+- pr_err("Could not register clocksource %s\n",
+- clocksource_gpt.name);
+-}
+-#endif
+-
+-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
+- clksrc_nr, clksrc_src) \
+-static void __init omap##name##_timer_init(void) \
+-{ \
+- omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+- omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
+-}
+-
+-#define OMAP_SYS_TIMER(name) \
+-struct sys_timer omap##name##_timer = { \
+- .init = omap##name##_timer_init, \
+-};
+-
+-#ifdef CONFIG_ARCH_OMAP2
+-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+-OMAP_SYS_TIMER(2)
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP3
+-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+-OMAP_SYS_TIMER(3)
+-OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
+- 2, OMAP3_MPU_SOURCE)
+-OMAP_SYS_TIMER(3_secure)
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP4
+-static void __init omap4_timer_init(void)
+-{
+-#ifdef CONFIG_LOCAL_TIMERS
+- twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+- BUG_ON(!twd_base);
+-#endif
+- omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+- omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+-}
+-OMAP_SYS_TIMER(4)
+-#endif
+diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
+new file mode 100644
+index 0000000..e964072
+--- /dev/null
++++ b/arch/arm/mach-omap2/timer.c
+@@ -0,0 +1,342 @@
++/*
++ * linux/arch/arm/mach-omap2/timer.c
++ *
++ * OMAP2 GP timer support.
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ *
++ * Update to use new clocksource/clockevent layers
++ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
++ * Copyright (C) 2007 MontaVista Software, Inc.
++ *
++ * Original driver:
++ * Copyright (C) 2005 Nokia Corporation
++ * Author: Paul Mundt <paul.mundt@nokia.com>
++ * Juha Yrjölä <juha.yrjola@nokia.com>
++ * OMAP Dual-mode timer framework support by Timo Teras
++ *
++ * Some parts based off of TI's 24xx code:
++ *
++ * Copyright (C) 2004-2009 Texas Instruments, Inc.
++ *
++ * Roughly modelled after the OMAP1 MPU timer code.
++ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ */
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/irq.h>
++#include <linux/clocksource.h>
++#include <linux/clockchips.h>
++
++#include <asm/mach/time.h>
++#include <plat/dmtimer.h>
++#include <asm/localtimer.h>
++#include <asm/sched_clock.h>
++#include <plat/common.h>
++#include <plat/omap_hwmod.h>
++
++/* Parent clocks, eventually these will come from the clock framework */
++
++#define OMAP2_MPU_SOURCE "sys_ck"
++#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
++#define OMAP4_MPU_SOURCE "sys_clkin_ck"
++#define OMAP2_32K_SOURCE "func_32k_ck"
++#define OMAP3_32K_SOURCE "omap_32k_fck"
++#define OMAP4_32K_SOURCE "sys_32k_ck"
++
++#ifdef CONFIG_OMAP_32K_TIMER
++#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
++#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
++#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
++#define OMAP3_SECURE_TIMER 12
++#else
++#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
++#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
++#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
++#define OMAP3_SECURE_TIMER 1
++#endif
++
++/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
++#define MAX_GPTIMER_ID 12
++
++u32 sys_timer_reserved;
++
++/* Clockevent code */
++
++static struct omap_dm_timer clkev;
++static struct clock_event_device clockevent_gpt;
++
++static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
++{
++ struct clock_event_device *evt = &clockevent_gpt;
++
++ __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
++
++ evt->event_handler(evt);
++ return IRQ_HANDLED;
++}
++
++static struct irqaction omap2_gp_timer_irq = {
++ .name = "gp timer",
++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = omap2_gp_timer_interrupt,
++};
++
++static int omap2_gp_timer_set_next_event(unsigned long cycles,
++ struct clock_event_device *evt)
++{
++ __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
++ 0xffffffff - cycles, 1);
++
++ return 0;
++}
++
++static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
++ struct clock_event_device *evt)
++{
++ u32 period;
++
++ __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
++
++ switch (mode) {
++ case CLOCK_EVT_MODE_PERIODIC:
++ period = clkev.rate / HZ;
++ period -= 1;
++ /* Looks like we need to first set the load value separately */
++ __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
++ 0xffffffff - period, 1);
++ __omap_dm_timer_load_start(clkev.io_base,
++ OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
++ 0xffffffff - period, 1);
++ break;
++ case CLOCK_EVT_MODE_ONESHOT:
++ break;
++ case CLOCK_EVT_MODE_UNUSED:
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ case CLOCK_EVT_MODE_RESUME:
++ break;
++ }
++}
++
++static struct clock_event_device clockevent_gpt = {
++ .name = "gp timer",
++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
++ .shift = 32,
++ .set_next_event = omap2_gp_timer_set_next_event,
++ .set_mode = omap2_gp_timer_set_mode,
++};
++
++static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
++ int gptimer_id,
++ const char *fck_source)
++{
++ char name[10]; /* 10 = sizeof("gptXX_Xck0") */
++ struct omap_hwmod *oh;
++ size_t size;
++ int res = 0;
++
++ sprintf(name, "timer%d", gptimer_id);
++ omap_hwmod_setup_one(name);
++ oh = omap_hwmod_lookup(name);
++ if (!oh)
++ return -ENODEV;
++
++ timer->irq = oh->mpu_irqs[0].irq;
++ timer->phys_base = oh->slaves[0]->addr->pa_start;
++ size = oh->slaves[0]->addr->pa_end - timer->phys_base;
++
++ /* Static mapping, never released */
++ timer->io_base = ioremap(timer->phys_base, size);
++ if (!timer->io_base)
++ return -ENXIO;
++
++ /* After the dmtimer is using hwmod these clocks won't be needed */
++ sprintf(name, "gpt%d_fck", gptimer_id);
++ timer->fclk = clk_get(NULL, name);
++ if (IS_ERR(timer->fclk))
++ return -ENODEV;
++
++ sprintf(name, "gpt%d_ick", gptimer_id);
++ timer->iclk = clk_get(NULL, name);
++ if (IS_ERR(timer->iclk)) {
++ clk_put(timer->fclk);
++ return -ENODEV;
++ }
++
++ omap_hwmod_enable(oh);
++
++ sys_timer_reserved |= (1 << (gptimer_id - 1));
++
++ if (gptimer_id != 12) {
++ struct clk *src;
++
++ src = clk_get(NULL, fck_source);
++ if (IS_ERR(src)) {
++ res = -EINVAL;
++ } else {
++ res = __omap_dm_timer_set_source(timer->fclk, src);
++ if (IS_ERR_VALUE(res))
++ pr_warning("%s: timer%i cannot set source\n",
++ __func__, gptimer_id);
++ clk_put(src);
++ }
++ }
++ __omap_dm_timer_reset(timer->io_base, 1, 1);
++ timer->posted = 1;
++
++ timer->rate = clk_get_rate(timer->fclk);
++
++ timer->reserved = 1;
++
++ return res;
++}
++
++static void __init omap2_gp_clockevent_init(int gptimer_id,
++ const char *fck_source)
++{
++ int res;
++
++ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
++ BUG_ON(res);
++
++ omap2_gp_timer_irq.dev_id = (void *)&clkev;
++ setup_irq(clkev.irq, &omap2_gp_timer_irq);
++
++ __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
++
++ clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
++ clockevent_gpt.shift);
++ clockevent_gpt.max_delta_ns =
++ clockevent_delta2ns(0xffffffff, &clockevent_gpt);
++ clockevent_gpt.min_delta_ns =
++ clockevent_delta2ns(3, &clockevent_gpt);
++ /* Timer internal resynch latency. */
++
++ clockevent_gpt.cpumask = cpumask_of(0);
++ clockevents_register_device(&clockevent_gpt);
++
++ pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
++ gptimer_id, clkev.rate);
++}
++
++/* Clocksource code */
++
++#ifdef CONFIG_OMAP_32K_TIMER
++/*
++ * When 32k-timer is enabled, don't use GPTimer for clocksource
++ * instead, just leave default clocksource which uses the 32k
++ * sync counter. See clocksource setup in plat-omap/counter_32k.c
++ */
++
++static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
++{
++ omap_init_clocksource_32k();
++}
++
++#else
++
++static struct omap_dm_timer clksrc;
++
++/*
++ * clocksource
++ */
++static DEFINE_CLOCK_DATA(cd);
++static cycle_t clocksource_read_cycles(struct clocksource *cs)
++{
++ return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
++}
++
++static struct clocksource clocksource_gpt = {
++ .name = "gp timer",
++ .rating = 300,
++ .read = clocksource_read_cycles,
++ .mask = CLOCKSOURCE_MASK(32),
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++static void notrace dmtimer_update_sched_clock(void)
++{
++ u32 cyc;
++
++ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
++
++ update_sched_clock(&cd, cyc, (u32)~0);
++}
++
++unsigned long long notrace sched_clock(void)
++{
++ u32 cyc = 0;
++
++ if (clksrc.reserved)
++ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
++
++ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
++}
++
++/* Setup free-running counter for clocksource */
++static void __init omap2_gp_clocksource_init(int gptimer_id,
++ const char *fck_source)
++{
++ int res;
++
++ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
++ BUG_ON(res);
++
++ pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
++ gptimer_id, clksrc.rate);
++
++ __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
++ init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
++
++ if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
++ pr_err("Could not register clocksource %s\n",
++ clocksource_gpt.name);
++}
++#endif
++
++#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
++ clksrc_nr, clksrc_src) \
++static void __init omap##name##_timer_init(void) \
++{ \
++ omap2_gp_clockevent_init((clkev_nr), clkev_src); \
++ omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
++}
++
++#define OMAP_SYS_TIMER(name) \
++struct sys_timer omap##name##_timer = { \
++ .init = omap##name##_timer_init, \
++};
++
++#ifdef CONFIG_ARCH_OMAP2
++OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
++OMAP_SYS_TIMER(2)
++#endif
++
++#ifdef CONFIG_ARCH_OMAP3
++OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
++OMAP_SYS_TIMER(3)
++OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
++ 2, OMAP3_MPU_SOURCE)
++OMAP_SYS_TIMER(3_secure)
++#endif
++
++#ifdef CONFIG_ARCH_OMAP4
++static void __init omap4_timer_init(void)
++{
++#ifdef CONFIG_LOCAL_TIMERS
++ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
++ BUG_ON(!twd_base);
++#endif
++ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
++ omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
++}
++OMAP_SYS_TIMER(4)
++#endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0017-omap-cleanup-NAND-platform-data.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0017-omap-cleanup-NAND-platform-data.patch
--- /dev/null
@@ -0,0 +1,165 @@
+From 1fb8bf12fc634685ecf9225c6d22823dbab5464b Mon Sep 17 00:00:00 2001
+From: Grazvydas Ignotas <notasas@gmail.com>
+Date: Fri, 3 Jun 2011 19:56:33 +0000
+Subject: [PATCH 017/149] omap: cleanup NAND platform data
+
+omap_nand_platform_data fields 'options', 'gpio_irq', 'nand_setup' and
+'dma_channel' are never referenced by the NAND driver, yet various
+board files are initializing those fields. This is both incorrect and
+confusing, so remove them. This allows to get rid of a global
+variable in gpmc-nand.c.
+
+This also corrects an issue where some boards are trying to pass NAND
+16bit flag through .options, but the driver is using .devsize instead
+and ignoring .options.
+
+Finally, .dev_ready is treated as a flag by the driver, so make it bool
+instead of a function pointer.
+
+Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-cm-t35.c | 2 --
+ arch/arm/mach-omap2/board-cm-t3517.c | 1 -
+ arch/arm/mach-omap2/board-flash.c | 4 ----
+ arch/arm/mach-omap2/common-board-devices.c | 6 ++----
+ arch/arm/mach-omap2/gpmc-nand.c | 10 +++-------
+ arch/arm/plat-omap/include/plat/nand.h | 6 +-----
+ 6 files changed, 6 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 1a18d3b..d76dca7 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -162,9 +162,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
+ static struct omap_nand_platform_data cm_t35_nand_data = {
+ .parts = cm_t35_nand_partitions,
+ .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
+- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+ .cs = 0,
+-
+ };
+
+ static void __init cm_t35_init_nand(void)
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index aa67240..05c72f4 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
+ static struct omap_nand_platform_data cm_t3517_nand_data = {
+ .parts = cm_t3517_nand_partitions,
+ .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
+- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+ .cs = 0,
+ };
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index 729892f..aa1b0cb 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
+ };
+
+ static struct omap_nand_platform_data board_nand_data = {
+- .nand_setup = NULL,
+ .gpmc_t = &nand_timings,
+- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+- .dev_ready = NULL,
+- .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
+ };
+
+ void
+diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
+index 94ccf46..0043fa8 100644
+--- a/arch/arm/mach-omap2/common-board-devices.c
++++ b/arch/arm/mach-omap2/common-board-devices.c
+@@ -115,9 +115,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+ #endif
+
+ #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+-static struct omap_nand_platform_data nand_data = {
+- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+-};
++static struct omap_nand_platform_data nand_data;
+
+ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+ int nr_parts)
+@@ -148,7 +146,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+ nand_data.cs = nandcs;
+ nand_data.parts = parts;
+ nand_data.nr_parts = nr_parts;
+- nand_data.options = options;
++ nand_data.devsize = options;
+
+ printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+ if (gpmc_nand_init(&nand_data) < 0)
+diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
+index c1791d0..8ad210b 100644
+--- a/arch/arm/mach-omap2/gpmc-nand.c
++++ b/arch/arm/mach-omap2/gpmc-nand.c
+@@ -20,8 +20,6 @@
+ #include <plat/board.h>
+ #include <plat/gpmc.h>
+
+-static struct omap_nand_platform_data *gpmc_nand_data;
+-
+ static struct resource gpmc_nand_resource = {
+ .flags = IORESOURCE_MEM,
+ };
+@@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
+ .resource = &gpmc_nand_resource,
+ };
+
+-static int omap2_nand_gpmc_retime(void)
++static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
+ {
+ struct gpmc_timings t;
+ int err;
+@@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
+ return 0;
+ }
+
+-int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
++int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+ {
+ int err = 0;
+ struct device *dev = &gpmc_nand_device.dev;
+
+- gpmc_nand_data = _nand_data;
+- gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
+ gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+
+ err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
+@@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
+ }
+
+ /* Set timings in GPMC */
+- err = omap2_nand_gpmc_retime();
++ err = omap2_nand_gpmc_retime(gpmc_nand_data);
+ if (err < 0) {
+ dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+ return err;
+diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
+index d86d1ec..67fc506 100644
+--- a/arch/arm/plat-omap/include/plat/nand.h
++++ b/arch/arm/plat-omap/include/plat/nand.h
+@@ -19,15 +19,11 @@ enum nand_io {
+ };
+
+ struct omap_nand_platform_data {
+- unsigned int options;
+ int cs;
+- int gpio_irq;
+ struct mtd_partition *parts;
+ struct gpmc_timings *gpmc_t;
+ int nr_parts;
+- int (*nand_setup)(void);
+- int (*dev_ready)(struct omap_nand_platform_data *);
+- int dma_channel;
++ bool dev_ready;
+ int gpmc_irq;
+ enum nand_io xfer_type;
+ unsigned long phys_base;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0018-omap-board-omap3evm-Fix-compilation-error.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0018-omap-board-omap3evm-Fix-compilation-error.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0018-omap-board-omap3evm-Fix-compilation-error.patch
@@ -0,0 +1,40 @@
+From 59a54033e4f7c06fa47a7e0a81f8f35a10a362b0 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Tue, 28 Jun 2011 10:16:55 +0000
+Subject: [PATCH 018/149] omap: board-omap3evm: Fix compilation error
+
+Fix compilation error introduced with 786b01a8c1db0c0decca55d660a2a3ebd7cfb26b
+(cleanup regulator supply definitions in mach-omap2).
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+[tony@atomide.com: updated comments]
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 6f957ed..57bce0f 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -510,7 +510,7 @@ static struct regulator_init_data omap3evm_vio = {
+ #define OMAP3EVM_WLAN_IRQ_GPIO (149)
+
+ static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+ /* VMMC2 for driving the WL12xx module */
+@@ -518,7 +518,7 @@ static struct regulator_init_data omap3evm_vmmc2 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply);,
++ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
+ .consumer_supplies = omap3evm_vmmc2_supply,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0019-omap-mcbsp-Drop-SPI-mode-support.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0019-omap-mcbsp-Drop-SPI-mode-support.patch
--- /dev/null
@@ -0,0 +1,311 @@
+From 4e3c37e5871f6ef060ad32c23d5c0300641cb6ac Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jhnikula@gmail.com>
+Date: Tue, 14 Jun 2011 11:23:51 +0000
+Subject: [PATCH 019/149] omap: mcbsp: Drop SPI mode support
+
+We haven't seen any use for the SPI API in McBSP driver over the years. More
+over, Peter Ujfalusi <peter.ujfalusi@ti.com> noticed that SPI mode is not
+even supported since OMAP2430 so it's very unlikely that we'll see any use
+for it in the future either.
+
+Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/mcbsp.h | 37 ------
+ arch/arm/plat-omap/mcbsp.c | 214 -------------------------------
+ 2 files changed, 0 insertions(+), 251 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index f8f690a..3fc75a8 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -353,38 +353,6 @@ typedef enum {
+ OMAP_MCBSP_WORD_32,
+ } omap_mcbsp_word_length;
+
+-typedef enum {
+- OMAP_MCBSP_CLK_RISING = 0,
+- OMAP_MCBSP_CLK_FALLING,
+-} omap_mcbsp_clk_polarity;
+-
+-typedef enum {
+- OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
+- OMAP_MCBSP_FS_ACTIVE_LOW,
+-} omap_mcbsp_fs_polarity;
+-
+-typedef enum {
+- OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
+- OMAP_MCBSP_CLK_STP_MODE_DELAY,
+-} omap_mcbsp_clk_stp_mode;
+-
+-
+-/******* SPI specific mode **********/
+-typedef enum {
+- OMAP_MCBSP_SPI_MASTER = 0,
+- OMAP_MCBSP_SPI_SLAVE,
+-} omap_mcbsp_spi_mode;
+-
+-struct omap_mcbsp_spi_cfg {
+- omap_mcbsp_spi_mode spi_mode;
+- omap_mcbsp_clk_polarity rx_clock_polarity;
+- omap_mcbsp_clk_polarity tx_clock_polarity;
+- omap_mcbsp_fs_polarity fsx_polarity;
+- u8 clk_div;
+- omap_mcbsp_clk_stp_mode clk_stp_mode;
+- omap_mcbsp_word_length word_length;
+-};
+-
+ /* Platform specific configuration */
+ struct omap_mcbsp_ops {
+ void (*request)(unsigned int);
+@@ -504,14 +472,9 @@ u32 omap_mcbsp_recv_word(unsigned int id);
+
+ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
+-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
+-
+
+ /* McBSP functional clock source changing function */
+ extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
+-/* SPI specific API */
+-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
+
+ /* Polled read/write functions */
+ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 5587acf..1de2724 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -1175,147 +1175,6 @@ u32 omap_mcbsp_recv_word(unsigned int id)
+ }
+ EXPORT_SYMBOL(omap_mcbsp_recv_word);
+
+-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
+-{
+- struct omap_mcbsp *mcbsp;
+- omap_mcbsp_word_length tx_word_length;
+- omap_mcbsp_word_length rx_word_length;
+- u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+- tx_word_length = mcbsp->tx_word_length;
+- rx_word_length = mcbsp->rx_word_length;
+-
+- if (tx_word_length != rx_word_length)
+- return -EINVAL;
+-
+- /* First we wait for the transmitter to be ready */
+- spcr2 = MCBSP_READ(mcbsp, SPCR2);
+- while (!(spcr2 & XRDY)) {
+- spcr2 = MCBSP_READ(mcbsp, SPCR2);
+- if (attempts++ > 1000) {
+- /* We must reset the transmitter */
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
+- udelay(10);
+- dev_err(mcbsp->dev, "McBSP%d transmitter not "
+- "ready\n", mcbsp->id);
+- return -EAGAIN;
+- }
+- }
+-
+- /* Now we can push the data */
+- if (tx_word_length > OMAP_MCBSP_WORD_16)
+- MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+- MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
+-
+- /* We wait for the receiver to be ready */
+- spcr1 = MCBSP_READ(mcbsp, SPCR1);
+- while (!(spcr1 & RRDY)) {
+- spcr1 = MCBSP_READ(mcbsp, SPCR1);
+- if (attempts++ > 1000) {
+- /* We must reset the receiver */
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
+- udelay(10);
+- dev_err(mcbsp->dev, "McBSP%d receiver not "
+- "ready\n", mcbsp->id);
+- return -EAGAIN;
+- }
+- }
+-
+- /* Receiver is ready, let's read the dummy data */
+- if (rx_word_length > OMAP_MCBSP_WORD_16)
+- word_msb = MCBSP_READ(mcbsp, DRR2);
+- word_lsb = MCBSP_READ(mcbsp, DRR1);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
+-
+-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
+-{
+- struct omap_mcbsp *mcbsp;
+- u32 clock_word = 0;
+- omap_mcbsp_word_length tx_word_length;
+- omap_mcbsp_word_length rx_word_length;
+- u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+-
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- tx_word_length = mcbsp->tx_word_length;
+- rx_word_length = mcbsp->rx_word_length;
+-
+- if (tx_word_length != rx_word_length)
+- return -EINVAL;
+-
+- /* First we wait for the transmitter to be ready */
+- spcr2 = MCBSP_READ(mcbsp, SPCR2);
+- while (!(spcr2 & XRDY)) {
+- spcr2 = MCBSP_READ(mcbsp, SPCR2);
+- if (attempts++ > 1000) {
+- /* We must reset the transmitter */
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
+- udelay(10);
+- dev_err(mcbsp->dev, "McBSP%d transmitter not "
+- "ready\n", mcbsp->id);
+- return -EAGAIN;
+- }
+- }
+-
+- /* We first need to enable the bus clock */
+- if (tx_word_length > OMAP_MCBSP_WORD_16)
+- MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
+- MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
+-
+- /* We wait for the receiver to be ready */
+- spcr1 = MCBSP_READ(mcbsp, SPCR1);
+- while (!(spcr1 & RRDY)) {
+- spcr1 = MCBSP_READ(mcbsp, SPCR1);
+- if (attempts++ > 1000) {
+- /* We must reset the receiver */
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
+- udelay(10);
+- dev_err(mcbsp->dev, "McBSP%d receiver not "
+- "ready\n", mcbsp->id);
+- return -EAGAIN;
+- }
+- }
+-
+- /* Receiver is ready, there is something for us */
+- if (rx_word_length > OMAP_MCBSP_WORD_16)
+- word_msb = MCBSP_READ(mcbsp, DRR2);
+- word_lsb = MCBSP_READ(mcbsp, DRR1);
+-
+- word[0] = (word_lsb | (word_msb << 16));
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
+-
+ /*
+ * Simple DMA based buffer rx/tx routines.
+ * Nothing fancy, just a single buffer tx/rx through DMA.
+@@ -1449,79 +1308,6 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+ }
+ EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
+
+-/*
+- * SPI wrapper.
+- * Since SPI setup is much simpler than the generic McBSP one,
+- * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
+- * Once this is done, you can call omap_mcbsp_start().
+- */
+-void omap_mcbsp_set_spi_mode(unsigned int id,
+- const struct omap_mcbsp_spi_cfg *spi_cfg)
+-{
+- struct omap_mcbsp *mcbsp;
+- struct omap_mcbsp_reg_cfg mcbsp_cfg;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
+-
+- /* SPI has only one frame */
+- mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
+- mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
+-
+- /* Clock stop mode */
+- if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
+- mcbsp_cfg.spcr1 |= (1 << 12);
+- else
+- mcbsp_cfg.spcr1 |= (3 << 11);
+-
+- /* Set clock parities */
+- if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+- mcbsp_cfg.pcr0 |= CLKRP;
+- else
+- mcbsp_cfg.pcr0 &= ~CLKRP;
+-
+- if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+- mcbsp_cfg.pcr0 &= ~CLKXP;
+- else
+- mcbsp_cfg.pcr0 |= CLKXP;
+-
+- /* Set SCLKME to 0 and CLKSM to 1 */
+- mcbsp_cfg.pcr0 &= ~SCLKME;
+- mcbsp_cfg.srgr2 |= CLKSM;
+-
+- /* Set FSXP */
+- if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
+- mcbsp_cfg.pcr0 &= ~FSXP;
+- else
+- mcbsp_cfg.pcr0 |= FSXP;
+-
+- if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
+- mcbsp_cfg.pcr0 |= CLKXM;
+- mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
+- mcbsp_cfg.pcr0 |= FSXM;
+- mcbsp_cfg.srgr2 &= ~FSGM;
+- mcbsp_cfg.xcr2 |= XDATDLY(1);
+- mcbsp_cfg.rcr2 |= RDATDLY(1);
+- } else {
+- mcbsp_cfg.pcr0 &= ~CLKXM;
+- mcbsp_cfg.srgr1 |= CLKGDV(1);
+- mcbsp_cfg.pcr0 &= ~FSXM;
+- mcbsp_cfg.xcr2 &= ~XDATDLY(3);
+- mcbsp_cfg.rcr2 &= ~RDATDLY(3);
+- }
+-
+- mcbsp_cfg.xcr2 &= ~XPHASE;
+- mcbsp_cfg.rcr2 &= ~RPHASE;
+-
+- omap_mcbsp_config(id, &mcbsp_cfg);
+-}
+-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
+-
+ #ifdef CONFIG_ARCH_OMAP3
+ #define max_thres(m) (mcbsp->pdata->buffer_size)
+ #define valid_threshold(m, val) ((val) <= max_thres(m))
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0020-omap-mcbsp-Drop-in-driver-transfer-support.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0020-omap-mcbsp-Drop-in-driver-transfer-support.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0020-omap-mcbsp-Drop-in-driver-transfer-support.patch
@@ -0,0 +1,548 @@
+From b3e109513b7cfc01b0e8b1acb6d586f0d273303a Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jhnikula@gmail.com>
+Date: Tue, 14 Jun 2011 11:23:52 +0000
+Subject: [PATCH 020/149] omap: mcbsp: Drop in-driver transfer support
+
+We haven't seen either use for in-driver transfer API in McBSP driver
+over the years so it looks they can be removed too.
+
+Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/mcbsp.h | 25 --
+ arch/arm/plat-omap/mcbsp.c | 382 ++-----------------------------
+ 2 files changed, 19 insertions(+), 388 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 3fc75a8..6c53508 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -24,7 +24,6 @@
+ #ifndef __ASM_ARCH_OMAP_MCBSP_H
+ #define __ASM_ARCH_OMAP_MCBSP_H
+
+-#include <linux/completion.h>
+ #include <linux/spinlock.h>
+
+ #include <mach/hardware.h>
+@@ -340,10 +339,6 @@ typedef enum {
+ OMAP_MCBSP5
+ } omap_mcbsp_id;
+
+-typedef int __bitwise omap_mcbsp_io_type_t;
+-#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
+-#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
+-
+ typedef enum {
+ OMAP_MCBSP_WORD_8 = 0,
+ OMAP_MCBSP_WORD_12,
+@@ -393,22 +388,12 @@ struct omap_mcbsp {
+ omap_mcbsp_word_length rx_word_length;
+ omap_mcbsp_word_length tx_word_length;
+
+- omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+- /* IRQ based TX/RX */
+ int rx_irq;
+ int tx_irq;
+
+ /* DMA stuff */
+ u8 dma_rx_sync;
+- short dma_rx_lch;
+ u8 dma_tx_sync;
+- short dma_tx_lch;
+-
+- /* Completion queues */
+- struct completion tx_irq_completion;
+- struct completion rx_irq_completion;
+- struct completion tx_dma_completion;
+- struct completion rx_dma_completion;
+
+ /* Protect the field .free, while checking if the mcbsp is in use */
+ spinlock_t lock;
+@@ -467,20 +452,10 @@ int omap_mcbsp_request(unsigned int id);
+ void omap_mcbsp_free(unsigned int id);
+ void omap_mcbsp_start(unsigned int id, int tx, int rx);
+ void omap_mcbsp_stop(unsigned int id, int tx, int rx);
+-void omap_mcbsp_xmit_word(unsigned int id, u32 word);
+-u32 omap_mcbsp_recv_word(unsigned int id);
+-
+-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+
+ /* McBSP functional clock source changing function */
+ extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
+
+-/* Polled read/write functions */
+-int omap_mcbsp_pollread(unsigned int id, u16 * buf);
+-int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
+-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
+-
+ /* McBSP signal muxing API */
+ void omap2_mcbsp1_mux_clkr_src(u8 mux);
+ void omap2_mcbsp1_mux_fsr_src(u8 mux);
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 1de2724..455eadc 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -16,8 +16,6 @@
+ #include <linux/init.h>
+ #include <linux/device.h>
+ #include <linux/platform_device.h>
+-#include <linux/wait.h>
+-#include <linux/completion.h>
+ #include <linux/interrupt.h>
+ #include <linux/err.h>
+ #include <linux/clk.h>
+@@ -25,7 +23,6 @@
+ #include <linux/io.h>
+ #include <linux/slab.h>
+
+-#include <plat/dma.h>
+ #include <plat/mcbsp.h>
+ #include <plat/omap_device.h>
+ #include <linux/pm_runtime.h>
+@@ -136,8 +133,6 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
+ irqst_spcr2);
+ /* Writing zero to XSYNC_ERR clears the IRQ */
+ MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
+- } else {
+- complete(&mcbsp_tx->tx_irq_completion);
+ }
+
+ return IRQ_HANDLED;
+@@ -156,41 +151,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
+ irqst_spcr1);
+ /* Writing zero to RSYNC_ERR clears the IRQ */
+ MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
+- } else {
+- complete(&mcbsp_rx->rx_irq_completion);
+ }
+
+ return IRQ_HANDLED;
+ }
+
+-static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
+-{
+- struct omap_mcbsp *mcbsp_dma_tx = data;
+-
+- dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
+- MCBSP_READ(mcbsp_dma_tx, SPCR2));
+-
+- /* We can free the channels */
+- omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
+- mcbsp_dma_tx->dma_tx_lch = -1;
+-
+- complete(&mcbsp_dma_tx->tx_dma_completion);
+-}
+-
+-static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
+-{
+- struct omap_mcbsp *mcbsp_dma_rx = data;
+-
+- dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
+- MCBSP_READ(mcbsp_dma_rx, SPCR2));
+-
+- /* We can free the channels */
+- omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
+- mcbsp_dma_rx->dma_rx_lch = -1;
+-
+- complete(&mcbsp_dma_rx->rx_dma_completion);
+-}
+-
+ /*
+ * omap_mcbsp_config simply write a config to the
+ * appropriate McBSP.
+@@ -758,37 +723,6 @@ static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
+ static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
+ #endif
+
+-/*
+- * We can choose between IRQ based or polled IO.
+- * This needs to be called before omap_mcbsp_request().
+- */
+-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
+-{
+- struct omap_mcbsp *mcbsp;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- spin_lock(&mcbsp->lock);
+-
+- if (!mcbsp->free) {
+- dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
+- mcbsp->id);
+- spin_unlock(&mcbsp->lock);
+- return -EINVAL;
+- }
+-
+- mcbsp->io_type = io_type;
+-
+- spin_unlock(&mcbsp->lock);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_set_io_type);
+-
+ int omap_mcbsp_request(unsigned int id)
+ {
+ struct omap_mcbsp *mcbsp;
+@@ -833,29 +767,24 @@ int omap_mcbsp_request(unsigned int id)
+ MCBSP_WRITE(mcbsp, SPCR1, 0);
+ MCBSP_WRITE(mcbsp, SPCR2, 0);
+
+- if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
+- /* We need to get IRQs here */
+- init_completion(&mcbsp->tx_irq_completion);
+- err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
+- 0, "McBSP", (void *)mcbsp);
++ err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
++ 0, "McBSP", (void *)mcbsp);
++ if (err != 0) {
++ dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
++ "for McBSP%d\n", mcbsp->tx_irq,
++ mcbsp->id);
++ goto err_clk_disable;
++ }
++
++ if (mcbsp->rx_irq) {
++ err = request_irq(mcbsp->rx_irq,
++ omap_mcbsp_rx_irq_handler,
++ 0, "McBSP", (void *)mcbsp);
+ if (err != 0) {
+- dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
+- "for McBSP%d\n", mcbsp->tx_irq,
++ dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
++ "for McBSP%d\n", mcbsp->rx_irq,
+ mcbsp->id);
+- goto err_clk_disable;
+- }
+-
+- if (mcbsp->rx_irq) {
+- init_completion(&mcbsp->rx_irq_completion);
+- err = request_irq(mcbsp->rx_irq,
+- omap_mcbsp_rx_irq_handler,
+- 0, "McBSP", (void *)mcbsp);
+- if (err != 0) {
+- dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
+- "for McBSP%d\n", mcbsp->rx_irq,
+- mcbsp->id);
+- goto err_free_irq;
+- }
++ goto err_free_irq;
+ }
+ }
+
+@@ -901,12 +830,9 @@ void omap_mcbsp_free(unsigned int id)
+
+ pm_runtime_put_sync(mcbsp->dev);
+
+- if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
+- /* Free IRQs */
+- if (mcbsp->rx_irq)
+- free_irq(mcbsp->rx_irq, (void *)mcbsp);
+- free_irq(mcbsp->tx_irq, (void *)mcbsp);
+- }
++ if (mcbsp->rx_irq)
++ free_irq(mcbsp->rx_irq, (void *)mcbsp);
++ free_irq(mcbsp->tx_irq, (void *)mcbsp);
+
+ reg_cache = mcbsp->reg_cache;
+
+@@ -1043,271 +969,6 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
+ }
+ EXPORT_SYMBOL(omap_mcbsp_stop);
+
+-/* polled mcbsp i/o operations */
+-int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
+-{
+- struct omap_mcbsp *mcbsp;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+-
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- MCBSP_WRITE(mcbsp, DXR1, buf);
+- /* if frame sync error - clear the error */
+- if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
+- /* clear error */
+- MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
+- /* resend */
+- return -1;
+- } else {
+- /* wait for transmit confirmation */
+- int attemps = 0;
+- while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
+- if (attemps++ > 1000) {
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) &
+- (~XRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR2,
+- MCBSP_READ_CACHE(mcbsp, SPCR2) |
+- (XRST));
+- udelay(10);
+- dev_err(mcbsp->dev, "Could not write to"
+- " McBSP%d Register\n", mcbsp->id);
+- return -2;
+- }
+- }
+- }
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_pollwrite);
+-
+-int omap_mcbsp_pollread(unsigned int id, u16 *buf)
+-{
+- struct omap_mcbsp *mcbsp;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- /* if frame sync error - clear the error */
+- if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
+- /* clear error */
+- MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
+- /* resend */
+- return -1;
+- } else {
+- /* wait for receive confirmation */
+- int attemps = 0;
+- while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
+- if (attemps++ > 1000) {
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) &
+- (~RRST));
+- udelay(10);
+- MCBSP_WRITE(mcbsp, SPCR1,
+- MCBSP_READ_CACHE(mcbsp, SPCR1) |
+- (RRST));
+- udelay(10);
+- dev_err(mcbsp->dev, "Could not read from"
+- " McBSP%d Register\n", mcbsp->id);
+- return -2;
+- }
+- }
+- }
+- *buf = MCBSP_READ(mcbsp, DRR1);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_pollread);
+-
+-/*
+- * IRQ based word transmission.
+- */
+-void omap_mcbsp_xmit_word(unsigned int id, u32 word)
+-{
+- struct omap_mcbsp *mcbsp;
+- omap_mcbsp_word_length word_length;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return;
+- }
+-
+- mcbsp = id_to_mcbsp_ptr(id);
+- word_length = mcbsp->tx_word_length;
+-
+- wait_for_completion(&mcbsp->tx_irq_completion);
+-
+- if (word_length > OMAP_MCBSP_WORD_16)
+- MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+- MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
+-}
+-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
+-
+-u32 omap_mcbsp_recv_word(unsigned int id)
+-{
+- struct omap_mcbsp *mcbsp;
+- u16 word_lsb, word_msb = 0;
+- omap_mcbsp_word_length word_length;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- word_length = mcbsp->rx_word_length;
+-
+- wait_for_completion(&mcbsp->rx_irq_completion);
+-
+- if (word_length > OMAP_MCBSP_WORD_16)
+- word_msb = MCBSP_READ(mcbsp, DRR2);
+- word_lsb = MCBSP_READ(mcbsp, DRR1);
+-
+- return (word_lsb | (word_msb << 16));
+-}
+-EXPORT_SYMBOL(omap_mcbsp_recv_word);
+-
+-/*
+- * Simple DMA based buffer rx/tx routines.
+- * Nothing fancy, just a single buffer tx/rx through DMA.
+- * The DMA resources are released once the transfer is done.
+- * For anything fancier, you should use your own customized DMA
+- * routines and callbacks.
+- */
+-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
+- unsigned int length)
+-{
+- struct omap_mcbsp *mcbsp;
+- int dma_tx_ch;
+- int src_port = 0;
+- int dest_port = 0;
+- int sync_dev = 0;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
+- omap_mcbsp_tx_dma_callback,
+- mcbsp,
+- &dma_tx_ch)) {
+- dev_err(mcbsp->dev, " Unable to request DMA channel for "
+- "McBSP%d TX. Trying IRQ based TX\n",
+- mcbsp->id);
+- return -EAGAIN;
+- }
+- mcbsp->dma_tx_lch = dma_tx_ch;
+-
+- dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
+- dma_tx_ch);
+-
+- init_completion(&mcbsp->tx_dma_completion);
+-
+- if (cpu_class_is_omap1()) {
+- src_port = OMAP_DMA_PORT_TIPB;
+- dest_port = OMAP_DMA_PORT_EMIFF;
+- }
+- if (cpu_class_is_omap2())
+- sync_dev = mcbsp->dma_tx_sync;
+-
+- omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
+- OMAP_DMA_DATA_TYPE_S16,
+- length >> 1, 1,
+- OMAP_DMA_SYNC_ELEMENT,
+- sync_dev, 0);
+-
+- omap_set_dma_dest_params(mcbsp->dma_tx_lch,
+- src_port,
+- OMAP_DMA_AMODE_CONSTANT,
+- mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
+- 0, 0);
+-
+- omap_set_dma_src_params(mcbsp->dma_tx_lch,
+- dest_port,
+- OMAP_DMA_AMODE_POST_INC,
+- buffer,
+- 0, 0);
+-
+- omap_start_dma(mcbsp->dma_tx_lch);
+- wait_for_completion(&mcbsp->tx_dma_completion);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
+-
+-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+- unsigned int length)
+-{
+- struct omap_mcbsp *mcbsp;
+- int dma_rx_ch;
+- int src_port = 0;
+- int dest_port = 0;
+- int sync_dev = 0;
+-
+- if (!omap_mcbsp_check_valid_id(id)) {
+- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+- return -ENODEV;
+- }
+- mcbsp = id_to_mcbsp_ptr(id);
+-
+- if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
+- omap_mcbsp_rx_dma_callback,
+- mcbsp,
+- &dma_rx_ch)) {
+- dev_err(mcbsp->dev, "Unable to request DMA channel for "
+- "McBSP%d RX. Trying IRQ based RX\n",
+- mcbsp->id);
+- return -EAGAIN;
+- }
+- mcbsp->dma_rx_lch = dma_rx_ch;
+-
+- dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
+- dma_rx_ch);
+-
+- init_completion(&mcbsp->rx_dma_completion);
+-
+- if (cpu_class_is_omap1()) {
+- src_port = OMAP_DMA_PORT_TIPB;
+- dest_port = OMAP_DMA_PORT_EMIFF;
+- }
+- if (cpu_class_is_omap2())
+- sync_dev = mcbsp->dma_rx_sync;
+-
+- omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
+- OMAP_DMA_DATA_TYPE_S16,
+- length >> 1, 1,
+- OMAP_DMA_SYNC_ELEMENT,
+- sync_dev, 0);
+-
+- omap_set_dma_src_params(mcbsp->dma_rx_lch,
+- src_port,
+- OMAP_DMA_AMODE_CONSTANT,
+- mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
+- 0, 0);
+-
+- omap_set_dma_dest_params(mcbsp->dma_rx_lch,
+- dest_port,
+- OMAP_DMA_AMODE_POST_INC,
+- buffer,
+- 0, 0);
+-
+- omap_start_dma(mcbsp->dma_rx_lch);
+- wait_for_completion(&mcbsp->rx_dma_completion);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
+-
+ #ifdef CONFIG_ARCH_OMAP3
+ #define max_thres(m) (mcbsp->pdata->buffer_size)
+ #define valid_threshold(m, val) ((val) <= max_thres(m))
+@@ -1619,8 +1280,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ spin_lock_init(&mcbsp->lock);
+ mcbsp->id = id + 1;
+ mcbsp->free = true;
+- mcbsp->dma_tx_lch = -1;
+- mcbsp->dma_rx_lch = -1;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
+ if (!res) {
+@@ -1646,9 +1305,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ else
+ mcbsp->phys_dma_base = res->start;
+
+- /* Default I/O is IRQ based */
+- mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
+-
+ mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
+ mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0021-omap2-fix-build-regression.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0021-omap2-fix-build-regression.patch
--- /dev/null
@@ -0,0 +1,29 @@
+From 2cb6af64e37c13cd61ff3c15ec89415086e97cd7 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 30 Jun 2011 12:58:01 +0000
+Subject: [PATCH 021/149] omap2+: fix build regression
+
+board-generic.c now contains a reference to omap3_timer, but depends
+only on ARCH_OMAP2, not on ARCH_OMAP3, which controls that symbol.
+omap2_timer seems to be more appropriate anyway, so use that instead.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-generic.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
+index c6ecf60..54db41a 100644
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -72,5 +72,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+ .init_early = omap_generic_init_early,
+ .init_irq = omap2_init_irq,
+ .init_machine = omap_generic_init,
+- .timer = &omap3_timer,
++ .timer = &omap2_timer,
+ MACHINE_END
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0022-OMAP-New-twl-common-for-common-TWL-configuration.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0022-OMAP-New-twl-common-for-common-TWL-configuration.patch
--- /dev/null
@@ -0,0 +1,200 @@
+From c7cd9749f6092a5411a66a863b98c2cb4ecd86aa Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sat, 4 Jun 2011 08:16:41 +0300
+Subject: [PATCH 022/149] OMAP: New twl-common for common TWL configuration
+
+Introduce a new file, which will be used to configure
+common pmic (TWL) devices, regulators, and TWL audio.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/common-board-devices.c | 21 -------------
+ arch/arm/mach-omap2/common-board-devices.h | 26 +--------------
+ arch/arm/mach-omap2/twl-common.c | 46 ++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/twl-common.h | 28 +++++++++++++++++
+ 5 files changed, 77 insertions(+), 46 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/twl-common.c
+ create mode 100644 arch/arm/mach-omap2/twl-common.h
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index adbe82d..ff1466f 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -269,4 +269,4 @@ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
+ disp-$(CONFIG_OMAP2_DSS) := display.o
+ obj-y += $(disp-m) $(disp-y)
+
+-obj-y += common-board-devices.o
++obj-y += common-board-devices.o twl-common.o
+diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
+index 0043fa8..bcb0c58 100644
+--- a/arch/arm/mach-omap2/common-board-devices.c
++++ b/arch/arm/mach-omap2/common-board-devices.c
+@@ -20,36 +20,15 @@
+ *
+ */
+
+-#include <linux/i2c.h>
+-#include <linux/i2c/twl.h>
+-
+ #include <linux/gpio.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
+
+-#include <plat/i2c.h>
+ #include <plat/mcspi.h>
+ #include <plat/nand.h>
+
+ #include "common-board-devices.h"
+
+-static struct i2c_board_info __initdata pmic_i2c_board_info = {
+- .addr = 0x48,
+- .flags = I2C_CLIENT_WAKE,
+-};
+-
+-void __init omap_pmic_init(int bus, u32 clkrate,
+- const char *pmic_type, int pmic_irq,
+- struct twl4030_platform_data *pmic_data)
+-{
+- strncpy(pmic_i2c_board_info.type, pmic_type,
+- sizeof(pmic_i2c_board_info.type));
+- pmic_i2c_board_info.irq = pmic_irq;
+- pmic_i2c_board_info.platform_data = pmic_data;
+-
+- omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+-}
+-
+ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
+index 6797190..a0b4a42 100644
+--- a/arch/arm/mach-omap2/common-board-devices.h
++++ b/arch/arm/mach-omap2/common-board-devices.h
+@@ -1,33 +1,11 @@
+ #ifndef __OMAP_COMMON_BOARD_DEVICES__
+ #define __OMAP_COMMON_BOARD_DEVICES__
+
++#include "twl-common.h"
++
+ #define NAND_BLOCK_SIZE SZ_128K
+
+-struct twl4030_platform_data;
+ struct mtd_partition;
+-
+-void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+- struct twl4030_platform_data *pmic_data);
+-
+-static inline void omap2_pmic_init(const char *pmic_type,
+- struct twl4030_platform_data *pmic_data)
+-{
+- omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+-}
+-
+-static inline void omap3_pmic_init(const char *pmic_type,
+- struct twl4030_platform_data *pmic_data)
+-{
+- omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+-}
+-
+-static inline void omap4_pmic_init(const char *pmic_type,
+- struct twl4030_platform_data *pmic_data)
+-{
+- /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+- omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+-}
+-
+ struct ads7846_platform_data;
+
+ void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
+new file mode 100644
+index 0000000..4f7b24c
+--- /dev/null
++++ b/arch/arm/mach-omap2/twl-common.c
+@@ -0,0 +1,46 @@
++/*
++ * twl-common.c
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc..
++ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
++#include <linux/i2c.h>
++#include <linux/i2c/twl.h>
++#include <linux/gpio.h>
++
++#include <plat/i2c.h>
++
++#include "twl-common.h"
++
++static struct i2c_board_info __initdata pmic_i2c_board_info = {
++ .addr = 0x48,
++ .flags = I2C_CLIENT_WAKE,
++};
++
++void __init omap_pmic_init(int bus, u32 clkrate,
++ const char *pmic_type, int pmic_irq,
++ struct twl4030_platform_data *pmic_data)
++{
++ strncpy(pmic_i2c_board_info.type, pmic_type,
++ sizeof(pmic_i2c_board_info.type));
++ pmic_i2c_board_info.irq = pmic_irq;
++ pmic_i2c_board_info.platform_data = pmic_data;
++
++ omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
++}
+diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
+new file mode 100644
+index 0000000..e9fe2ab
+--- /dev/null
++++ b/arch/arm/mach-omap2/twl-common.h
+@@ -0,0 +1,28 @@
++#ifndef __OMAP_PMIC_COMMON__
++#define __OMAP_PMIC_COMMON__
++
++struct twl4030_platform_data;
++
++void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
++ struct twl4030_platform_data *pmic_data);
++
++static inline void omap2_pmic_init(const char *pmic_type,
++ struct twl4030_platform_data *pmic_data)
++{
++ omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
++}
++
++static inline void omap3_pmic_init(const char *pmic_type,
++ struct twl4030_platform_data *pmic_data)
++{
++ omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
++}
++
++static inline void omap4_pmic_init(const char *pmic_type,
++ struct twl4030_platform_data *pmic_data)
++{
++ /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
++ omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
++}
++
++#endif /* __OMAP_PMIC_COMMON__ */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0023-OMAP4-Move-common-twl6030-configuration-to-twl-commo.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0023-OMAP4-Move-common-twl6030-configuration-to-twl-commo.patch
--- /dev/null
@@ -0,0 +1,601 @@
+From 96fff3aa7a203c74768bfd35dde000653f706d2c Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Tue, 7 Jun 2011 10:26:46 +0300
+Subject: [PATCH 023/149] OMAP4: Move common twl6030 configuration to twl-common
+
+Reduce the amount of duplicated code by moving the common
+configuration for TWL6030 (on OMAP4 platform) to the
+twl-common file.
+Use the omap4_pmic_get_config function from board files to
+properly configure the PMIC with the common fields.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 141 ++-------------------------
+ arch/arm/mach-omap2/board-omap4panda.c | 146 +++--------------------------
+ arch/arm/mach-omap2/twl-common.c | 163 ++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/twl-common.h | 20 ++++
+ 4 files changed, 205 insertions(+), 265 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index d7df07e..933b25b 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -302,14 +302,6 @@ static struct omap_musb_board_data musb_board_data = {
+ .power = 100,
+ };
+
+-static struct twl4030_usb_data omap4_usbphy_data = {
+- .phy_init = omap4430_phy_init,
+- .phy_exit = omap4430_phy_exit,
+- .phy_power = omap4430_phy_power,
+- .phy_set_clock = omap4430_phy_set_clk,
+- .phy_suspend = omap4430_phy_suspend,
+-};
+-
+ static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 2,
+@@ -332,10 +324,6 @@ static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+-static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+-};
+-
+ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+ {
+ int ret = 0;
+@@ -394,61 +382,6 @@ static struct regulator_init_data sdp4430_vaux1 = {
+ .consumer_supplies = sdp4430_vaux_supply,
+ };
+
+-static struct regulator_init_data sdp4430_vaux2 = {
+- .constraints = {
+- .min_uV = 1200000,
+- .max_uV = 2800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data sdp4430_vaux3 = {
+- .constraints = {
+- .min_uV = 1000000,
+- .max_uV = 3000000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-/* VMMC1 for MMC1 card */
+-static struct regulator_init_data sdp4430_vmmc = {
+- .constraints = {
+- .min_uV = 1200000,
+- .max_uV = 3000000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = sdp4430_vmmc_supply,
+-};
+-
+-static struct regulator_init_data sdp4430_vpp = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 2500000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+ static struct regulator_init_data sdp4430_vusim = {
+ .constraints = {
+ .min_uV = 1200000,
+@@ -462,74 +395,10 @@ static struct regulator_init_data sdp4430_vusim = {
+ },
+ };
+
+-static struct regulator_init_data sdp4430_vana = {
+- .constraints = {
+- .min_uV = 2100000,
+- .max_uV = 2100000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data sdp4430_vcxio = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data sdp4430_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data sdp4430_vusb = {
+- .constraints = {
+- .min_uV = 3300000,
+- .max_uV = 3300000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data sdp4430_clk32kg = {
+- .constraints = {
+- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+ static struct twl4030_platform_data sdp4430_twldata = {
+- .irq_base = TWL6030_IRQ_BASE,
+- .irq_end = TWL6030_IRQ_END,
+-
+ /* Regulators */
+- .vmmc = &sdp4430_vmmc,
+- .vpp = &sdp4430_vpp,
+ .vusim = &sdp4430_vusim,
+- .vana = &sdp4430_vana,
+- .vcxio = &sdp4430_vcxio,
+- .vdac = &sdp4430_vdac,
+- .vusb = &sdp4430_vusb,
+ .vaux1 = &sdp4430_vaux1,
+- .vaux2 = &sdp4430_vaux2,
+- .vaux3 = &sdp4430_vaux3,
+- .clk32kg = &sdp4430_clk32kg,
+- .usb = &omap4_usbphy_data
+ };
+
+ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
+@@ -547,6 +416,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
+ };
+ static int __init omap4_i2c_init(void)
+ {
++ omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
++ TWL_COMMON_REGULATOR_VDAC |
++ TWL_COMMON_REGULATOR_VAUX2 |
++ TWL_COMMON_REGULATOR_VAUX3 |
++ TWL_COMMON_REGULATOR_VMMC |
++ TWL_COMMON_REGULATOR_VPP |
++ TWL_COMMON_REGULATOR_VANA |
++ TWL_COMMON_REGULATOR_VCXIO |
++ TWL_COMMON_REGULATOR_VUSB |
++ TWL_COMMON_REGULATOR_CLK32KG);
+ omap4_pmic_init("twl6030", &sdp4430_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index ee2034e..9aaa960 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -154,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
+ .power = 100,
+ };
+
+-static struct twl4030_usb_data omap4_usbphy_data = {
+- .phy_init = omap4430_phy_init,
+- .phy_exit = omap4430_phy_exit,
+- .phy_power = omap4430_phy_power,
+- .phy_set_clock = omap4430_phy_set_clk,
+- .phy_suspend = omap4430_phy_suspend,
+-};
+-
+ static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 1,
+@@ -181,10 +173,6 @@ static struct omap2_hsmmc_info mmc[] = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
+- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+-};
+-
+ static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
+ };
+@@ -269,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+ return 0;
+ }
+
+-static struct regulator_init_data omap4_panda_vaux2 = {
+- .constraints = {
+- .min_uV = 1200000,
+- .max_uV = 2800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_vaux3 = {
+- .constraints = {
+- .min_uV = 1000000,
+- .max_uV = 3000000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-/* VMMC1 for MMC1 card */
+-static struct regulator_init_data omap4_panda_vmmc = {
+- .constraints = {
+- .min_uV = 1200000,
+- .max_uV = 3000000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc_supply),
+- .consumer_supplies = omap4_panda_vmmc_supply,
+-};
+-
+-static struct regulator_init_data omap4_panda_vpp = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 2500000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+- | REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_vana = {
+- .constraints = {
+- .min_uV = 2100000,
+- .max_uV = 2100000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_vcxio = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_vusb = {
+- .constraints = {
+- .min_uV = 3300000,
+- .max_uV = 3300000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct regulator_init_data omap4_panda_clk32kg = {
+- .constraints = {
+- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+- },
+-};
+-
+-static struct twl4030_platform_data omap4_panda_twldata = {
+- .irq_base = TWL6030_IRQ_BASE,
+- .irq_end = TWL6030_IRQ_END,
+-
+- /* Regulators */
+- .vmmc = &omap4_panda_vmmc,
+- .vpp = &omap4_panda_vpp,
+- .vana = &omap4_panda_vana,
+- .vcxio = &omap4_panda_vcxio,
+- .vdac = &omap4_panda_vdac,
+- .vusb = &omap4_panda_vusb,
+- .vaux2 = &omap4_panda_vaux2,
+- .vaux3 = &omap4_panda_vaux3,
+- .clk32kg = &omap4_panda_clk32kg,
+- .usb = &omap4_usbphy_data,
+-};
++/* Panda board uses the common PMIC configuration */
++static struct twl4030_platform_data omap4_panda_twldata;
+
+ /*
+ * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
+@@ -404,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
+
+ static int __init omap4_panda_i2c_init(void)
+ {
++ omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
++ TWL_COMMON_REGULATOR_VDAC |
++ TWL_COMMON_REGULATOR_VAUX2 |
++ TWL_COMMON_REGULATOR_VAUX3 |
++ TWL_COMMON_REGULATOR_VMMC |
++ TWL_COMMON_REGULATOR_VPP |
++ TWL_COMMON_REGULATOR_VANA |
++ TWL_COMMON_REGULATOR_VCXIO |
++ TWL_COMMON_REGULATOR_VUSB |
++ TWL_COMMON_REGULATOR_CLK32KG);
+ omap4_pmic_init("twl6030", &omap4_panda_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ /*
+diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
+index 4f7b24c..cf80f4c 100644
+--- a/arch/arm/mach-omap2/twl-common.c
++++ b/arch/arm/mach-omap2/twl-common.c
+@@ -23,8 +23,11 @@
+ #include <linux/i2c.h>
+ #include <linux/i2c/twl.h>
+ #include <linux/gpio.h>
++#include <linux/regulator/machine.h>
++#include <linux/regulator/fixed.h>
+
+ #include <plat/i2c.h>
++#include <plat/usb.h>
+
+ #include "twl-common.h"
+
+@@ -44,3 +47,163 @@ void __init omap_pmic_init(int bus, u32 clkrate,
+
+ omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+ }
++
++static struct twl4030_usb_data omap4_usb_pdata = {
++ .phy_init = omap4430_phy_init,
++ .phy_exit = omap4430_phy_exit,
++ .phy_power = omap4430_phy_power,
++ .phy_set_clock = omap4430_phy_set_clk,
++ .phy_suspend = omap4430_phy_suspend,
++};
++
++static struct regulator_init_data omap4_vdac_idata = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 1800000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_vaux2_idata = {
++ .constraints = {
++ .min_uV = 1200000,
++ .max_uV = 2800000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
++ | REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_vaux3_idata = {
++ .constraints = {
++ .min_uV = 1000000,
++ .max_uV = 3000000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
++ | REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_consumer_supply omap4_vmmc_supply[] = {
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
++};
++
++/* VMMC1 for MMC1 card */
++static struct regulator_init_data omap4_vmmc_idata = {
++ .constraints = {
++ .min_uV = 1200000,
++ .max_uV = 3000000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
++ | REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
++ .consumer_supplies = omap4_vmmc_supply,
++};
++
++static struct regulator_init_data omap4_vpp_idata = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 2500000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
++ | REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_vana_idata = {
++ .constraints = {
++ .min_uV = 2100000,
++ .max_uV = 2100000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_vcxio_idata = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 1800000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_vusb_idata = {
++ .constraints = {
++ .min_uV = 3300000,
++ .max_uV = 3300000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct regulator_init_data omap4_clk32kg_idata = {
++ .constraints = {
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++};
++
++void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
++ u32 pdata_flags, u32 regulators_flags)
++{
++ if (!pmic_data->irq_base)
++ pmic_data->irq_base = TWL6030_IRQ_BASE;
++ if (!pmic_data->irq_end)
++ pmic_data->irq_end = TWL6030_IRQ_END;
++
++ /* Common platform data configurations */
++ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
++ pmic_data->usb = &omap4_usb_pdata;
++
++ /* Common regulator configurations */
++ if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
++ pmic_data->vdac = &omap4_vdac_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
++ pmic_data->vaux2 = &omap4_vaux2_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
++ pmic_data->vaux3 = &omap4_vaux3_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
++ pmic_data->vmmc = &omap4_vmmc_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
++ pmic_data->vpp = &omap4_vpp_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
++ pmic_data->vana = &omap4_vana_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
++ pmic_data->vcxio = &omap4_vcxio_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
++ pmic_data->vusb = &omap4_vusb_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
++ !pmic_data->clk32kg)
++ pmic_data->clk32kg = &omap4_clk32kg_idata;
++}
+diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
+index e9fe2ab..d96c289 100644
+--- a/arch/arm/mach-omap2/twl-common.h
++++ b/arch/arm/mach-omap2/twl-common.h
+@@ -1,6 +1,23 @@
+ #ifndef __OMAP_PMIC_COMMON__
+ #define __OMAP_PMIC_COMMON__
+
++#define TWL_COMMON_PDATA_USB (1 << 0)
++
++/* Common LDO regulators for TWL4030/TWL6030 */
++#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
++#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
++#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
++#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
++
++/* TWL6030 LDO regulators */
++#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
++#define TWL_COMMON_REGULATOR_VPP (1 << 5)
++#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
++#define TWL_COMMON_REGULATOR_VANA (1 << 7)
++#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
++#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
++#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
++
+ struct twl4030_platform_data;
+
+ void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+@@ -25,4 +42,7 @@ static inline void omap4_pmic_init(const char *pmic_type,
+ omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+ }
+
++void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
++ u32 pdata_flags, u32 regulators_flags);
++
+ #endif /* __OMAP_PMIC_COMMON__ */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0024-OMAP3-Move-common-twl-configuration-to-twl-common.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0024-OMAP3-Move-common-twl-configuration-to-twl-common.patch
--- /dev/null
@@ -0,0 +1,827 @@
+From 7f52cd416de3100e27599382f8dfea45ed1a6d45 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Tue, 7 Jun 2011 10:28:54 +0300
+Subject: [PATCH 024/149] OMAP3: Move common twl configuration to twl-common
+
+Reduce the amount of duplicated code by moving the common
+configuration for twl4030/5030/tpsxx to the twl-common file.
+Use the omap3_pmic_get_config function from board files to
+properly configure the PMIC with the common fields.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 42 ++------------------
+ arch/arm/mach-omap2/board-cm-t35.c | 9 +----
+ arch/arm/mach-omap2/board-devkit8000.c | 18 +--------
+ arch/arm/mach-omap2/board-igep0020.c | 20 ++--------
+ arch/arm/mach-omap2/board-ldp.c | 15 +------
+ arch/arm/mach-omap2/board-omap3beagle.c | 18 +--------
+ arch/arm/mach-omap2/board-omap3evm.c | 24 +----------
+ arch/arm/mach-omap2/board-omap3pandora.c | 17 +-------
+ arch/arm/mach-omap2/board-omap3stalker.c | 24 +----------
+ arch/arm/mach-omap2/board-omap3touchbook.c | 19 +--------
+ arch/arm/mach-omap2/board-overo.c | 17 +-------
+ arch/arm/mach-omap2/board-rm680.c | 8 +---
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 15 +------
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 51 +++++--------------------
+ arch/arm/mach-omap2/twl-common.c | 53 ++++++++++++++++++++++++++
+ arch/arm/mach-omap2/twl-common.h | 6 +++
+ 16 files changed, 99 insertions(+), 257 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 12fae21..8bbd4e0 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
+ omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
+ }
+
+-static int sdp3430_batt_table[] = {
+-/* 0 C*/
+-30800, 29500, 28300, 27100,
+-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+-11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
+-8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
+-5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
+-4040, 3910, 3790, 3670, 3550
+-};
+-
+-static struct twl4030_bci_platform_data sdp3430_bci_data = {
+- .battery_tmp_tbl = sdp3430_batt_table,
+- .tblsize = ARRAY_SIZE(sdp3430_batt_table),
+-};
+-
+ static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 1,
+@@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
+ .setup = sdp3430_twl_gpio_setup,
+ };
+
+-static struct twl4030_usb_data sdp3430_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+-static struct twl4030_madc_platform_data sdp3430_madc_data = {
+- .irq_line = 1,
+-};
+-
+ /* regulator consumer mappings */
+
+ /* ads7846 on SPI */
+@@ -463,24 +439,10 @@ static struct regulator_init_data sdp3430_vpll2 = {
+ .consumer_supplies = sdp3430_vpll2_supplies,
+ };
+
+-static struct twl4030_codec_audio_data sdp3430_audio;
+-
+-static struct twl4030_codec_data sdp3430_codec = {
+- .audio_mclk = 26000000,
+- .audio = &sdp3430_audio,
+-};
+-
+ static struct twl4030_platform_data sdp3430_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .bci = &sdp3430_bci_data,
+ .gpio = &sdp3430_gpio_data,
+- .madc = &sdp3430_madc_data,
+ .keypad = &sdp3430_kp_data,
+- .usb = &sdp3430_usb_data,
+- .codec = &sdp3430_codec,
+
+ .vaux1 = &sdp3430_vaux1,
+ .vaux2 = &sdp3430_vaux2,
+@@ -496,7 +458,11 @@ static struct twl4030_platform_data sdp3430_twldata = {
+ static int __init omap3430_i2c_init(void)
+ {
+ /* i2c1 for PMIC only */
++ omap3_pmic_get_config(&sdp3430_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
++ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("twl4030", &sdp3430_twldata);
++
+ /* i2c2 on camera connector (for sensor control) and optional isp1301 */
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ /* i2c3 on display connector (for DVI, tfp410) */
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index d76dca7..cb00abc 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -410,10 +410,6 @@ static struct regulator_init_data cm_t35_vpll2 = {
+ .consumer_supplies = cm_t35_vdvi_supply,
+ };
+
+-static struct twl4030_usb_data cm_t35_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static uint32_t cm_t35_keymap[] = {
+ KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
+ KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
+@@ -492,12 +488,8 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
+ };
+
+ static struct twl4030_platform_data cm_t35_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+ .keypad = &cm_t35_kp_data,
+- .usb = &cm_t35_usb_data,
+ .gpio = &cm_t35_gpio_data,
+ .vmmc1 = &cm_t35_vmmc1,
+ .vsim = &cm_t35_vsim,
+@@ -507,6 +499,7 @@ static struct twl4030_platform_data cm_t35_twldata = {
+
+ static void __init cm_t35_init_i2c(void)
+ {
++ omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB, 0);
+ omap3_pmic_init("tps65930", &cm_t35_twldata);
+ }
+
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 949dbea..364942e 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -332,25 +332,9 @@ static struct regulator_init_data devkit8000_vio = {
+ .consumer_supplies = devkit8000_vio_supply,
+ };
+
+-static struct twl4030_usb_data devkit8000_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+-static struct twl4030_codec_audio_data devkit8000_audio_data;
+-
+-static struct twl4030_codec_data devkit8000_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &devkit8000_audio_data,
+-};
+-
+ static struct twl4030_platform_data devkit8000_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .usb = &devkit8000_usb_data,
+ .gpio = &devkit8000_gpio_data,
+- .codec = &devkit8000_codec_data,
+ .vmmc1 = &devkit8000_vmmc1,
+ .vdac = &devkit8000_vdac,
+ .vpll1 = &devkit8000_vpll1,
+@@ -360,6 +344,8 @@ static struct twl4030_platform_data devkit8000_twldata = {
+
+ static int __init devkit8000_i2c_init(void)
+ {
++ omap3_pmic_get_config(&devkit8000_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("tps65930", &devkit8000_twldata);
+ /* Bus 3 is attached to the DVI port where devices like the pico DLP
+ * projector don't work reliably with 400kHz */
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index f683835..e0a6687 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -443,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
+ .setup = igep_twl_gpio_setup,
+ };
+
+-static struct twl4030_usb_data igep_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static int igep2_enable_dvi(struct omap_dss_device *dssdev)
+ {
+ gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
+@@ -522,13 +518,6 @@ static void __init igep_init_early(void)
+ m65kxxxxam_sdrc_params);
+ }
+
+-static struct twl4030_codec_audio_data igep2_audio_data;
+-
+-static struct twl4030_codec_data igep2_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &igep2_audio_data,
+-};
+-
+ static int igep2_keymap[] = {
+ KEY(0, 0, KEY_LEFT),
+ KEY(0, 1, KEY_RIGHT),
+@@ -561,11 +550,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
+ };
+
+ static struct twl4030_platform_data igep_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .usb = &igep_usb_data,
+ .gpio = &igep_twl4030_gpio_pdata,
+ .vmmc1 = &igep_vmmc1,
+ .vio = &igep_vio,
+@@ -581,6 +566,8 @@ static void __init igep_i2c_init(void)
+ {
+ int ret;
+
++ omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
++
+ if (machine_is_igep0020()) {
+ /*
+ * Bus 3 is attached to the DVI port where devices like the
+@@ -591,9 +578,10 @@ static void __init igep_i2c_init(void)
+ if (ret)
+ pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
+
+- igep_twldata.codec = &igep2_codec_data;
+ igep_twldata.keypad = &igep2_keypad_pdata;
+ igep_twldata.vpll2 = &igep2_vpll2;
++ /* Use common codec data */
++ omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
+ }
+
+ omap3_pmic_init("twl4030", &igep_twldata);
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index 5d4328f..218764c 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -199,20 +199,12 @@ static void __init omap_ldp_init_early(void)
+ omap2_init_common_devices(NULL, NULL);
+ }
+
+-static struct twl4030_usb_data ldp_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static struct twl4030_gpio_platform_data ldp_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+ .irq_end = TWL4030_GPIO_IRQ_END,
+ };
+
+-static struct twl4030_madc_platform_data ldp_madc_data = {
+- .irq_line = 1,
+-};
+-
+ static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+@@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
+ };
+
+ static struct twl4030_platform_data ldp_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .madc = &ldp_madc_data,
+- .usb = &ldp_usb_data,
+ .vmmc1 = &ldp_vmmc1,
+ .vaux1 = &ldp_vaux1,
+ .gpio = &ldp_gpio_data,
+@@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
+
+ static int __init omap_i2c_init(void)
+ {
++ omap3_pmic_get_config(&ldp_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
+ omap3_pmic_init("twl4030", &ldp_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 2d8dfb3..ec61e9c 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -380,25 +380,9 @@ static struct regulator_init_data beagle_vpll2 = {
+ .consumer_supplies = beagle_vdvi_supplies,
+ };
+
+-static struct twl4030_usb_data beagle_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+-static struct twl4030_codec_audio_data beagle_audio_data;
+-
+-static struct twl4030_codec_data beagle_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &beagle_audio_data,
+-};
+-
+ static struct twl4030_platform_data beagle_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .usb = &beagle_usb_data,
+ .gpio = &beagle_gpio_data,
+- .codec = &beagle_codec_data,
+ .vmmc1 = &beagle_vmmc1,
+ .vsim = &beagle_vsim,
+ .vdac = &beagle_vdac,
+@@ -413,6 +397,8 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+
+ static int __init omap3_beagle_i2c_init(void)
+ {
++ omap3_pmic_get_config(&beagle_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("twl4030", &beagle_twldata);
+ /* Bus 3 is attached to the DVI port where devices like the pico DLP
+ * projector don't work reliably with 400kHz */
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 57bce0f..1ca298a 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -396,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
+ .setup = omap3evm_twl_gpio_setup,
+ };
+
+-static struct twl4030_usb_data omap3evm_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static uint32_t board_keymap[] = {
+ KEY(0, 0, KEY_LEFT),
+ KEY(0, 1, KEY_DOWN),
+@@ -434,17 +430,6 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
+ .rep = 1,
+ };
+
+-static struct twl4030_madc_platform_data omap3evm_madc_data = {
+- .irq_line = 1,
+-};
+-
+-static struct twl4030_codec_audio_data omap3evm_audio_data;
+-
+-static struct twl4030_codec_data omap3evm_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &omap3evm_audio_data,
+-};
+-
+ static struct regulator_consumer_supply omap3_evm_vdda_dac_supply[] = {
+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+ };
+@@ -547,15 +532,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
+ #endif
+
+ static struct twl4030_platform_data omap3evm_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+ .keypad = &omap3evm_kp_data,
+- .madc = &omap3evm_madc_data,
+- .usb = &omap3evm_usb_data,
+ .gpio = &omap3evm_gpio_data,
+- .codec = &omap3evm_codec_data,
+ .vdac = &omap3_evm_vdac,
+ .vpll2 = &omap3_evm_vpll2,
+ .vio = &omap3evm_vio,
+@@ -565,6 +544,9 @@ static struct twl4030_platform_data omap3evm_twldata = {
+
+ static int __init omap3_evm_i2c_init(void)
+ {
++ omap3_pmic_get_config(&omap3evm_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
++ TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("twl4030", &omap3evm_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index d4ea940..f5abf76 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -508,25 +508,10 @@ static struct platform_device pandora_vwlan_device = {
+ },
+ };
+
+-static struct twl4030_usb_data omap3pandora_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+-static struct twl4030_codec_audio_data omap3pandora_audio_data;
+-
+-static struct twl4030_codec_data omap3pandora_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &omap3pandora_audio_data,
+-};
+-
+ static struct twl4030_bci_platform_data pandora_bci_data;
+
+ static struct twl4030_platform_data omap3pandora_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+ .gpio = &omap3pandora_gpio_data,
+- .usb = &omap3pandora_usb_data,
+- .codec = &omap3pandora_codec_data,
+ .vmmc1 = &pandora_vmmc1,
+ .vmmc2 = &pandora_vmmc2,
+ .vdac = &pandora_vdac,
+@@ -548,6 +533,8 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
+
+ static int __init omap3pandora_i2c_init(void)
+ {
++ omap3_pmic_get_config(&omap3pandora_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("tps65950", &omap3pandora_twldata);
+ /* i2c2 pins are not connected */
+ omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index b8ad4dd..6e59e59 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -349,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
+ .setup = omap3stalker_twl_gpio_setup,
+ };
+
+-static struct twl4030_usb_data omap3stalker_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static uint32_t board_keymap[] = {
+ KEY(0, 0, KEY_LEFT),
+ KEY(0, 1, KEY_DOWN),
+@@ -387,17 +383,6 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
+ .rep = 1,
+ };
+
+-static struct twl4030_madc_platform_data omap3stalker_madc_data = {
+- .irq_line = 1,
+-};
+-
+-static struct twl4030_codec_audio_data omap3stalker_audio_data;
+-
+-static struct twl4030_codec_data omap3stalker_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &omap3stalker_audio_data,
+-};
+-
+ static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply[] = {
+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+ };
+@@ -439,15 +424,9 @@ static struct regulator_init_data omap3_stalker_vpll2 = {
+ };
+
+ static struct twl4030_platform_data omap3stalker_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+ .keypad = &omap3stalker_kp_data,
+- .madc = &omap3stalker_madc_data,
+- .usb = &omap3stalker_usb_data,
+ .gpio = &omap3stalker_gpio_data,
+- .codec = &omap3stalker_codec_data,
+ .vdac = &omap3_stalker_vdac,
+ .vpll2 = &omap3_stalker_vpll2,
+ .vmmc1 = &omap3stalker_vmmc1,
+@@ -470,6 +449,9 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
+
+ static int __init omap3_stalker_i2c_init(void)
+ {
++ omap3_pmic_get_config(&omap3stalker_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
++ TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("twl4030", &omap3stalker_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 57e6ed3..717972c 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -235,25 +235,9 @@ static struct regulator_init_data touchbook_vpll2 = {
+ .consumer_supplies = touchbook_vdvi_supply,
+ };
+
+-static struct twl4030_usb_data touchbook_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+-static struct twl4030_codec_audio_data touchbook_audio_data;
+-
+-static struct twl4030_codec_data touchbook_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &touchbook_audio_data,
+-};
+-
+ static struct twl4030_platform_data touchbook_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .usb = &touchbook_usb_data,
+ .gpio = &touchbook_gpio_data,
+- .codec = &touchbook_codec_data,
+ .vmmc1 = &touchbook_vmmc1,
+ .vsim = &touchbook_vsim,
+ .vdac = &touchbook_vdac,
+@@ -269,8 +253,9 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
+ static int __init omap3_touchbook_i2c_init(void)
+ {
+ /* Standard TouchBook bus */
++ omap3_pmic_get_config(&touchbook_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("twl4030", &touchbook_twldata);
+-
+ /* Additional TouchBook bus */
+ omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
+ ARRAY_SIZE(touchBook_i2c_boardinfo));
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 1bf2f39..776b444 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -433,10 +433,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
+ .setup = overo_twl_gpio_setup,
+ };
+
+-static struct twl4030_usb_data overo_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static struct regulator_init_data overo_vmmc1 = {
+ .constraints = {
+ .min_uV = 1850000,
+@@ -480,19 +476,8 @@ static struct regulator_init_data overo_vpll2 = {
+ .consumer_supplies = overo_vdds_dsi_supply,
+ };
+
+-static struct twl4030_codec_audio_data overo_audio_data;
+-
+-static struct twl4030_codec_data overo_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &overo_audio_data,
+-};
+-
+ static struct twl4030_platform_data overo_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+ .gpio = &overo_gpio_data,
+- .usb = &overo_usb_data,
+- .codec = &overo_codec_data,
+ .vmmc1 = &overo_vmmc1,
+ .vdac = &overo_vdac,
+ .vpll2 = &overo_vpll2,
+@@ -500,6 +485,8 @@ static struct twl4030_platform_data overo_twldata = {
+
+ static int __init overo_i2c_init(void)
+ {
++ omap3_pmic_get_config(&overo_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
+ omap3_pmic_init("tps65950", &overo_twldata);
+ /* i2c2 pins are used for gpio */
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
+index 54dceb1..7dfed24 100644
+--- a/arch/arm/mach-omap2/board-rm680.c
++++ b/arch/arm/mach-omap2/board-rm680.c
+@@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
+ .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
+ };
+
+-static struct twl4030_usb_data rm680_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static struct twl4030_platform_data rm680_twl_data = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+ .gpio = &rm680_gpio_data,
+- .usb = &rm680_usb_data,
+ /* add rest of the children here */
+ };
+
+ static void __init rm680_i2c_init(void)
+ {
++ omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
+ omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index 7810b1e..75be074 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -288,10 +288,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
+ .rep = 1,
+ };
+
+-static struct twl4030_madc_platform_data rx51_madc_data = {
+- .irq_line = 1,
+-};
+-
+ /* Enable input logic and pull all lines up when eMMC is on. */
+ static struct omap_board_mux rx51_mmc2_on_mux[] = {
+ OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+@@ -603,10 +599,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
+ .setup = rx51_twlgpio_setup,
+ };
+
+-static struct twl4030_usb_data rx51_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static struct twl4030_ins sleep_on_seq[] __initdata = {
+ /*
+ * Turn off everything
+@@ -778,14 +770,9 @@ struct twl4030_codec_data rx51_codec_data __initdata = {
+ };
+
+ static struct twl4030_platform_data rx51_twldata __initdata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+ .gpio = &rx51_gpio_data,
+ .keypad = &rx51_kp_data,
+- .madc = &rx51_madc_data,
+- .usb = &rx51_usb_data,
+ .power = &rx51_t2scripts_data,
+ .codec = &rx51_codec_data,
+
+@@ -850,6 +837,8 @@ static int __init rx51_i2c_init(void)
+ rx51_twldata.vaux3 = &rx51_vaux3_cam;
+ }
+ rx51_twldata.vmmc2 = &rx51_vmmc2;
++ omap3_pmic_get_config(&rx51_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
+ omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+ omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
+ ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index 8495f82..6d8df1b 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -285,26 +285,6 @@ static void zoom2_set_hs_extmute(int mute)
+ gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
+ }
+
+-static int zoom_batt_table[] = {
+-/* 0 C*/
+-30800, 29500, 28300, 27100,
+-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+-11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
+-8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
+-5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
+-4040, 3910, 3790, 3670, 3550
+-};
+-
+-static struct twl4030_bci_platform_data zoom_bci_data = {
+- .battery_tmp_tbl = zoom_batt_table,
+- .tblsize = ARRAY_SIZE(zoom_batt_table),
+-};
+-
+-static struct twl4030_usb_data zoom_usb_data = {
+- .usb_mode = T2_USB_MODE_ULPI,
+-};
+-
+ static struct twl4030_gpio_platform_data zoom_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+@@ -312,28 +292,10 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
+ .setup = zoom_twl_gpio_setup,
+ };
+
+-static struct twl4030_madc_platform_data zoom_madc_data = {
+- .irq_line = 1,
+-};
+-
+-static struct twl4030_codec_audio_data zoom_audio_data;
+-
+-static struct twl4030_codec_data zoom_codec_data = {
+- .audio_mclk = 26000000,
+- .audio = &zoom_audio_data,
+-};
+-
+ static struct twl4030_platform_data zoom_twldata = {
+- .irq_base = TWL4030_IRQ_BASE,
+- .irq_end = TWL4030_IRQ_END,
+-
+ /* platform_data for children goes here */
+- .bci = &zoom_bci_data,
+- .madc = &zoom_madc_data,
+- .usb = &zoom_usb_data,
+ .gpio = &zoom_gpio_data,
+ .keypad = &zoom_kp_twl4030_data,
+- .codec = &zoom_codec_data,
+ .vmmc1 = &zoom_vmmc1,
+ .vmmc2 = &zoom_vmmc2,
+ .vsim = &zoom_vsim,
+@@ -343,10 +305,17 @@ static struct twl4030_platform_data zoom_twldata = {
+
+ static int __init omap_i2c_init(void)
+ {
++ omap3_pmic_get_config(&zoom_twldata,
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
++ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, 0);
++
+ if (machine_is_omap_zoom2()) {
+- zoom_audio_data.ramp_delay_value = 3; /* 161 ms */
+- zoom_audio_data.hs_extmute = 1;
+- zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
++ struct twl4030_codec_audio_data *audio_data;
++ audio_data = zoom_twldata.codec->audio;
++
++ audio_data->ramp_delay_value = 3; /* 161 ms */
++ audio_data->hs_extmute = 1;
++ audio_data->set_hs_extmute = zoom2_set_hs_extmute;
+ }
+ omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
+index cf80f4c..9e8decf 100644
+--- a/arch/arm/mach-omap2/twl-common.c
++++ b/arch/arm/mach-omap2/twl-common.c
+@@ -56,6 +56,37 @@ static struct twl4030_usb_data omap4_usb_pdata = {
+ .phy_suspend = omap4430_phy_suspend,
+ };
+
++static struct twl4030_usb_data omap3_usb_pdata = {
++ .usb_mode = T2_USB_MODE_ULPI,
++};
++
++static int omap3_batt_table[] = {
++/* 0 C */
++30800, 29500, 28300, 27100,
++26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
++17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
++11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
++8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
++5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
++4040, 3910, 3790, 3670, 3550
++};
++
++static struct twl4030_bci_platform_data omap3_bci_pdata = {
++ .battery_tmp_tbl = omap3_batt_table,
++ .tblsize = ARRAY_SIZE(omap3_batt_table),
++};
++
++static struct twl4030_madc_platform_data omap3_madc_pdata = {
++ .irq_line = 1,
++};
++
++static struct twl4030_codec_audio_data omap3_audio;
++
++static struct twl4030_codec_data omap3_codec_pdata = {
++ .audio_mclk = 26000000,
++ .audio = &omap3_audio,
++};
++
+ static struct regulator_init_data omap4_vdac_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+@@ -207,3 +238,25 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ !pmic_data->clk32kg)
+ pmic_data->clk32kg = &omap4_clk32kg_idata;
+ }
++
++void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
++ u32 pdata_flags, u32 regulators_flags)
++{
++ if (!pmic_data->irq_base)
++ pmic_data->irq_base = TWL4030_IRQ_BASE;
++ if (!pmic_data->irq_end)
++ pmic_data->irq_end = TWL4030_IRQ_END;
++
++ /* Common platform data configurations */
++ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
++ pmic_data->usb = &omap3_usb_pdata;
++
++ if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
++ pmic_data->bci = &omap3_bci_pdata;
++
++ if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
++ pmic_data->madc = &omap3_madc_pdata;
++
++ if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->codec)
++ pmic_data->codec = &omap3_codec_pdata;
++}
+diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
+index d96c289..3b4b05d 100644
+--- a/arch/arm/mach-omap2/twl-common.h
++++ b/arch/arm/mach-omap2/twl-common.h
+@@ -2,6 +2,9 @@
+ #define __OMAP_PMIC_COMMON__
+
+ #define TWL_COMMON_PDATA_USB (1 << 0)
++#define TWL_COMMON_PDATA_BCI (1 << 1)
++#define TWL_COMMON_PDATA_MADC (1 << 2)
++#define TWL_COMMON_PDATA_AUDIO (1 << 3)
+
+ /* Common LDO regulators for TWL4030/TWL6030 */
+ #define TWL_COMMON_REGULATOR_VDAC (1 << 0)
+@@ -42,6 +45,9 @@ static inline void omap4_pmic_init(const char *pmic_type,
+ omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+ }
+
++void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
++ u32 pdata_flags, u32 regulators_flags);
++
+ void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ u32 pdata_flags, u32 regulators_flags);
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0025-OMAP3-Move-common-regulator-configuration-to-twl-com.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0025-OMAP3-Move-common-regulator-configuration-to-twl-com.patch
--- /dev/null
@@ -0,0 +1,924 @@
+From 8e61cb467b9c0f30cf24f244f176d497d4ce3e2a Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Tue, 7 Jun 2011 11:38:24 +0300
+Subject: [PATCH 025/149] OMAP3: Move common regulator configuration to twl-common
+
+Some regulator config can be moved out from board files,
+since they are close to identical.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 51 ++++----------------------
+ arch/arm/mach-omap2/board-cm-t35.c | 44 ++++------------------
+ arch/arm/mach-omap2/board-devkit8000.c | 22 +----------
+ arch/arm/mach-omap2/board-igep0020.c | 28 +++------------
+ arch/arm/mach-omap2/board-omap3beagle.c | 46 +++---------------------
+ arch/arm/mach-omap2/board-omap3evm.c | 50 ++++----------------------
+ arch/arm/mach-omap2/board-omap3pandora.c | 47 +++++-------------------
+ arch/arm/mach-omap2/board-omap3stalker.c | 50 ++++----------------------
+ arch/arm/mach-omap2/board-omap3touchbook.c | 44 ++++++----------------
+ arch/arm/mach-omap2/board-overo.c | 46 +++---------------------
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 27 +++-----------
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 42 ++--------------------
+ arch/arm/mach-omap2/twl-common.c | 42 +++++++++++++++++++++
+ arch/arm/mach-omap2/twl-common.h | 5 +++
+ 14 files changed, 124 insertions(+), 420 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 8bbd4e0..bd600cf 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -283,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+ };
+
+-static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+ static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+@@ -409,36 +399,6 @@ static struct regulator_init_data sdp3430_vsim = {
+ .consumer_supplies = sdp3430_vsim_supplies,
+ };
+
+-/* VDAC for DSS driving S-Video */
+-static struct regulator_init_data sdp3430_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
+- .consumer_supplies = sdp3430_vdda_dac_supplies,
+-};
+-
+-static struct regulator_init_data sdp3430_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
+- .consumer_supplies = sdp3430_vpll2_supplies,
+-};
+-
+ static struct twl4030_platform_data sdp3430_twldata = {
+ /* platform_data for children goes here */
+ .gpio = &sdp3430_gpio_data,
+@@ -451,16 +411,19 @@ static struct twl4030_platform_data sdp3430_twldata = {
+ .vmmc1 = &sdp3430_vmmc1,
+ .vmmc2 = &sdp3430_vmmc2,
+ .vsim = &sdp3430_vsim,
+- .vdac = &sdp3430_vdac,
+- .vpll2 = &sdp3430_vpll2,
+ };
+
+ static int __init omap3430_i2c_init(void)
+ {
+ /* i2c1 for PMIC only */
+ omap3_pmic_get_config(&sdp3430_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+- TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
++ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++ sdp3430_twldata.vdac->constraints.apply_uV = true;
++ sdp3430_twldata.vpll2->constraints.apply_uV = true;
++ sdp3430_twldata.vpll2->constraints.name = "VDVI";
++
+ omap3_pmic_init("twl4030", &sdp3430_twldata);
+
+ /* i2c2 on camera connector (for sensor control) and optional isp1301 */
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index cb00abc..35891d4 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -343,10 +343,6 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+-static struct regulator_consumer_supply cm_t35_vdac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+ static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
+ REGULATOR_SUPPLY("vdvi", "omapdss"),
+ };
+@@ -381,35 +377,6 @@ static struct regulator_init_data cm_t35_vsim = {
+ .consumer_supplies = cm_t35_vsim_supply,
+ };
+
+-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+-static struct regulator_init_data cm_t35_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdac_supply),
+- .consumer_supplies = cm_t35_vdac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_init_data cm_t35_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdvi_supply),
+- .consumer_supplies = cm_t35_vdvi_supply,
+-};
+-
+ static uint32_t cm_t35_keymap[] = {
+ KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
+ KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
+@@ -493,13 +460,18 @@ static struct twl4030_platform_data cm_t35_twldata = {
+ .gpio = &cm_t35_gpio_data,
+ .vmmc1 = &cm_t35_vmmc1,
+ .vsim = &cm_t35_vsim,
+- .vdac = &cm_t35_vdac,
+- .vpll2 = &cm_t35_vpll2,
+ };
+
+ static void __init cm_t35_init_i2c(void)
+ {
+- omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB, 0);
++ omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ cm_t35_twldata.vpll2->constraints.name = "VDVI";
++ cm_t35_twldata.vpll2->num_consumer_supplies =
++ ARRAY_SIZE(cm_t35_vdvi_supply);
++ cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
++
+ omap3_pmic_init("tps65930", &cm_t35_twldata);
+ }
+
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 364942e..b6002ec 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -186,10 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
+ .default_device = &devkit8000_lcd_device,
+ };
+
+-static struct regulator_consumer_supply devkit8000_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+ static uint32_t board_keymap[] = {
+ KEY(0, 0, KEY_1),
+ KEY(1, 0, KEY_2),
+@@ -289,20 +285,6 @@ static struct regulator_init_data devkit8000_vmmc1 = {
+ .consumer_supplies = devkit8000_vmmc1_supply,
+ };
+
+-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+-static struct regulator_init_data devkit8000_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(devkit8000_vdda_dac_supply),
+- .consumer_supplies = devkit8000_vdda_dac_supply,
+-};
+-
+ /* VPLL1 for digital video outputs */
+ static struct regulator_init_data devkit8000_vpll1 = {
+ .constraints = {
+@@ -336,7 +318,6 @@ static struct twl4030_platform_data devkit8000_twldata = {
+ /* platform_data for children goes here */
+ .gpio = &devkit8000_gpio_data,
+ .vmmc1 = &devkit8000_vmmc1,
+- .vdac = &devkit8000_vdac,
+ .vpll1 = &devkit8000_vpll1,
+ .vio = &devkit8000_vio,
+ .keypad = &devkit8000_kp_data,
+@@ -345,7 +326,8 @@ static struct twl4030_platform_data devkit8000_twldata = {
+ static int __init devkit8000_i2c_init(void)
+ {
+ omap3_pmic_get_config(&devkit8000_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC);
+ omap3_pmic_init("tps65930", &devkit8000_twldata);
+ /* Bus 3 is attached to the DVI port where devices like the pico DLP
+ * projector don't work reliably with 400kHz */
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index e0a6687..35be778 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -479,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
+ .default_device = &igep2_dvi_device,
+ };
+
+-static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+-static struct regulator_init_data igep2_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies),
+- .consumer_supplies = igep2_vpll2_supplies,
+-};
+-
+ static void __init igep2_display_init(void)
+ {
+ int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
+@@ -579,9 +559,11 @@ static void __init igep_i2c_init(void)
+ pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
+
+ igep_twldata.keypad = &igep2_keypad_pdata;
+- igep_twldata.vpll2 = &igep2_vpll2;
+- /* Use common codec data */
+- omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
++ /* Get common pmic data */
++ omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VPLL2);
++ igep_twldata.vpll2->constraints.apply_uV = true;
++ igep_twldata.vpll2->constraints.name = "VDVI";
+ }
+
+ omap3_pmic_init("twl4030", &igep_twldata);
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index ec61e9c..34f8411 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -209,15 +209,6 @@ static struct omap_dss_board_info beagle_dss_data = {
+ .default_device = &beagle_dvi_device,
+ };
+
+-static struct regulator_consumer_supply beagle_vdac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+ static void __init beagle_display_init(void)
+ {
+ int r;
+@@ -351,42 +342,11 @@ static struct regulator_init_data beagle_vsim = {
+ .consumer_supplies = beagle_vsim_supply,
+ };
+
+-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+-static struct regulator_init_data beagle_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(beagle_vdac_supply),
+- .consumer_supplies = beagle_vdac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_init_data beagle_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies),
+- .consumer_supplies = beagle_vdvi_supplies,
+-};
+-
+ static struct twl4030_platform_data beagle_twldata = {
+ /* platform_data for children goes here */
+ .gpio = &beagle_gpio_data,
+ .vmmc1 = &beagle_vmmc1,
+ .vsim = &beagle_vsim,
+- .vdac = &beagle_vdac,
+- .vpll2 = &beagle_vpll2,
+ };
+
+ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+@@ -398,7 +358,11 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+ static int __init omap3_beagle_i2c_init(void)
+ {
+ omap3_pmic_get_config(&beagle_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ beagle_twldata.vpll2->constraints.name = "VDVI";
++
+ omap3_pmic_init("twl4030", &beagle_twldata);
+ /* Bus 3 is attached to the DVI port where devices like the pico DLP
+ * projector don't work reliably with 400kHz */
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 1ca298a..c452b3f 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -430,45 +430,6 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
+ .rep = 1,
+ };
+
+-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-/* VDAC for DSS driving S-Video */
+-static struct regulator_init_data omap3_evm_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vdda_dac_supply),
+- .consumer_supplies = omap3_evm_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+-static struct regulator_init_data omap3_evm_vpll2 = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
+- .consumer_supplies = omap3_evm_vpll2_supplies,
+-};
+-
+ /* ads7846 on SPI */
+ static struct regulator_consumer_supply omap3evm_vio_supply[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+@@ -535,8 +496,6 @@ static struct twl4030_platform_data omap3evm_twldata = {
+ /* platform_data for children goes here */
+ .keypad = &omap3evm_kp_data,
+ .gpio = &omap3evm_gpio_data,
+- .vdac = &omap3_evm_vdac,
+- .vpll2 = &omap3_evm_vpll2,
+ .vio = &omap3evm_vio,
+ .vmmc1 = &omap3evm_vmmc1,
+ .vsim = &omap3evm_vsim,
+@@ -545,8 +504,13 @@ static struct twl4030_platform_data omap3evm_twldata = {
+ static int __init omap3_evm_i2c_init(void)
+ {
+ omap3_pmic_get_config(&omap3evm_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+- TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
++ TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ omap3evm_twldata.vdac->constraints.apply_uV = true;
++ omap3evm_twldata.vpll2->constraints.apply_uV = true;
++
+ omap3_pmic_init("twl4030", &omap3evm_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index f5abf76..080d7bd 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -332,10 +332,6 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
+ };
+
+-static struct regulator_consumer_supply pandora_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
+ REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+@@ -391,36 +387,6 @@ static struct regulator_init_data pandora_vmmc2 = {
+ .consumer_supplies = pandora_vmmc2_supply,
+ };
+
+-/* VDAC for DSS driving S-Video */
+-static struct regulator_init_data pandora_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(pandora_vdda_dac_supply),
+- .consumer_supplies = pandora_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_init_data pandora_vpll2 = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
+- .consumer_supplies = pandora_vdds_supplies,
+-};
+-
+ /* VAUX1 for LCD */
+ static struct regulator_init_data pandora_vaux1 = {
+ .constraints = {
+@@ -514,8 +480,6 @@ static struct twl4030_platform_data omap3pandora_twldata = {
+ .gpio = &omap3pandora_gpio_data,
+ .vmmc1 = &pandora_vmmc1,
+ .vmmc2 = &pandora_vmmc2,
+- .vdac = &pandora_vdac,
+- .vpll2 = &pandora_vpll2,
+ .vaux1 = &pandora_vaux1,
+ .vaux2 = &pandora_vaux2,
+ .vaux4 = &pandora_vaux4,
+@@ -534,7 +498,16 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
+ static int __init omap3pandora_i2c_init(void)
+ {
+ omap3_pmic_get_config(&omap3pandora_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ omap3pandora_twldata.vdac->constraints.apply_uV = true;
++
++ omap3pandora_twldata.vpll2->constraints.apply_uV = true;
++ omap3pandora_twldata.vpll2->num_consumer_supplies =
++ ARRAY_SIZE(pandora_vdds_supplies);
++ omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
++
+ omap3_pmic_init("tps65950", &omap3pandora_twldata);
+ /* i2c2 pins are not connected */
+ omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 6e59e59..8e10498 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -383,52 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
+ .rep = 1,
+ };
+
+-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-/* VDAC for DSS driving S-Video */
+-static struct regulator_init_data omap3_stalker_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vdda_dac_supply),
+- .consumer_supplies = omap3_stalker_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+-static struct regulator_init_data omap3_stalker_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
+- .consumer_supplies = omap3_stalker_vpll2_supplies,
+-};
+-
+ static struct twl4030_platform_data omap3stalker_twldata = {
+ /* platform_data for children goes here */
+ .keypad = &omap3stalker_kp_data,
+ .gpio = &omap3stalker_gpio_data,
+- .vdac = &omap3_stalker_vdac,
+- .vpll2 = &omap3_stalker_vpll2,
+ .vmmc1 = &omap3stalker_vmmc1,
+ .vsim = &omap3stalker_vsim,
+ };
+@@ -451,7 +409,13 @@ static int __init omap3_stalker_i2c_init(void)
+ {
+ omap3_pmic_get_config(&omap3stalker_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+- TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ omap3stalker_twldata.vdac->constraints.apply_uV = true;
++ omap3stalker_twldata.vpll2->constraints.apply_uV = true;
++ omap3stalker_twldata.vpll2->constraints.name = "VDVI";
++
+ omap3_pmic_init("twl4030", &omap3stalker_twldata);
+ omap_register_i2c_bus(2, 400, NULL, 0);
+ omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 717972c..852ea04 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -206,42 +206,11 @@ static struct regulator_init_data touchbook_vsim = {
+ .consumer_supplies = touchbook_vsim_supply,
+ };
+
+-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+-static struct regulator_init_data touchbook_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(touchbook_vdac_supply),
+- .consumer_supplies = touchbook_vdac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_init_data touchbook_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(touchbook_vdvi_supply),
+- .consumer_supplies = touchbook_vdvi_supply,
+-};
+-
+ static struct twl4030_platform_data touchbook_twldata = {
+ /* platform_data for children goes here */
+ .gpio = &touchbook_gpio_data,
+ .vmmc1 = &touchbook_vmmc1,
+ .vsim = &touchbook_vsim,
+- .vdac = &touchbook_vdac,
+- .vpll2 = &touchbook_vpll2,
+ };
+
+ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
+@@ -254,7 +223,18 @@ static int __init omap3_touchbook_i2c_init(void)
+ {
+ /* Standard TouchBook bus */
+ omap3_pmic_get_config(&touchbook_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ touchbook_twldata.vdac->num_consumer_supplies =
++ ARRAY_SIZE(touchbook_vdac_supply);
++ touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
++
++ touchbook_twldata.vpll2->constraints.name = "VDVI";
++ touchbook_twldata.vpll2->num_consumer_supplies =
++ ARRAY_SIZE(touchbook_vdvi_supply);
++ touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
++
+ omap3_pmic_init("twl4030", &touchbook_twldata);
+ /* Additional TouchBook bus */
+ omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 776b444..f1f18d0 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -265,15 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
+ .default_device = &overo_dvi_device,
+ };
+
+-static struct regulator_consumer_supply overo_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+ static struct mtd_partition overo_nand_partitions[] = {
+ {
+ .name = "xloader",
+@@ -447,46 +438,19 @@ static struct regulator_init_data overo_vmmc1 = {
+ .consumer_supplies = overo_vmmc1_supply,
+ };
+
+-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+-static struct regulator_init_data overo_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(overo_vdda_dac_supply),
+- .consumer_supplies = overo_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_init_data overo_vpll2 = {
+- .constraints = {
+- .name = "VDVI",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply),
+- .consumer_supplies = overo_vdds_dsi_supply,
+-};
+-
+ static struct twl4030_platform_data overo_twldata = {
+ .gpio = &overo_gpio_data,
+ .vmmc1 = &overo_vmmc1,
+- .vdac = &overo_vdac,
+- .vpll2 = &overo_vpll2,
+ };
+
+ static int __init overo_i2c_init(void)
+ {
+ omap3_pmic_get_config(&overo_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
++
++ overo_twldata.vpll2->constraints.name = "VDVI";
++
+ omap3_pmic_init("tps65950", &overo_twldata);
+ /* i2c2 pins are used for gpio */
+ omap_register_i2c_bus(3, 400, NULL, 0);
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index 75be074..bdb24db 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -394,10 +394,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
+ REGULATOR_SUPPLY("vdd", "2-0063"),
+ };
+
+-static struct regulator_consumer_supply rx51_vdac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+ static struct regulator_init_data rx51_vaux1 = {
+ .constraints = {
+ .name = "V28",
+@@ -514,21 +510,6 @@ static struct regulator_init_data rx51_vsim = {
+ .consumer_supplies = rx51_vsim_supply,
+ };
+
+-static struct regulator_init_data rx51_vdac = {
+- .constraints = {
+- .name = "VDAC",
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .apply_uV = true,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(rx51_vdac_supply),
+- .consumer_supplies = rx51_vdac_supply,
+-};
+-
+ static struct regulator_init_data rx51_vio = {
+ .constraints = {
+ .min_uV = 1800000,
+@@ -781,7 +762,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
+ .vaux4 = &rx51_vaux4,
+ .vmmc1 = &rx51_vmmc1,
+ .vsim = &rx51_vsim,
+- .vdac = &rx51_vdac,
+ .vio = &rx51_vio,
+ };
+
+@@ -838,7 +818,12 @@ static int __init rx51_i2c_init(void)
+ }
+ rx51_twldata.vmmc2 = &rx51_vmmc2;
+ omap3_pmic_get_config(&rx51_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
++ TWL_COMMON_REGULATOR_VDAC);
++
++ rx51_twldata.vdac->constraints.apply_uV = true;
++ rx51_twldata.vdac->constraints.name = "VDAC";
++
+ omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+ omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
+ ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index 6d8df1b..13a6442 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -226,41 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+-};
+-
+-static struct regulator_consumer_supply zoom_vdda_dac_supply[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+-};
+-
+-static struct regulator_init_data zoom_vpll2 = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies),
+- .consumer_supplies = zoom_vpll2_supplies,
+-};
+-
+-static struct regulator_init_data zoom_vdac = {
+- .constraints = {
+- .min_uV = 1800000,
+- .max_uV = 1800000,
+- .valid_modes_mask = REGULATOR_MODE_NORMAL
+- | REGULATOR_MODE_STANDBY,
+- .valid_ops_mask = REGULATOR_CHANGE_MODE
+- | REGULATOR_CHANGE_STATUS,
+- },
+- .num_consumer_supplies = ARRAY_SIZE(zoom_vdda_dac_supply),
+- .consumer_supplies = zoom_vdda_dac_supply,
+-};
+-
+ static int zoom_twl_gpio_setup(struct device *dev,
+ unsigned gpio, unsigned ngpio)
+ {
+@@ -299,15 +264,14 @@ static struct twl4030_platform_data zoom_twldata = {
+ .vmmc1 = &zoom_vmmc1,
+ .vmmc2 = &zoom_vmmc2,
+ .vsim = &zoom_vsim,
+- .vpll2 = &zoom_vpll2,
+- .vdac = &zoom_vdac,
+ };
+
+ static int __init omap_i2c_init(void)
+ {
+ omap3_pmic_get_config(&zoom_twldata,
+- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+- TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, 0);
++ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
++ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
++ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ if (machine_is_omap_zoom2()) {
+ struct twl4030_codec_audio_data *audio_data;
+diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
+index 9e8decf..3aaa46f 100644
+--- a/arch/arm/mach-omap2/twl-common.c
++++ b/arch/arm/mach-omap2/twl-common.c
+@@ -87,6 +87,41 @@ static struct twl4030_codec_data omap3_codec_pdata = {
+ .audio = &omap3_audio,
+ };
+
++static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
++};
++
++static struct regulator_init_data omap3_vdac_idata = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 1800000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
++ .consumer_supplies = omap3_vdda_dac_supplies,
++};
++
++static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
++};
++
++static struct regulator_init_data omap3_vpll2_idata = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 1800000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
++ .consumer_supplies = omap3_vpll2_supplies,
++};
++
+ static struct regulator_init_data omap4_vdac_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+@@ -259,4 +294,11 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+
+ if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->codec)
+ pmic_data->codec = &omap3_codec_pdata;
++
++ /* Common regulator configurations */
++ if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
++ pmic_data->vdac = &omap3_vdac_idata;
++
++ if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
++ pmic_data->vpll2 = &omap3_vpll2_idata;
+ }
+diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
+index 3b4b05d..5e83a5b 100644
+--- a/arch/arm/mach-omap2/twl-common.h
++++ b/arch/arm/mach-omap2/twl-common.h
+@@ -21,6 +21,11 @@
+ #define TWL_COMMON_REGULATOR_VUSB (1 << 9)
+ #define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
+
++/* TWL4030 LDO regulators */
++#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
++#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
++
++
+ struct twl4030_platform_data;
+
+ void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0026-omap-mcbsp-Remove-rx_-tx_word_length-variables.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0026-omap-mcbsp-Remove-rx_-tx_word_length-variables.patch
--- /dev/null
@@ -0,0 +1,45 @@
+From 1274a75667a90dd8deeeee99911e4528ffd57b21 Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jhnikula@gmail.com>
+Date: Fri, 1 Jul 2011 08:52:26 +0000
+Subject: [PATCH 026/149] omap: mcbsp: Remove rx_/tx_word_length variables
+
+These variables got unused after ("omap: mcbsp: Drop in-driver transfer
+support") but was noticed only afterwards.
+
+Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/mcbsp.h | 2 --
+ arch/arm/plat-omap/mcbsp.c | 3 ---
+ 2 files changed, 0 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 6c53508..63464ad 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -385,8 +385,6 @@ struct omap_mcbsp {
+ void __iomem *io_base;
+ u8 id;
+ u8 free;
+- omap_mcbsp_word_length rx_word_length;
+- omap_mcbsp_word_length tx_word_length;
+
+ int rx_irq;
+ int tx_irq;
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 455eadc..3c1fbdc 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -869,9 +869,6 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
+ if (cpu_is_omap34xx())
+ omap_st_start(mcbsp);
+
+- mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
+- mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
+-
+ /* Only enable SRG, if McBSP is master */
+ w = MCBSP_READ_CACHE(mcbsp, PCR0);
+ if (w & (FSXM | FSRM | CLKXM | CLKRM))
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0027-omap-mcbsp-Remove-port-number-enums.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0027-omap-mcbsp-Remove-port-number-enums.patch
--- /dev/null
@@ -0,0 +1,68 @@
+From 22df47275fc045af1cc0ac0fd4cd44b4b0021729 Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jhnikula@gmail.com>
+Date: Fri, 1 Jul 2011 08:52:27 +0000
+Subject: [PATCH 027/149] omap: mcbsp: Remove port number enums
+
+These McBSP port number enums are used only in two places in the McBSP code
+so we may remove then and just use numeric values like rest of the code does.
+
+Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/mcbsp.c | 4 ++--
+ arch/arm/plat-omap/include/plat/mcbsp.h | 10 +---------
+ 2 files changed, 3 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
+index d9af981..ab7395d 100644
+--- a/arch/arm/mach-omap1/mcbsp.c
++++ b/arch/arm/mach-omap1/mcbsp.c
+@@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
+ * On 1510, 1610 and 1710, McBSP1 and McBSP3
+ * are DSP public peripherals.
+ */
+- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
++ if (id == 0 || id == 2) {
+ if (dsp_use++ == 0) {
+ api_clk = clk_get(NULL, "api_ck");
+ dsp_clk = clk_get(NULL, "dsp_ck");
+@@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
+
+ static void omap1_mcbsp_free(unsigned int id)
+ {
+- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
++ if (id == 0 || id == 2) {
+ if (--dsp_use == 0) {
+ if (!IS_ERR(api_clk)) {
+ clk_disable(api_clk);
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 63464ad..9882c65 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -33,7 +33,7 @@
+ #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
+ static struct platform_device omap_mcbsp##port_nr = { \
+ .name = "omap-mcbsp-dai", \
+- .id = OMAP_MCBSP##port_nr, \
++ .id = port_nr - 1, \
+ }
+
+ #define MCBSP_CONFIG_TYPE2 0x2
+@@ -332,14 +332,6 @@ struct omap_mcbsp_reg_cfg {
+ };
+
+ typedef enum {
+- OMAP_MCBSP1 = 0,
+- OMAP_MCBSP2,
+- OMAP_MCBSP3,
+- OMAP_MCBSP4,
+- OMAP_MCBSP5
+-} omap_mcbsp_id;
+-
+-typedef enum {
+ OMAP_MCBSP_WORD_8 = 0,
+ OMAP_MCBSP_WORD_12,
+ OMAP_MCBSP_WORD_16,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0028-OMAP-dmtimer-add-missing-include.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0028-OMAP-dmtimer-add-missing-include.patch
--- /dev/null
@@ -0,0 +1,31 @@
+From 9a21aa1140e4c3c5621726e6eb5d3bd91ea85a3e Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 18:00:25 -0600
+Subject: [PATCH 028/149] OMAP: dmtimer: add missing include
+
+After commit caf64f2fdc48472995d40656eb1a75524c464447 ("omap: Make a subset
+of dmtimer functions into inline functions"),
+arch/arm/plat-omap/include/plat/dmtimer.h is missing an include of linux/io.h
+- add it.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/dmtimer.h | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index d0f3a2d..eb5d16c 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -34,6 +34,7 @@
+
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/io.h>
+
+ #ifndef __ASM_ARCH_DMTIMER_H
+ #define __ASM_ARCH_DMTIMER_H
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0029-OMAP2-hwmod-Fix-smart-standby-wakeup-support.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0029-OMAP2-hwmod-Fix-smart-standby-wakeup-support.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0029-OMAP2-hwmod-Fix-smart-standby-wakeup-support.patch
@@ -0,0 +1,130 @@
+From 6c2e1f27c319dfd7655b820752f5b347c331dc06 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:00 +0200
+Subject: [PATCH 029/149] OMAP2+: hwmod: Fix smart-standby + wakeup support
+
+The commit 86009eb326afde34ffdc5648cd344aa86b8d58d4 was adding
+the wakeup support for new OMAP4 IPs. This support is incomplete for
+busmaster IPs that need as well to use smart-standby with wakeup.
+
+This new standbymode is suported on HSI and USB_HOST_FS for the moment.
+
+Add the new MSTANDBY_SMART_WKUP flag to mark the IPs that support this
+capability.
+
+Enable this new mode when applicable in _enable_wakeup, _disable_wakeup,
+_enable_sysc and _idle_sysc.
+
+The omap_hwmod_44xx_data.c will have to be updated to add this new flag.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 34 +++++++++++++++++++++----
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 +-
+ 2 files changed, 29 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 293fa6c..384d3c3 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -391,7 +391,8 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+
+ if (!oh->class->sysc ||
+ !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
++ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
++ (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
+ return -EINVAL;
+
+ if (!oh->class->sysc->sysc_fields) {
+@@ -405,6 +406,8 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+
+ if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
++ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
++ _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+
+ /* XXX test pwrdm_get_wken for this hwmod's subsystem */
+
+@@ -426,7 +429,8 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+
+ if (!oh->class->sysc ||
+ !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
++ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
++ (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
+ return -EINVAL;
+
+ if (!oh->class->sysc->sysc_fields) {
+@@ -440,6 +444,8 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+
+ if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
++ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
++ _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+
+ /* XXX test pwrdm_get_wken for this hwmod's subsystem */
+
+@@ -781,8 +787,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
+ }
+
+ if (sf & SYSC_HAS_MIDLEMODE) {
+- idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
+- HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
++ if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
++ idlemode = HWMOD_IDLEMODE_NO;
++ } else {
++ if (sf & SYSC_HAS_ENAWAKEUP)
++ _enable_wakeup(oh, &v);
++ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
++ idlemode = HWMOD_IDLEMODE_SMART_WKUP;
++ else
++ idlemode = HWMOD_IDLEMODE_SMART;
++ }
+ _set_master_standbymode(oh, idlemode, &v);
+ }
+
+@@ -840,8 +854,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
+ }
+
+ if (sf & SYSC_HAS_MIDLEMODE) {
+- idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
+- HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
++ if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
++ idlemode = HWMOD_IDLEMODE_FORCE;
++ } else {
++ if (sf & SYSC_HAS_ENAWAKEUP)
++ _enable_wakeup(oh, &v);
++ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
++ idlemode = HWMOD_IDLEMODE_SMART_WKUP;
++ else
++ idlemode = HWMOD_IDLEMODE_SMART;
++ }
+ _set_master_standbymode(oh, idlemode, &v);
+ }
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 1adea9c..e93438c 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+ #define HWMOD_IDLEMODE_FORCE (1 << 0)
+ #define HWMOD_IDLEMODE_NO (1 << 1)
+ #define HWMOD_IDLEMODE_SMART (1 << 2)
+-/* Slave idle mode flag only */
+ #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
+
+ /**
+@@ -258,6 +257,7 @@ struct omap_hwmod_ocp_if {
+ #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
+ #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
+ #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
++#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
+
+ /* omap_hwmod_sysconfig.sysc_flags capability flags */
+ #define SYSC_HAS_AUTOIDLE (1 << 0)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0030-OMAP4-hwmod-data-Add-MSTANDBY_SMART_WKUP-flag.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0030-OMAP4-hwmod-data-Add-MSTANDBY_SMART_WKUP-flag.patch
--- /dev/null
@@ -0,0 +1,61 @@
+From b487cae55998f8e6baa7047eeb89a193cd218a8c Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:01 +0200
+Subject: [PATCH 030/149] OMAP4: hwmod data: Add MSTANDBY_SMART_WKUP flag
+
+Add the flag to every IPs that support it to allow the
+framework to enable it instead of the SMART_STANDBY default
+mode.
+Without that, an IP with busmaster capability will not
+be able to wakeup the interconnect at all.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 9 +++++----
+ 1 files changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index e1c69ff..8cbbfbf 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -660,7 +660,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
++ MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+ };
+
+@@ -2044,7 +2045,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+- MSTANDBY_SMART),
++ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+@@ -2446,7 +2447,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+- MSTANDBY_SMART),
++ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+ };
+
+@@ -3420,7 +3421,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+- MSTANDBY_SMART),
++ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0031-OMAP2-hwmod-Enable-module-in-shutdown-to-access-sysc.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0031-OMAP2-hwmod-Enable-module-in-shutdown-to-access-sysc.patch
--- /dev/null
@@ -0,0 +1,37 @@
+From 4795bf332f1d577bc6e37cf54d36de26b5ea09dc Mon Sep 17 00:00:00 2001
+From: Miguel Vadillo <vadillo@ti.com>
+Date: Fri, 1 Jul 2011 22:54:02 +0200
+Subject: [PATCH 031/149] OMAP2+: hwmod: Enable module in shutdown to access sysconfig
+
+When calling the shutdown, the module may be already in idle.
+Accessing the sysconfig register will then lead to a crash.
+In that case, re-enable the module in order to allow the access
+to the sysconfig register.
+
+Signed-off-by: Miguel Vadillo <vadillo@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 5 ++++-
+ 1 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 384d3c3..cbc2a8a 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1396,8 +1396,11 @@ static int _shutdown(struct omap_hwmod *oh)
+ }
+ }
+
+- if (oh->class->sysc)
++ if (oh->class->sysc) {
++ if (oh->_state == _HWMOD_STATE_IDLE)
++ _enable(oh);
+ _shutdown_sysc(oh);
++ }
+
+ /*
+ * If an IP contains only one HW reset line, then assert it
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0032-OMAP2-hwmod-Do-not-write-the-enawakeup-bit-if-SYSC_H.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0032-OMAP2-hwmod-Do-not-write-the-enawakeup-bit-if-SYSC_H.patch
--- /dev/null
@@ -0,0 +1,65 @@
+From aa6d37a4dfb78110b79632cd7829750f2dd6b274 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:03 +0200
+Subject: [PATCH 032/149] OMAP2+: hwmod: Do not write the enawakeup bit if SYSC_HAS_ENAWAKEUP is not set
+
+The Type 2 type of IPs will not have any enawakeup bit in their sysconfig.
+Writing to that bit will instead trigger a softreset.
+Check the flag to write this bit only if the module supports it.
+
+Reported-by: Miguel Vadillo <vadillo@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 14 ++++----------
+ 1 files changed, 4 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index cbc2a8a..3800084 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -387,8 +387,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
+ */
+ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+ {
+- u32 wakeup_mask;
+-
+ if (!oh->class->sysc ||
+ !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+@@ -400,9 +398,8 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+ return -EINVAL;
+ }
+
+- wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
+-
+- *v |= wakeup_mask;
++ if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
++ *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
+
+ if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+@@ -425,8 +422,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+ */
+ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+ {
+- u32 wakeup_mask;
+-
+ if (!oh->class->sysc ||
+ !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+@@ -438,9 +433,8 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+ return -EINVAL;
+ }
+
+- wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
+-
+- *v &= ~wakeup_mask;
++ if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
++ *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
+
+ if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0033-OMAP2-hwmod-Remove-_populate_mpu_rt_base-warning.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0033-OMAP2-hwmod-Remove-_populate_mpu_rt_base-warning.patch
--- /dev/null
@@ -0,0 +1,33 @@
+From 045a9fc0357b8409ab4f9e549f20123c3ac7b353 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:04 +0200
+Subject: [PATCH 033/149] OMAP2+: hwmod: Remove _populate_mpu_rt_base warning
+
+It is perfectly valid for some hwmod to not have any
+register target address for sysconfig. This is especially
+true for interconnect hwmods.
+Remove the warning.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 3800084..f401417 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1704,9 +1704,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ return 0;
+
+ oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+- if (!oh->_mpu_rt_va)
+- pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
+- __func__, oh->name);
+
+ return 0;
+ }
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0034-OMAP2-hwmod-Fix-the-HW-reset-management.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0034-OMAP2-hwmod-Fix-the-HW-reset-management.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0034-OMAP2-hwmod-Fix-the-HW-reset-management.patch
@@ -0,0 +1,87 @@
+From f9c8ace6aaf0d0c9ccac3c22226340db2cabdf17 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:05 +0200
+Subject: [PATCH 034/149] OMAP2+: hwmod: Fix the HW reset management
+
+The HW reset must be de-assert after the clocks are enabled
+but before waiting for the target to be ready. Otherwise the
+reset might not work properly since the clock is not running
+to proceed the reset.
+
+De-assert the reset after _enable_clocks and before
+_wait_target_ready.
+Re-assert it only when the clocks are disabled.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 32 ++++++++++++++++----------------
+ 1 files changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index f401417..df91bb1 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1250,15 +1250,6 @@ static int _enable(struct omap_hwmod *oh)
+
+ pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+
+- /*
+- * If an IP contains only one HW reset line, then de-assert it in order
+- * to allow to enable the clocks. Otherwise the PRCM will return
+- * Intransition status, and the init will failed.
+- */
+- if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+- oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+- _deassert_hardreset(oh, oh->rst_lines[0].name);
+-
+ /* Mux pins for device runtime if populated */
+ if (oh->mux && (!oh->mux->enabled ||
+ ((oh->_state == _HWMOD_STATE_IDLE) &&
+@@ -1268,6 +1259,15 @@ static int _enable(struct omap_hwmod *oh)
+ _add_initiator_dep(oh, mpu_oh);
+ _enable_clocks(oh);
+
++ /*
++ * If an IP contains only one HW reset line, then de-assert it in order
++ * to allow the module state transition. Otherwise the PRCM will return
++ * Intransition status, and the init will failed.
++ */
++ if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
++ oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
++ _deassert_hardreset(oh, oh->rst_lines[0].name);
++
+ r = _wait_target_ready(oh);
+ if (!r) {
+ oh->_state = _HWMOD_STATE_ENABLED;
+@@ -1396,13 +1396,6 @@ static int _shutdown(struct omap_hwmod *oh)
+ _shutdown_sysc(oh);
+ }
+
+- /*
+- * If an IP contains only one HW reset line, then assert it
+- * before disabling the clocks and shutting down the IP.
+- */
+- if (oh->rst_lines_cnt == 1)
+- _assert_hardreset(oh, oh->rst_lines[0].name);
+-
+ /* clocks and deps are already disabled in idle */
+ if (oh->_state == _HWMOD_STATE_ENABLED) {
+ _del_initiator_dep(oh, mpu_oh);
+@@ -1411,6 +1404,13 @@ static int _shutdown(struct omap_hwmod *oh)
+ }
+ /* XXX Should this code also force-disable the optional clocks? */
+
++ /*
++ * If an IP contains only one HW reset line, then assert it
++ * after disabling the clocks and before shutting down the IP.
++ */
++ if (oh->rst_lines_cnt == 1)
++ _assert_hardreset(oh, oh->rst_lines[0].name);
++
+ /* Mux pins to safe mode or use populated off mode values */
+ if (oh->mux)
+ omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0035-OMAP-hwmod-Add-warnings-if-enable-failed.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0035-OMAP-hwmod-Add-warnings-if-enable-failed.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0035-OMAP-hwmod-Add-warnings-if-enable-failed.patch
@@ -0,0 +1,30 @@
+From a713416ce6fee5ffd2f5e00d539d86d9be9d8cdc Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:06 +0200
+Subject: [PATCH 035/149] OMAP: hwmod: Add warnings if enable failed
+
+Change the debug into warning to check what IPs are failing.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index df91bb1..64e9830 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -944,6 +944,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
+
+ if (!ret)
+ oh->_state = _HWMOD_STATE_CLKS_INITED;
++ else
++ pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
+
+ return ret;
+ }
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0036-OMAP-hwmod-Move-pr_debug-to-improve-the-readability.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0036-OMAP-hwmod-Move-pr_debug-to-improve-the-readability.patch
--- /dev/null
@@ -0,0 +1,95 @@
+From 57560af36861b7010fae509f2ddd75127c0c45df Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 1 Jul 2011 22:54:07 +0200
+Subject: [PATCH 036/149] OMAP: hwmod: Move pr_debug to improve the readability
+
+Move the pr_debug at the top of the function
+to trace the entry even if the first test is failing.
+That help understanding that we entered the function
+but failed in it.
+
+Move the _enable last part out of the test to reduce
+indentation and improve readability.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 32 +++++++++++++++++---------------
+ 1 files changed, 17 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 64e9830..e530bcb 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1242,6 +1242,8 @@ static int _enable(struct omap_hwmod *oh)
+ {
+ int r;
+
++ pr_debug("omap_hwmod: %s: enabling\n", oh->name);
++
+ if (oh->_state != _HWMOD_STATE_INITIALIZED &&
+ oh->_state != _HWMOD_STATE_IDLE &&
+ oh->_state != _HWMOD_STATE_DISABLED) {
+@@ -1250,8 +1252,6 @@ static int _enable(struct omap_hwmod *oh)
+ return -EINVAL;
+ }
+
+- pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+-
+ /* Mux pins for device runtime if populated */
+ if (oh->mux && (!oh->mux->enabled ||
+ ((oh->_state == _HWMOD_STATE_IDLE) &&
+@@ -1271,19 +1271,21 @@ static int _enable(struct omap_hwmod *oh)
+ _deassert_hardreset(oh, oh->rst_lines[0].name);
+
+ r = _wait_target_ready(oh);
+- if (!r) {
+- oh->_state = _HWMOD_STATE_ENABLED;
+-
+- /* Access the sysconfig only if the target is ready */
+- if (oh->class->sysc) {
+- if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
+- _update_sysc_cache(oh);
+- _enable_sysc(oh);
+- }
+- } else {
+- _disable_clocks(oh);
++ if (r) {
+ pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
+ oh->name, r);
++ _disable_clocks(oh);
++
++ return r;
++ }
++
++ oh->_state = _HWMOD_STATE_ENABLED;
++
++ /* Access the sysconfig only if the target is ready */
++ if (oh->class->sysc) {
++ if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
++ _update_sysc_cache(oh);
++ _enable_sysc(oh);
+ }
+
+ return r;
+@@ -1299,14 +1301,14 @@ static int _enable(struct omap_hwmod *oh)
+ */
+ static int _idle(struct omap_hwmod *oh)
+ {
++ pr_debug("omap_hwmod: %s: idling\n", oh->name);
++
+ if (oh->_state != _HWMOD_STATE_ENABLED) {
+ WARN(1, "omap_hwmod: %s: idle state can only be entered from "
+ "enabled state\n", oh->name);
+ return -EINVAL;
+ }
+
+- pr_debug("omap_hwmod: %s: idling\n", oh->name);
+-
+ if (oh->class->sysc)
+ _idle_sysc(oh);
+ _del_initiator_dep(oh, mpu_oh);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0037-omap_hwmod-use-a-null-structure-record-to-terminate-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0037-omap_hwmod-use-a-null-structure-record-to-terminate-.patch
--- /dev/null
@@ -0,0 +1,3529 @@
+From a0e59db8c28f84434d699fbbf70f56f37db3df00 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:05 -0600
+Subject: [PATCH 037/149] omap_hwmod: use a null structure record to terminate omap_hwmod_addr_space arrays
+
+Previously, struct omap_hwmod_addr_space arrays were unterminated; and
+users of these arrays used the ARRAY_SIZE() macro to determine the
+length of the array. However, ARRAY_SIZE() only works when the array
+is in the same scope as the macro user.
+
+So far this hasn't been a problem. However, to reduce duplicated
+data, a subsequent patch will move common data to a separate, shared
+file. When this is done, ARRAY_SIZE() will no longer be usable.
+
+This patch removes ARRAY_SIZE() usage for struct omap_hwmod_addr_space
+arrays and uses a null structure member as the array terminator
+instead.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 45 ++++++--
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 66 +++++-----
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 83 ++++++-------
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 108 ++++++++--------
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 170 +++++++++++++-------------
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 -
+ 6 files changed, 249 insertions(+), 225 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index e530bcb..73599f0 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -2,6 +2,7 @@
+ * omap_hwmod implementation for OMAP2/3/4
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * Paul Walmsley, Benoît Cousson, Kevin Hilman
+ *
+@@ -678,6 +679,29 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
+ }
+
+ /**
++ * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
++ * @oh: struct omap_hwmod *oh
++ *
++ * Count and return the number of address space ranges associated with
++ * the hwmod @oh. Used to allocate struct resource data. Returns 0
++ * if @oh is NULL.
++ */
++static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
++{
++ struct omap_hwmod_addr_space *mem;
++ int i = 0;
++
++ if (!os || !os->addr)
++ return 0;
++
++ do {
++ mem = &os->addr[i++];
++ } while (mem->pa_start != mem->pa_end);
++
++ return i;
++}
++
++/**
+ * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
+ * @oh: struct omap_hwmod *
+ *
+@@ -722,8 +746,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+ {
+ struct omap_hwmod_ocp_if *os;
+ struct omap_hwmod_addr_space *mem;
+- int i;
+- int found = 0;
++ int i = 0, found = 0;
+ void __iomem *va_start;
+
+ if (!oh || oh->slaves_cnt == 0)
+@@ -731,12 +754,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+
+ os = oh->slaves[index];
+
+- for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
+- if (mem->flags & ADDR_TYPE_RT) {
++ if (!os->addr)
++ return NULL;
++
++ do {
++ mem = &os->addr[i++];
++ if (mem->flags & ADDR_TYPE_RT)
+ found = 1;
+- break;
+- }
+- }
++ } while (!found && mem->pa_start != mem->pa_end);
+
+ if (found) {
+ va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+@@ -1962,7 +1987,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
+
+ for (i = 0; i < oh->slaves_cnt; i++)
+- ret += oh->slaves[i]->addr_cnt;
++ ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+
+ return ret;
+ }
+@@ -2002,10 +2027,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+
+ for (i = 0; i < oh->slaves_cnt; i++) {
+ struct omap_hwmod_ocp_if *os;
++ int addr_cnt;
+
+ os = oh->slaves[i];
++ addr_cnt = _count_ocp_if_addr_spaces(os);
+
+- for (j = 0; j < os->addr_cnt; j++) {
++ for (j = 0; j < addr_cnt; j++) {
+ (res + r)->name = (os->addr + j)->name;
+ (res + r)->start = (os->addr + j)->pa_start;
+ (res + r)->end = (os->addr + j)->pa_end;
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index c4d0ae8..1a7ce3e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1,7 +1,7 @@
+ /*
+ * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
+ *
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -120,6 +120,7 @@ static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+ .pa_end = 0x480980ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+@@ -127,7 +128,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+ .slave = &omap2420_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+ .addr = omap2420_mcspi1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -138,6 +138,7 @@ static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
+ .pa_end = 0x4809a0ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+@@ -145,7 +146,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+ .slave = &omap2420_mcspi2_hwmod,
+ .clk = "mcspi2_ick",
+ .addr = omap2420_mcspi2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -163,6 +163,7 @@ static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
+ .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+@@ -170,7 +171,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+ .slave = &omap2420_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = omap2420_uart1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -181,6 +181,7 @@ static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
+ .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+@@ -188,7 +189,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+ .slave = &omap2420_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = omap2420_uart2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -199,6 +199,7 @@ static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
+ .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+@@ -206,7 +207,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .slave = &omap2420_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = omap2420_uart3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -220,6 +220,7 @@ static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+@@ -227,7 +228,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+ .slave = &omap2420_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2420_i2c1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -238,6 +238,7 @@ static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+@@ -245,7 +246,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+ .slave = &omap2420_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2420_i2c2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -370,6 +370,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+ .pa_end = 0x48028000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> timer1 */
+@@ -378,7 +379,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+ .slave = &omap2420_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2420_timer1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -420,6 +420,7 @@ static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer2 */
+@@ -428,7 +429,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+ .slave = &omap2420_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap2420_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -470,6 +470,7 @@ static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+ .pa_end = 0x48078000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer3 */
+@@ -478,7 +479,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+ .slave = &omap2420_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap2420_timer3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -520,6 +520,7 @@ static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+ .pa_end = 0x4807a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer4 */
+@@ -528,7 +529,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+ .slave = &omap2420_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap2420_timer4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -570,6 +570,7 @@ static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+ .pa_end = 0x4807c000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer5 */
+@@ -578,7 +579,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+ .slave = &omap2420_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap2420_timer5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -621,6 +621,7 @@ static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+ .pa_end = 0x4807e000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer6 */
+@@ -629,7 +630,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+ .slave = &omap2420_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap2420_timer6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -671,6 +671,7 @@ static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+ .pa_end = 0x48080000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer7 */
+@@ -679,7 +680,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+ .slave = &omap2420_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap2420_timer7_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -721,6 +721,7 @@ static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+ .pa_end = 0x48082000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer8 */
+@@ -729,7 +730,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+ .slave = &omap2420_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap2420_timer8_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -771,6 +771,7 @@ static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+ .pa_end = 0x48084000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer9 */
+@@ -779,7 +780,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+ .slave = &omap2420_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap2420_timer9_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -821,6 +821,7 @@ static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer10 */
+@@ -829,7 +830,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+ .slave = &omap2420_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2420_timer10_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -871,6 +871,7 @@ static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer11 */
+@@ -879,7 +880,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+ .slave = &omap2420_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2420_timer11_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -921,6 +921,7 @@ static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+ .pa_end = 0x4808a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer12 */
+@@ -929,7 +930,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+ .slave = &omap2420_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap2420_timer12_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -966,6 +966,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+ .pa_end = 0x4802207f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+@@ -973,7 +974,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+ .slave = &omap2420_wd_timer2_hwmod,
+ .clk = "mpu_wdt_ick",
+ .addr = omap2420_wd_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1184,6 +1184,7 @@ static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
+ .pa_end = 0x480503FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss */
+@@ -1192,7 +1193,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
+ .slave = &omap2420_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2420_dss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1268,6 +1268,7 @@ static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
+ .pa_end = 0x480507FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1276,7 +1277,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+ .slave = &omap2420_dss_dispc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2420_dss_dispc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+@@ -1338,6 +1338,7 @@ static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
+ .pa_end = 0x48050BFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_rfbi */
+@@ -1346,7 +1347,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
+ .slave = &omap2420_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2420_dss_rfbi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1394,6 +1394,7 @@ static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
+ .pa_end = 0x48050FFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_venc */
+@@ -1402,7 +1403,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+ .slave = &omap2420_dss_venc_hwmod,
+ .clk = "dss_54m_fck",
+ .addr = omap2420_dss_venc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+@@ -1536,6 +1536,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
+ .pa_end = 0x480181ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
+@@ -1543,7 +1544,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
+ .slave = &omap2420_gpio1_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1554,6 +1554,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
+ .pa_end = 0x4801a1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
+@@ -1561,7 +1562,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
+ .slave = &omap2420_gpio2_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1572,6 +1572,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
+ .pa_end = 0x4801c1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
+@@ -1579,7 +1580,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
+ .slave = &omap2420_gpio3_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1590,6 +1590,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
+ .pa_end = 0x4801e1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
+@@ -1597,7 +1598,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
+ .slave = &omap2420_gpio4_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2420_gpio4_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1789,6 +1789,7 @@ static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
+ .pa_end = 0x48056fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* dma_system -> L3 */
+@@ -1810,7 +1811,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
+ .slave = &omap2420_dma_system_hwmod,
+ .clk = "sdma_ick",
+ .addr = omap2420_dma_system_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1868,6 +1868,7 @@ static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* l4_core -> mailbox */
+@@ -1875,7 +1876,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mailbox_hwmod,
+ .addr = omap2420_mailbox_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2044,6 +2044,7 @@ static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
+ .pa_end = 0x480740ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp1 */
+@@ -2052,7 +2053,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
+ .slave = &omap2420_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+ .addr = omap2420_mcbsp1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2101,6 +2101,7 @@ static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
+ .pa_end = 0x480760ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp2 */
+@@ -2109,7 +2110,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
+ .slave = &omap2420_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap2420_mcbsp2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 9682dd5..da28794 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1,7 +1,7 @@
+ /*
+ * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
+ *
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -141,6 +141,7 @@ static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+@@ -148,7 +149,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+ .slave = &omap2430_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2430_i2c1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -159,6 +159,7 @@ static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+@@ -166,7 +167,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+ .slave = &omap2430_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2430_i2c2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -184,6 +184,7 @@ static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
+ .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+@@ -191,7 +192,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+ .slave = &omap2430_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = omap2430_uart1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -202,6 +202,7 @@ static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
+ .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+@@ -209,7 +210,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+ .slave = &omap2430_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = omap2430_uart2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -220,6 +220,7 @@ static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
+ .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+@@ -227,7 +228,6 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .slave = &omap2430_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = omap2430_uart3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -248,7 +248,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+ .slave = &omap2430_usbhsotg_hwmod,
+ .clk = "usb_l4_ick",
+ .addr = omap2430_usbhsotg_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -267,6 +266,7 @@ static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+ .pa_end = 0x4809c1ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+@@ -274,7 +274,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+ .slave = &omap2430_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = omap2430_mmc1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -285,14 +284,14 @@ static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+ .pa_end = 0x480b41ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mmc2_hwmod,
+- .addr = omap2430_mmc2_addr_space,
+ .clk = "mmchs2_ick",
+- .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
++ .addr = omap2430_mmc2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -339,6 +338,7 @@ static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
+ .pa_end = 0x480980ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+@@ -346,7 +346,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+ .slave = &omap2430_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+ .addr = omap2430_mcspi1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -357,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
+ .pa_end = 0x4809a0ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+@@ -364,7 +364,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+ .slave = &omap2430_mcspi2_hwmod,
+ .clk = "mcspi2_ick",
+ .addr = omap2430_mcspi2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -375,6 +374,7 @@ static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+ .pa_end = 0x480b80ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+@@ -382,7 +382,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+ .slave = &omap2430_mcspi3_hwmod,
+ .clk = "mcspi3_ick",
+ .addr = omap2430_mcspi3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -471,6 +470,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+ .pa_end = 0x49018000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> timer1 */
+@@ -479,7 +479,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+ .slave = &omap2430_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2430_timer1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -521,6 +520,7 @@ static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer2 */
+@@ -529,7 +529,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+ .slave = &omap2430_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap2430_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -571,6 +570,7 @@ static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+ .pa_end = 0x48078000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer3 */
+@@ -579,7 +579,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+ .slave = &omap2430_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap2430_timer3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -621,6 +620,7 @@ static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+ .pa_end = 0x4807a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer4 */
+@@ -629,7 +629,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+ .slave = &omap2430_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap2430_timer4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -671,6 +670,7 @@ static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+ .pa_end = 0x4807c000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer5 */
+@@ -679,7 +679,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+ .slave = &omap2430_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap2430_timer5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -721,6 +720,7 @@ static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+ .pa_end = 0x4807e000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer6 */
+@@ -729,7 +729,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+ .slave = &omap2430_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap2430_timer6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -771,6 +770,7 @@ static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+ .pa_end = 0x48080000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer7 */
+@@ -779,7 +779,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+ .slave = &omap2430_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap2430_timer7_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -821,6 +820,7 @@ static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+ .pa_end = 0x48082000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer8 */
+@@ -829,7 +829,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+ .slave = &omap2430_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap2430_timer8_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -871,6 +870,7 @@ static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+ .pa_end = 0x48084000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer9 */
+@@ -879,7 +879,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+ .slave = &omap2430_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap2430_timer9_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -921,6 +920,7 @@ static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer10 */
+@@ -929,7 +929,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+ .slave = &omap2430_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2430_timer10_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -971,6 +970,7 @@ static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer11 */
+@@ -979,7 +979,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+ .slave = &omap2430_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2430_timer11_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1021,6 +1020,7 @@ static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+ .pa_end = 0x4808a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer12 */
+@@ -1029,7 +1029,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+ .slave = &omap2430_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap2430_timer12_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1066,6 +1065,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+ .pa_end = 0x4901607f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+@@ -1073,7 +1073,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+ .slave = &omap2430_wd_timer2_hwmod,
+ .clk = "mpu_wdt_ick",
+ .addr = omap2430_wd_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1284,6 +1283,7 @@ static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
+ .pa_end = 0x480503FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss */
+@@ -1292,7 +1292,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
+ .slave = &omap2430_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2430_dss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1362,6 +1361,7 @@ static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
+ .pa_end = 0x480507FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1370,7 +1370,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+ .slave = &omap2430_dss_dispc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2430_dss_dispc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1426,6 +1425,7 @@ static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
+ .pa_end = 0x48050BFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_rfbi */
+@@ -1434,7 +1434,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
+ .slave = &omap2430_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2430_dss_rfbi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1476,6 +1475,7 @@ static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
+ .pa_end = 0x48050FFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_venc */
+@@ -1484,7 +1484,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+ .slave = &omap2430_dss_venc_hwmod,
+ .clk = "dss_54m_fck",
+ .addr = omap2430_dss_venc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+@@ -1621,6 +1620,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+ .pa_end = 0x4900C1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+@@ -1628,7 +1628,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+ .slave = &omap2430_gpio1_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1639,6 +1638,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+ .pa_end = 0x4900E1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+@@ -1646,7 +1646,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+ .slave = &omap2430_gpio2_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1657,6 +1656,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+ .pa_end = 0x490101ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+@@ -1664,7 +1664,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+ .slave = &omap2430_gpio3_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1675,6 +1674,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+ .pa_end = 0x490121ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+@@ -1682,7 +1682,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+ .slave = &omap2430_gpio4_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio4_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1693,6 +1692,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+ .pa_end = 0x480B61ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+@@ -1700,7 +1700,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+ .slave = &omap2430_gpio5_hwmod,
+ .clk = "gpio5_ick",
+ .addr = omap2430_gpio5_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1923,6 +1922,7 @@ static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
+ .pa_end = 0x48056fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* dma_system -> L3 */
+@@ -1944,7 +1944,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+ .slave = &omap2430_dma_system_hwmod,
+ .clk = "sdma_ick",
+ .addr = omap2430_dma_system_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2001,6 +2000,7 @@ static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* l4_core -> mailbox */
+@@ -2008,7 +2008,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mailbox_hwmod,
+ .addr = omap2430_mailbox_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2287,6 +2286,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
+ .pa_end = 0x480740ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp1 */
+@@ -2295,7 +2295,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+ .slave = &omap2430_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+ .addr = omap2430_mcbsp1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2345,6 +2344,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
+ .pa_end = 0x480760ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp2 */
+@@ -2353,7 +2353,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+ .slave = &omap2430_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap2430_mcbsp2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2403,6 +2402,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+ .pa_end = 0x4808C0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp3 */
+@@ -2411,7 +2411,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+ .slave = &omap2430_mcbsp3_hwmod,
+ .clk = "mcbsp3_ick",
+ .addr = omap2430_mcbsp3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2461,6 +2460,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+ .pa_end = 0x4808E0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp4 */
+@@ -2469,7 +2469,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+ .slave = &omap2430_mcbsp4_hwmod,
+ .clk = "mcbsp4_ick",
+ .addr = omap2430_mcbsp4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2519,6 +2518,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+ .pa_end = 0x480960ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp5 */
+@@ -2527,7 +2527,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+ .slave = &omap2430_mcbsp5_hwmod,
+ .clk = "mcbsp5_ick",
+ .addr = omap2430_mcbsp5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 909a84d..6410779 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1,7 +1,7 @@
+ /*
+ * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
+ *
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -111,6 +111,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+ .pa_end = 0x6800ffff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* MPU -> L3 interface */
+@@ -118,7 +119,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
+ .master = &omap3xxx_mpu_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .addr = omap3xxx_l3_main_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -196,6 +196,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
+ .pa_end = 0x4809c1ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
+@@ -203,7 +204,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
+ .slave = &omap3xxx_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = omap3xxx_mmc1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+ };
+@@ -215,6 +215,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
+ .pa_end = 0x480b41ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
+@@ -222,7 +223,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
+ .slave = &omap3xxx_mmc2_hwmod,
+ .clk = "mmchs2_ick",
+ .addr = omap3xxx_mmc2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+ };
+@@ -234,6 +234,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
+ .pa_end = 0x480ad1ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+@@ -241,7 +242,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+ .slave = &omap3xxx_mmc3_hwmod,
+ .clk = "mmchs3_ick",
+ .addr = omap3xxx_mmc3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+ };
+@@ -253,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+ .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+@@ -260,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+ .slave = &omap3xxx_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = omap3xxx_uart1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -271,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+ .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+@@ -278,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+ .slave = &omap3xxx_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = omap3xxx_uart2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -289,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+ .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+@@ -296,7 +297,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+ .slave = &omap3xxx_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = omap3xxx_uart3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -307,6 +307,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
+ .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+@@ -314,7 +315,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+ .slave = &omap3xxx_uart4_hwmod,
+ .clk = "uart4_ick",
+ .addr = omap3xxx_uart4_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -328,6 +328,7 @@ static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+ .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+@@ -335,7 +336,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+ .slave = &omap3xxx_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap3xxx_i2c1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
+@@ -353,6 +353,7 @@ static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+ .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+@@ -360,7 +361,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+ .slave = &omap3xxx_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap3xxx_i2c2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
+@@ -378,6 +378,7 @@ static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+ .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+@@ -385,7 +386,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+ .slave = &omap3xxx_i2c3_hwmod,
+ .clk = "i2c3_ick",
+ .addr = omap3xxx_i2c3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
+@@ -403,6 +403,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+ .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+@@ -410,7 +411,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+ .slave = &omap34xx_sr1_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -421,6 +421,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+ .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+@@ -428,7 +429,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+ .slave = &omap34xx_sr2_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -442,6 +442,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> usbhsotg */
+@@ -450,7 +451,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+ .slave = &omap3xxx_usbhsotg_hwmod,
+ .clk = "l4_ick",
+ .addr = omap3xxx_usbhsotg_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -468,6 +468,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> usbhsotg */
+@@ -476,7 +477,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+ .slave = &am35xx_usbhsotg_hwmod,
+ .clk = "l4_ick",
+ .addr = am35xx_usbhsotg_addrs,
+- .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -621,6 +621,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+ .pa_end = 0x48318000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> timer1 */
+@@ -629,7 +630,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+ .slave = &omap3xxx_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap3xxx_timer1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -671,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+ .pa_end = 0x49032000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer2 */
+@@ -679,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+ .slave = &omap3xxx_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap3xxx_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -721,6 +721,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+ .pa_end = 0x49034000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer3 */
+@@ -729,7 +730,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+ .slave = &omap3xxx_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap3xxx_timer3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -771,6 +771,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+ .pa_end = 0x49036000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer4 */
+@@ -779,7 +780,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+ .slave = &omap3xxx_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap3xxx_timer4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -821,6 +821,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+ .pa_end = 0x49038000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer5 */
+@@ -829,7 +830,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+ .slave = &omap3xxx_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap3xxx_timer5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -871,6 +871,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+ .pa_end = 0x4903A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer6 */
+@@ -879,7 +880,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+ .slave = &omap3xxx_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap3xxx_timer6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -921,6 +921,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+ .pa_end = 0x4903C000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer7 */
+@@ -929,7 +930,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+ .slave = &omap3xxx_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap3xxx_timer7_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -971,6 +971,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+ .pa_end = 0x4903E000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer8 */
+@@ -979,7 +980,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+ .slave = &omap3xxx_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap3xxx_timer8_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1021,6 +1021,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+ .pa_end = 0x49040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer9 */
+@@ -1029,7 +1030,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+ .slave = &omap3xxx_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap3xxx_timer9_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1071,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer10 */
+@@ -1079,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+ .slave = &omap3xxx_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap3xxx_timer10_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1121,6 +1121,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer11 */
+@@ -1129,7 +1130,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+ .slave = &omap3xxx_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap3xxx_timer11_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1171,6 +1171,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+ .pa_end = 0x48304000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> timer12 */
+@@ -1179,7 +1180,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
+ .slave = &omap3xxx_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap3xxx_timer12_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1216,6 +1216,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+ .pa_end = 0x4831407f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+@@ -1223,7 +1224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+ .slave = &omap3xxx_wd_timer2_hwmod,
+ .clk = "wdt2_ick",
+ .addr = omap3xxx_wd_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1497,6 +1497,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
+ .pa_end = 0x480503FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss */
+@@ -1505,7 +1506,6 @@ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+ .slave = &omap3430es1_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap3xxx_dss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1521,7 +1521,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+ .slave = &omap3xxx_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap3xxx_dss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1632,6 +1631,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
+ .pa_end = 0x480507FF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1640,7 +1640,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+ .slave = &omap3xxx_dss_dispc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap3xxx_dss_dispc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+@@ -1697,6 +1696,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+ .pa_end = 0x4804FFFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_dsi1 */
+@@ -1704,7 +1704,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_dsi1_hwmod,
+ .addr = omap3xxx_dss_dsi1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+@@ -1767,6 +1766,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
+ .pa_end = 0x48050BFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_rfbi */
+@@ -1775,7 +1775,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+ .slave = &omap3xxx_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+ .addr = omap3xxx_dss_rfbi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+@@ -1826,6 +1825,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
+ .pa_end = 0x48050FFF,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> dss_venc */
+@@ -1834,7 +1834,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+ .slave = &omap3xxx_dss_venc_hwmod,
+ .clk = "dss_tv_fck",
+ .addr = omap3xxx_dss_venc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+@@ -2003,13 +2002,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+ .pa_end = 0x483101ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_gpio1_hwmod,
+ .addr = omap3xxx_gpio1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2020,13 +2019,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+ .pa_end = 0x490501ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio2_hwmod,
+ .addr = omap3xxx_gpio2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2037,13 +2036,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+ .pa_end = 0x490521ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio3_hwmod,
+ .addr = omap3xxx_gpio3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2054,13 +2053,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+ .pa_end = 0x490541ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio4_hwmod,
+ .addr = omap3xxx_gpio4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2071,13 +2070,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+ .pa_end = 0x490561ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio5_hwmod,
+ .addr = omap3xxx_gpio5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2088,13 +2087,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+ .pa_end = 0x490581ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio6_hwmod,
+ .addr = omap3xxx_gpio6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2395,6 +2394,7 @@ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+ .pa_end = 0x48056fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* dma_system master ports */
+@@ -2408,7 +2408,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+ .slave = &omap3xxx_dma_system_hwmod,
+ .clk = "core_l4_ick",
+ .addr = omap3xxx_dma_system_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2480,6 +2479,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+ .pa_end = 0x480740ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp1 */
+@@ -2488,7 +2488,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+ .slave = &omap3xxx_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+ .addr = omap3xxx_mcbsp1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2538,6 +2537,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+ .pa_end = 0x490220ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp2 */
+@@ -2546,7 +2546,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+ .slave = &omap3xxx_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap3xxx_mcbsp2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
++
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2601,6 +2601,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+ .pa_end = 0x490240ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp3 */
+@@ -2609,7 +2610,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+ .slave = &omap3xxx_mcbsp3_hwmod,
+ .clk = "mcbsp3_ick",
+ .addr = omap3xxx_mcbsp3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2664,6 +2664,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+ .pa_end = 0x490260ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp4 */
+@@ -2672,7 +2673,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+ .slave = &omap3xxx_mcbsp4_hwmod,
+ .clk = "mcbsp4_ick",
+ .addr = omap3xxx_mcbsp4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2722,6 +2722,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+ .pa_end = 0x480960ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_core -> mcbsp5 */
+@@ -2730,7 +2731,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+ .slave = &omap3xxx_mcbsp5_hwmod,
+ .clk = "mcbsp5_ick",
+ .addr = omap3xxx_mcbsp5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2785,6 +2785,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+ .pa_end = 0x490280ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp2_sidetone */
+@@ -2793,7 +2794,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+ .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap3xxx_mcbsp2_sidetone_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -2834,6 +2834,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+ .pa_end = 0x4902A0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp3_sidetone */
+@@ -2842,7 +2843,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+ .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
+ .clk = "mcbsp3_ick",
+ .addr = omap3xxx_mcbsp3_sidetone_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -3033,6 +3033,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* l4_core -> mailbox */
+@@ -3040,7 +3041,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mailbox_hwmod,
+ .addr = omap3xxx_mailbox_addrs,
+- .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3076,6 +3076,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+ .pa_end = 0x480980ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+@@ -3083,7 +3084,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+ .slave = &omap34xx_mcspi1,
+ .clk = "mcspi1_ick",
+ .addr = omap34xx_mcspi1_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3094,6 +3094,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
+ .pa_end = 0x4809a0ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+@@ -3101,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+ .slave = &omap34xx_mcspi2,
+ .clk = "mcspi2_ick",
+ .addr = omap34xx_mcspi2_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3112,6 +3112,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
+ .pa_end = 0x480b80ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+@@ -3119,7 +3120,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+ .slave = &omap34xx_mcspi3,
+ .clk = "mcspi3_ick",
+ .addr = omap34xx_mcspi3_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3130,6 +3130,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+ .pa_end = 0x480ba0ff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+@@ -3137,7 +3138,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+ .slave = &omap34xx_mcspi4,
+ .clk = "mcspi4_ick",
+ .addr = omap34xx_mcspi4_addr_space,
+- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 8cbbfbf..f8ccc4a 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -95,6 +95,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+ .pa_end = 0x4e0007ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* mpu -> dmm */
+@@ -103,7 +104,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+ .slave = &omap44xx_dmm_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dmm_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -150,6 +150,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
+ .pa_end = 0x4a20c0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> emif_fw */
+@@ -158,7 +159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+ .slave = &omap44xx_emif_fw_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_emif_fw_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -276,6 +276,7 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+ .pa_end = 0x44000fff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* mpu -> l3_main_1 */
+@@ -284,7 +285,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -356,6 +356,7 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+ .pa_end = 0x44801fff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* l3_main_1 -> l3_main_2 */
+@@ -364,7 +365,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -411,6 +411,7 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+ .pa_end = 0x45000fff,
+ .flags = ADDR_TYPE_RT,
+ },
++ { }
+ };
+
+ /* l3_main_1 -> l3_main_3 */
+@@ -419,7 +420,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -697,6 +697,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+ .pa_end = 0x401f13ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> aess */
+@@ -705,7 +706,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
+ .slave = &omap44xx_aess_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_aess_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -715,6 +715,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
+ .pa_end = 0x490f13ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> aess (dma) */
+@@ -723,7 +724,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
+ .slave = &omap44xx_aess_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_aess_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -807,6 +807,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
+ .pa_end = 0x4a30401f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> counter_32k */
+@@ -815,7 +816,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
+ .slave = &omap44xx_counter_32k_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_counter_32k_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -889,6 +889,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+ .pa_end = 0x4a056fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> dma_system */
+@@ -897,7 +898,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+ .slave = &omap44xx_dma_system_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dma_system_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -961,6 +961,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+ .pa_end = 0x4012e07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> dmic */
+@@ -969,7 +970,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+ .slave = &omap44xx_dmic_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_dmic_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -979,6 +979,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+ .pa_end = 0x4902e07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> dmic (dma) */
+@@ -987,7 +988,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+ .slave = &omap44xx_dmic_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_dmic_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1128,6 +1128,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+ .pa_end = 0x5800007f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss */
+@@ -1136,7 +1137,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1146,6 +1146,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+ .pa_end = 0x4804007f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss */
+@@ -1154,7 +1155,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1228,6 +1228,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_dispc */
+@@ -1236,7 +1237,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dispc_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1246,6 +1246,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+ .pa_end = 0x48041fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_dispc */
+@@ -1254,7 +1255,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dispc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1319,6 +1319,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+ .pa_end = 0x580041ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_dsi1 */
+@@ -1327,7 +1328,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dsi1_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1337,6 +1337,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+ .pa_end = 0x480441ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_dsi1 */
+@@ -1345,7 +1346,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1389,6 +1389,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+ .pa_end = 0x580051ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_dsi2 */
+@@ -1397,7 +1398,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dsi2_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1407,6 +1407,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+ .pa_end = 0x480451ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_dsi2 */
+@@ -1415,7 +1416,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1479,6 +1479,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+ .pa_end = 0x58006fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_hdmi */
+@@ -1487,7 +1488,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_hdmi_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1497,6 +1497,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+ .pa_end = 0x48046fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_hdmi */
+@@ -1505,7 +1506,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_hdmi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1565,6 +1565,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+ .pa_end = 0x580020ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_rfbi */
+@@ -1573,7 +1574,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_rfbi_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1583,6 +1583,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+ .pa_end = 0x480420ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_rfbi */
+@@ -1591,7 +1592,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_rfbi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1634,6 +1634,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+ .pa_end = 0x580030ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> dss_venc */
+@@ -1642,7 +1643,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_venc_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -1652,6 +1652,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+ .pa_end = 0x480430ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> dss_venc */
+@@ -1660,7 +1661,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_venc_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -1725,6 +1725,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+ .pa_end = 0x4a3101ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> gpio1 */
+@@ -1733,7 +1734,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+ .slave = &omap44xx_gpio1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_gpio1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1777,6 +1777,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+ .pa_end = 0x480551ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> gpio2 */
+@@ -1785,7 +1786,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+ .slave = &omap44xx_gpio2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1830,6 +1830,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+ .pa_end = 0x480571ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> gpio3 */
+@@ -1838,7 +1839,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+ .slave = &omap44xx_gpio3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1883,6 +1883,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+ .pa_end = 0x480591ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> gpio4 */
+@@ -1891,7 +1892,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+ .slave = &omap44xx_gpio4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1936,6 +1936,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+ .pa_end = 0x4805b1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> gpio5 */
+@@ -1944,7 +1945,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+ .slave = &omap44xx_gpio5_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1989,6 +1989,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+ .pa_end = 0x4805d1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> gpio6 */
+@@ -1997,7 +1998,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+ .slave = &omap44xx_gpio6_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2072,6 +2072,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+ .pa_end = 0x4a05bfff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> hsi */
+@@ -2080,7 +2081,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+ .slave = &omap44xx_hsi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_hsi_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2145,6 +2145,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+ .pa_end = 0x480700ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> i2c1 */
+@@ -2153,7 +2154,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+ .slave = &omap44xx_i2c1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2198,6 +2198,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+ .pa_end = 0x480720ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> i2c2 */
+@@ -2206,7 +2207,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+ .slave = &omap44xx_i2c2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2251,6 +2251,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+ .pa_end = 0x480600ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> i2c3 */
+@@ -2259,7 +2260,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+ .slave = &omap44xx_i2c3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2304,6 +2304,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+ .pa_end = 0x483500ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> i2c4 */
+@@ -2312,7 +2313,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+ .slave = &omap44xx_i2c4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2479,6 +2479,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+ .pa_end = 0x520000ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> iss */
+@@ -2487,7 +2488,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+ .slave = &omap44xx_iss_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_iss_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2562,6 +2562,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+ .pa_end = 0x5a07ffff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l3_main_2 -> iva */
+@@ -2570,7 +2571,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+ .slave = &omap44xx_iva_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_iva_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -2665,6 +2665,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+ .pa_end = 0x4a31c07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> kbd */
+@@ -2673,7 +2674,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+ .slave = &omap44xx_kbd_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_kbd_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2730,6 +2730,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> mailbox */
+@@ -2738,7 +2739,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .slave = &omap44xx_mailbox_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mailbox_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2799,6 +2799,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+ .pa_end = 0x401220ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp1 */
+@@ -2807,7 +2808,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+ .slave = &omap44xx_mcbsp1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -2818,6 +2818,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+ .pa_end = 0x490220ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp1 (dma) */
+@@ -2826,7 +2827,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+ .slave = &omap44xx_mcbsp1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp1_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -2872,6 +2872,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+ .pa_end = 0x401240ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp2 */
+@@ -2880,7 +2881,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+ .slave = &omap44xx_mcbsp2_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -2891,6 +2891,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+ .pa_end = 0x490240ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp2 (dma) */
+@@ -2899,7 +2900,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+ .slave = &omap44xx_mcbsp2_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp2_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -2945,6 +2945,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+ .pa_end = 0x401260ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp3 */
+@@ -2953,7 +2954,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+ .slave = &omap44xx_mcbsp3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -2964,6 +2964,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+ .pa_end = 0x490260ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcbsp3 (dma) */
+@@ -2972,7 +2973,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+ .slave = &omap44xx_mcbsp3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp3_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -3017,6 +3017,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+ .pa_end = 0x480960ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcbsp4 */
+@@ -3025,7 +3026,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+ .slave = &omap44xx_mcbsp4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcbsp4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3090,6 +3090,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+ .pa_end = 0x4013207f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcpdm */
+@@ -3098,7 +3099,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+ .slave = &omap44xx_mcpdm_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcpdm_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -3108,6 +3108,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+ .pa_end = 0x4903207f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> mcpdm (dma) */
+@@ -3116,7 +3117,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+ .slave = &omap44xx_mcpdm_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcpdm_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -3189,6 +3189,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+ .pa_end = 0x480981ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcspi1 */
+@@ -3197,7 +3198,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+ .slave = &omap44xx_mcspi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3249,6 +3249,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+ .pa_end = 0x4809a1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcspi2 */
+@@ -3257,7 +3258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+ .slave = &omap44xx_mcspi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3309,6 +3309,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+ .pa_end = 0x480b81ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcspi3 */
+@@ -3317,7 +3318,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+ .slave = &omap44xx_mcspi3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3367,6 +3367,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+ .pa_end = 0x480ba1ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mcspi4 */
+@@ -3375,7 +3376,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+ .slave = &omap44xx_mcspi4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3452,6 +3452,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+ .pa_end = 0x4809c3ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mmc1 */
+@@ -3460,7 +3461,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+ .slave = &omap44xx_mmc1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3516,6 +3516,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+ .pa_end = 0x480b43ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mmc2 */
+@@ -3524,7 +3525,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+ .slave = &omap44xx_mmc2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3570,6 +3570,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+ .pa_end = 0x480ad3ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mmc3 */
+@@ -3578,7 +3579,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+ .slave = &omap44xx_mmc3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3622,6 +3622,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+ .pa_end = 0x480d13ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mmc4 */
+@@ -3630,7 +3631,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+ .slave = &omap44xx_mmc4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3674,6 +3674,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+ .pa_end = 0x480d53ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> mmc5 */
+@@ -3682,7 +3683,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+ .slave = &omap44xx_mmc5_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3787,6 +3787,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+ .pa_end = 0x4a0dd03f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> smartreflex_core */
+@@ -3795,7 +3796,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+ .slave = &omap44xx_smartreflex_core_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_core_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3833,6 +3833,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+ .pa_end = 0x4a0db03f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> smartreflex_iva */
+@@ -3841,7 +3842,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+ .slave = &omap44xx_smartreflex_iva_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_iva_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3879,6 +3879,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+ .pa_end = 0x4a0d903f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> smartreflex_mpu */
+@@ -3887,7 +3888,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+ .slave = &omap44xx_smartreflex_mpu_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_mpu_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -3944,6 +3944,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+ .pa_end = 0x4a0f6fff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> spinlock */
+@@ -3952,7 +3953,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+ .slave = &omap44xx_spinlock_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_spinlock_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4024,6 +4024,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> timer1 */
+@@ -4032,7 +4033,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .slave = &omap44xx_timer1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_timer1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4069,6 +4069,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer2 */
+@@ -4077,7 +4078,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .slave = &omap44xx_timer2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4114,6 +4114,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer3 */
+@@ -4122,7 +4123,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+ .slave = &omap44xx_timer3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4159,6 +4159,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer4 */
+@@ -4167,7 +4168,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+ .slave = &omap44xx_timer4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4204,6 +4204,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+ .pa_end = 0x4013807f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer5 */
+@@ -4212,7 +4213,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -4222,6 +4222,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+ .pa_end = 0x4903807f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer5 (dma) */
+@@ -4230,7 +4231,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -4268,6 +4268,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+ .pa_end = 0x4013a07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer6 */
+@@ -4276,7 +4277,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -4286,6 +4286,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+ .pa_end = 0x4903a07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer6 (dma) */
+@@ -4294,7 +4295,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -4332,6 +4332,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+ .pa_end = 0x4013c07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer7 */
+@@ -4340,7 +4341,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -4350,6 +4350,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+ .pa_end = 0x4903c07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer7 (dma) */
+@@ -4358,7 +4359,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -4396,6 +4396,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+ .pa_end = 0x4013e07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer8 */
+@@ -4404,7 +4405,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -4414,6 +4414,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+ .pa_end = 0x4903e07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> timer8 (dma) */
+@@ -4422,7 +4423,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+@@ -4460,6 +4460,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer9 */
+@@ -4468,7 +4469,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+ .slave = &omap44xx_timer9_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer9_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4505,6 +4505,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer10 */
+@@ -4513,7 +4514,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+ .slave = &omap44xx_timer10_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer10_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4550,6 +4550,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> timer11 */
+@@ -4558,7 +4559,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+ .slave = &omap44xx_timer11_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer11_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4622,6 +4622,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+ .pa_end = 0x4806a0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> uart1 */
+@@ -4630,7 +4631,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+ .slave = &omap44xx_uart1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart1_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4674,6 +4674,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+ .pa_end = 0x4806c0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> uart2 */
+@@ -4682,7 +4683,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+ .slave = &omap44xx_uart2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4726,6 +4726,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+ .pa_end = 0x480200ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> uart3 */
+@@ -4734,7 +4735,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+ .slave = &omap44xx_uart3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4779,6 +4779,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+ .pa_end = 0x4806e0ff,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_per -> uart4 */
+@@ -4787,7 +4788,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+ .slave = &omap44xx_uart4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart4_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4854,6 +4854,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+ .pa_end = 0x4a0ab003,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_cfg -> usb_otg_hs */
+@@ -4862,7 +4863,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+ .slave = &omap44xx_usb_otg_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_otg_hs_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4931,6 +4931,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+ .pa_end = 0x4a31407f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_wkup -> wd_timer2 */
+@@ -4939,7 +4940,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+ .slave = &omap44xx_wd_timer2_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_wd_timer2_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -4976,6 +4976,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+ .pa_end = 0x4013007f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> wd_timer3 */
+@@ -4984,7 +4985,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+ .slave = &omap44xx_wd_timer3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_wd_timer3_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -4994,6 +4994,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+ .pa_end = 0x4903007f,
+ .flags = ADDR_TYPE_RT
+ },
++ { }
+ };
+
+ /* l4_abe -> wd_timer3 (dma) */
+@@ -5002,7 +5003,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+ .slave = &omap44xx_wd_timer3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_wd_timer3_dma_addrs,
+- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
+ .user = OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index e93438c..f3a3bff 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -219,7 +219,6 @@ struct omap_hwmod_addr_space {
+ * @clk: interface clock: OMAP clock name
+ * @_clk: pointer to the interface struct clk (filled in at runtime)
+ * @fw: interface firewall data
+- * @addr_cnt: ARRAY_SIZE(@addr)
+ * @width: OCP data width
+ * @user: initiators using this interface (see OCP_USER_* macros above)
+ * @flags: OCP interface flags (see OCPIF_* macros above)
+@@ -238,7 +237,6 @@ struct omap_hwmod_ocp_if {
+ union {
+ struct omap_hwmod_omap2_firewall omap2;
+ } fw;
+- u8 addr_cnt;
+ u8 width;
+ u8 user;
+ u8 flags;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0038-omap_hwmod-share-identical-omap_hwmod_addr_space-arr.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0038-omap_hwmod-share-identical-omap_hwmod_addr_space-arr.patch
--- /dev/null
@@ -0,0 +1,1958 @@
+From 69aca61879a4572e40cedce49c08464a2a8fe0b0 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:06 -0600
+Subject: [PATCH 038/149] omap_hwmod: share identical omap_hwmod_addr_space arrays
+
+To reduce kernel source file data duplication, share struct
+omap_hwmod_addr_space arrays across OMAP2xxx and 3xxx hwmod data
+files.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/Makefile | 11 +-
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 291 ++----------------
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 319 ++------------------
+ .../omap_hwmod_2xxx_3xxx_interconnect_data.c | 173 +++++++++++
+ .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 130 ++++++++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 151 +---------
+ arch/arm/mach-omap2/omap_hwmod_common_data.h | 38 +++-
+ 7 files changed, 414 insertions(+), 699 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+ create mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index ff1466f..8a75d17 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -145,9 +145,14 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
+ obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
+
+ # hwmod data
+-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
+-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
+-obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
++obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o \
++ omap_hwmod_2xxx_3xxx_interconnect_data.o \
++ omap_hwmod_2420_data.o
++obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o \
++ omap_hwmod_2xxx_3xxx_interconnect_data.o \
++ omap_hwmod_2430_data.o
++obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o \
++ omap_hwmod_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
+
+ # EMU peripherals
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 1a7ce3e..3ec625c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
+ static struct omap_hwmod omap2420_mcbsp2_hwmod;
+
+ /* l4 core -> mcspi1 interface */
+-static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+- {
+- .pa_start = 0x48098000,
+- .pa_end = 0x480980ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+- .addr = omap2420_mcspi1_addr_space,
++ .addr = omap2_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* l4 core -> mcspi2 interface */
+-static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
+- {
+- .pa_start = 0x4809a000,
+- .pa_end = 0x4809a0ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mcspi2_hwmod,
+ .clk = "mcspi2_ick",
+- .addr = omap2420_mcspi2_addr_space,
++ .addr = omap2_mcspi2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
+ };
+
+ /* L4 CORE -> UART1 interface */
+-static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART1_BASE,
+- .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_uart1_hwmod,
+ .clk = "uart1_ick",
+- .addr = omap2420_uart1_addr_space,
++ .addr = omap2xxx_uart1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 CORE -> UART2 interface */
+-static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART2_BASE,
+- .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_uart2_hwmod,
+ .clk = "uart2_ick",
+- .addr = omap2420_uart2_addr_space,
++ .addr = omap2xxx_uart2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 PER -> UART3 interface */
+-static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART3_BASE,
+- .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_uart3_hwmod,
+ .clk = "uart3_ick",
+- .addr = omap2420_uart3_addr_space,
++ .addr = omap2xxx_uart3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+-/* I2C IP block address space length (in bytes) */
+-#define OMAP2_I2C_AS_LEN 128
+-
+ /* L4 CORE -> I2C1 interface */
+-static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+- {
+- .pa_start = 0x48070000,
+- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_i2c1_hwmod,
+ .clk = "i2c1_ick",
+- .addr = omap2420_i2c1_addr_space,
++ .addr = omap2_i2c1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 CORE -> I2C2 interface */
+-static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+- {
+- .pa_start = 0x48072000,
+- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_i2c2_hwmod,
+ .clk = "i2c2_ick",
+- .addr = omap2420_i2c2_addr_space,
++ .addr = omap2_i2c2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -414,21 +348,13 @@ static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+- {
+- .pa_start = 0x4802a000,
+- .pa_end = 0x4802a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+
+ /* l4_core -> timer2 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer2_hwmod,
+ .clk = "gpt2_ick",
+- .addr = omap2420_timer2_addrs,
++ .addr = omap2xxx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -464,21 +390,12 @@ static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+ { .irq = 39, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+- {
+- .pa_start = 0x48078000,
+- .pa_end = 0x48078000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer3 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer3_hwmod,
+ .clk = "gpt3_ick",
+- .addr = omap2420_timer3_addrs,
++ .addr = omap2xxx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -514,21 +431,12 @@ static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+ { .irq = 40, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+- {
+- .pa_start = 0x4807a000,
+- .pa_end = 0x4807a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer4 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer4_hwmod,
+ .clk = "gpt4_ick",
+- .addr = omap2420_timer4_addrs,
++ .addr = omap2xxx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -564,21 +472,12 @@ static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+ { .irq = 41, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+- {
+- .pa_start = 0x4807c000,
+- .pa_end = 0x4807c000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer5 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer5_hwmod,
+ .clk = "gpt5_ick",
+- .addr = omap2420_timer5_addrs,
++ .addr = omap2xxx_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -615,21 +514,12 @@ static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+ { .irq = 42, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+- {
+- .pa_start = 0x4807e000,
+- .pa_end = 0x4807e000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer6 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer6_hwmod,
+ .clk = "gpt6_ick",
+- .addr = omap2420_timer6_addrs,
++ .addr = omap2xxx_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -665,21 +555,12 @@ static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+ { .irq = 43, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+- {
+- .pa_start = 0x48080000,
+- .pa_end = 0x48080000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer7 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer7_hwmod,
+ .clk = "gpt7_ick",
+- .addr = omap2420_timer7_addrs,
++ .addr = omap2xxx_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -715,21 +596,12 @@ static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+ { .irq = 44, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+- {
+- .pa_start = 0x48082000,
+- .pa_end = 0x48082000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer8 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer8_hwmod,
+ .clk = "gpt8_ick",
+- .addr = omap2420_timer8_addrs,
++ .addr = omap2xxx_timer8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -765,21 +637,12 @@ static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+ { .irq = 45, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+- {
+- .pa_start = 0x48084000,
+- .pa_end = 0x48084000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer9 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer9_hwmod,
+ .clk = "gpt9_ick",
+- .addr = omap2420_timer9_addrs,
++ .addr = omap2xxx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -815,21 +678,12 @@ static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+ { .irq = 46, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+- {
+- .pa_start = 0x48086000,
+- .pa_end = 0x48086000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer10_hwmod,
+ .clk = "gpt10_ick",
+- .addr = omap2420_timer10_addrs,
++ .addr = omap2_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -865,21 +719,12 @@ static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+ { .irq = 47, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+- {
+- .pa_start = 0x48088000,
+- .pa_end = 0x48088000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer11_hwmod,
+ .clk = "gpt11_ick",
+- .addr = omap2420_timer11_addrs,
++ .addr = omap2_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -915,21 +760,12 @@ static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+ { .irq = 48, },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+- {
+- .pa_start = 0x4808a000,
+- .pa_end = 0x4808a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer12 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer12_hwmod,
+ .clk = "gpt12_ick",
+- .addr = omap2420_timer12_addrs,
++ .addr = omap2xxx_timer12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1178,21 +1014,12 @@ static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
+ &omap2420_dss__l3,
+ };
+
+-static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
+- {
+- .pa_start = 0x48050000,
+- .pa_end = 0x480503FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_dss_core_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2420_dss_addrs,
++ .addr = omap2_dss_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1262,21 +1089,12 @@ static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
+ { .irq = 25 },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
+- {
+- .pa_start = 0x48050400,
+- .pa_end = 0x480507FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_dss_dispc_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2420_dss_dispc_addrs,
++ .addr = omap2_dss_dispc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+@@ -1332,21 +1150,12 @@ static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
+ .sysc = &omap2420_rfbi_sysc,
+ };
+
+-static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
+- {
+- .pa_start = 0x48050800,
+- .pa_end = 0x48050BFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2420_dss_rfbi_addrs,
++ .addr = omap2_dss_rfbi_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1387,22 +1196,12 @@ static struct omap_hwmod_class omap2420_venc_hwmod_class = {
+ .name = "venc",
+ };
+
+-/* dss_venc */
+-static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
+- {
+- .pa_start = 0x48050C00,
+- .pa_end = 0x48050FFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_dss_venc_hwmod,
+ .clk = "dss_54m_fck",
+- .addr = omap2420_dss_venc_addrs,
++ .addr = omap2_dss_venc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+@@ -1783,15 +1582,6 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+ };
+
+-static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
+- {
+- .pa_start = 0x48056000,
+- .pa_end = 0x48056fff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* dma_system -> L3 */
+ static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
+ .master = &omap2420_dma_system_hwmod,
+@@ -1810,7 +1600,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_dma_system_hwmod,
+ .clk = "sdma_ick",
+- .addr = omap2420_dma_system_addrs,
++ .addr = omap2_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1862,20 +1652,11 @@ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = "iva", .irq = 34 },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+- {
+- .pa_start = 0x48094000,
+- .pa_end = 0x480941ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ /* l4_core -> mailbox */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mailbox_hwmod,
+- .addr = omap2420_mailbox_addrs,
++ .addr = omap2_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2037,22 +1818,12 @@ static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+ { .name = "tx", .dma_req = 31 },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
+- {
+- .name = "mpu",
+- .pa_start = 0x48074000,
+- .pa_end = 0x480740ff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> mcbsp1 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+- .addr = omap2420_mcbsp1_addrs,
++ .addr = omap2_mcbsp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2094,22 +1865,12 @@ static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+ { .name = "tx", .dma_req = 33 },
+ };
+
+-static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
+- {
+- .name = "mpu",
+- .pa_start = 0x48076000,
+- .pa_end = 0x480760ff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> mcbsp2 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+- .addr = omap2420_mcbsp2_addrs,
++ .addr = omap2xxx_mcbsp2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index da28794..9531ef2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
+ .user = OCP_USER_MPU,
+ };
+
+-/* I2C IP block address space length (in bytes) */
+-#define OMAP2_I2C_AS_LEN 128
+-
+ /* L4 CORE -> I2C1 interface */
+-static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+- {
+- .pa_start = 0x48070000,
+- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_i2c1_hwmod,
+ .clk = "i2c1_ick",
+- .addr = omap2430_i2c1_addr_space,
++ .addr = omap2_i2c1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 CORE -> I2C2 interface */
+-static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+- {
+- .pa_start = 0x48072000,
+- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_i2c2_hwmod,
+ .clk = "i2c2_ick",
+- .addr = omap2430_i2c2_addr_space,
++ .addr = omap2_i2c2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
+ };
+
+ /* L4 CORE -> UART1 interface */
+-static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART1_BASE,
+- .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_uart1_hwmod,
+ .clk = "uart1_ick",
+- .addr = omap2430_uart1_addr_space,
++ .addr = omap2xxx_uart1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 CORE -> UART2 interface */
+-static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART2_BASE,
+- .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_uart2_hwmod,
+ .clk = "uart2_ick",
+- .addr = omap2430_uart2_addr_space,
++ .addr = omap2xxx_uart2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* L4 PER -> UART3 interface */
+-static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
+- {
+- .pa_start = OMAP2_UART3_BASE,
+- .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
+- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_uart3_hwmod,
+ .clk = "uart3_ick",
+- .addr = omap2430_uart3_addr_space,
++ .addr = omap2xxx_uart3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -260,15 +212,6 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
+ };
+
+ /* L4 CORE -> MMC1 interface */
+-static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+- {
+- .pa_start = 0x4809c000,
+- .pa_end = 0x4809c1ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mmc1_hwmod,
+@@ -278,15 +221,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+ };
+
+ /* L4 CORE -> MMC2 interface */
+-static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+- {
+- .pa_start = 0x480b4000,
+- .pa_end = 0x480b41ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mmc2_hwmod,
+@@ -332,51 +266,24 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
+ };
+
+ /* l4 core -> mcspi1 interface */
+-static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
+- {
+- .pa_start = 0x48098000,
+- .pa_end = 0x480980ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+- .addr = omap2430_mcspi1_addr_space,
++ .addr = omap2_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* l4 core -> mcspi2 interface */
+-static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
+- {
+- .pa_start = 0x4809a000,
+- .pa_end = 0x4809a0ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mcspi2_hwmod,
+ .clk = "mcspi2_ick",
+- .addr = omap2430_mcspi2_addr_space,
++ .addr = omap2_mcspi2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* l4 core -> mcspi3 interface */
+-static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+- {
+- .pa_start = 0x480b8000,
+- .pa_end = 0x480b80ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mcspi3_hwmod,
+@@ -514,21 +421,12 @@ static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+- {
+- .pa_start = 0x4802a000,
+- .pa_end = 0x4802a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer2 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer2_hwmod,
+ .clk = "gpt2_ick",
+- .addr = omap2430_timer2_addrs,
++ .addr = omap2xxx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -564,21 +462,12 @@ static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+ { .irq = 39, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+- {
+- .pa_start = 0x48078000,
+- .pa_end = 0x48078000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer3 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer3_hwmod,
+ .clk = "gpt3_ick",
+- .addr = omap2430_timer3_addrs,
++ .addr = omap2xxx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -614,21 +503,12 @@ static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+ { .irq = 40, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+- {
+- .pa_start = 0x4807a000,
+- .pa_end = 0x4807a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer4 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer4_hwmod,
+ .clk = "gpt4_ick",
+- .addr = omap2430_timer4_addrs,
++ .addr = omap2xxx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -664,21 +544,12 @@ static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+ { .irq = 41, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+- {
+- .pa_start = 0x4807c000,
+- .pa_end = 0x4807c000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer5 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer5_hwmod,
+ .clk = "gpt5_ick",
+- .addr = omap2430_timer5_addrs,
++ .addr = omap2xxx_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -714,21 +585,12 @@ static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+ { .irq = 42, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+- {
+- .pa_start = 0x4807e000,
+- .pa_end = 0x4807e000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer6 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer6_hwmod,
+ .clk = "gpt6_ick",
+- .addr = omap2430_timer6_addrs,
++ .addr = omap2xxx_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -764,21 +626,12 @@ static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+ { .irq = 43, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+- {
+- .pa_start = 0x48080000,
+- .pa_end = 0x48080000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer7 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer7_hwmod,
+ .clk = "gpt7_ick",
+- .addr = omap2430_timer7_addrs,
++ .addr = omap2xxx_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -814,21 +667,12 @@ static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+ { .irq = 44, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+- {
+- .pa_start = 0x48082000,
+- .pa_end = 0x48082000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer8 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer8_hwmod,
+ .clk = "gpt8_ick",
+- .addr = omap2430_timer8_addrs,
++ .addr = omap2xxx_timer8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -864,21 +708,12 @@ static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+ { .irq = 45, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+- {
+- .pa_start = 0x48084000,
+- .pa_end = 0x48084000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer9 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer9_hwmod,
+ .clk = "gpt9_ick",
+- .addr = omap2430_timer9_addrs,
++ .addr = omap2xxx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -914,21 +749,12 @@ static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+ { .irq = 46, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+- {
+- .pa_start = 0x48086000,
+- .pa_end = 0x48086000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer10_hwmod,
+ .clk = "gpt10_ick",
+- .addr = omap2430_timer10_addrs,
++ .addr = omap2_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -964,21 +790,12 @@ static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+ { .irq = 47, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+- {
+- .pa_start = 0x48088000,
+- .pa_end = 0x48088000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer11_hwmod,
+ .clk = "gpt11_ick",
+- .addr = omap2430_timer11_addrs,
++ .addr = omap2_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1014,21 +831,12 @@ static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+ { .irq = 48, },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+- {
+- .pa_start = 0x4808a000,
+- .pa_end = 0x4808a000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer12 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer12_hwmod,
+ .clk = "gpt12_ick",
+- .addr = omap2430_timer12_addrs,
++ .addr = omap2xxx_timer12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1277,21 +1085,12 @@ static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
+ &omap2430_dss__l3,
+ };
+
+-static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
+- {
+- .pa_start = 0x48050000,
+- .pa_end = 0x480503FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_dss_core_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2430_dss_addrs,
++ .addr = omap2_dss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1355,21 +1154,12 @@ static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
+ { .irq = 25 },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
+- {
+- .pa_start = 0x48050400,
+- .pa_end = 0x480507FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_dss_dispc_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2430_dss_dispc_addrs,
++ .addr = omap2_dss_dispc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1419,21 +1209,12 @@ static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
+ .sysc = &omap2430_rfbi_sysc,
+ };
+
+-static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
+- {
+- .pa_start = 0x48050800,
+- .pa_end = 0x48050BFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+- .addr = omap2430_dss_rfbi_addrs,
++ .addr = omap2_dss_rfbi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1468,22 +1249,12 @@ static struct omap_hwmod_class omap2430_venc_hwmod_class = {
+ .name = "venc",
+ };
+
+-/* dss_venc */
+-static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
+- {
+- .pa_start = 0x48050C00,
+- .pa_end = 0x48050FFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_dss_venc_hwmod,
+ .clk = "dss_54m_fck",
+- .addr = omap2430_dss_venc_addrs,
++ .addr = omap2_dss_venc_addrs,
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+@@ -1916,15 +1687,6 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+ };
+
+-static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
+- {
+- .pa_start = 0x48056000,
+- .pa_end = 0x48056fff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* dma_system -> L3 */
+ static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+ .master = &omap2430_dma_system_hwmod,
+@@ -1943,7 +1705,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_dma_system_hwmod,
+ .clk = "sdma_ick",
+- .addr = omap2430_dma_system_addrs,
++ .addr = omap2_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1994,20 +1756,11 @@ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .irq = 26 },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+- {
+- .pa_start = 0x48094000,
+- .pa_end = 0x480941ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ /* l4_core -> mailbox */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mailbox_hwmod,
+- .addr = omap2430_mailbox_addrs,
++ .addr = omap2_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2279,22 +2032,12 @@ static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+ { .name = "tx", .dma_req = 31 },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
+- {
+- .name = "mpu",
+- .pa_start = 0x48074000,
+- .pa_end = 0x480740ff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> mcbsp1 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+- .addr = omap2430_mcbsp1_addrs,
++ .addr = omap2_mcbsp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2337,22 +2080,12 @@ static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+ { .name = "tx", .dma_req = 33 },
+ };
+
+-static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
+- {
+- .name = "mpu",
+- .pa_start = 0x48076000,
+- .pa_end = 0x480760ff,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> mcbsp2 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+- .addr = omap2430_mcbsp2_addrs,
++ .addr = omap2xxx_mcbsp2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+new file mode 100644
+index 0000000..04637fa
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+@@ -0,0 +1,173 @@
++/*
++ * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
++ *
++ * Copyright (C) 2009-2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * XXX handle crossbar/shared link difference for L3?
++ * XXX these should be marked initdata for multi-OMAP kernels
++ */
++#include <asm/sizes.h>
++
++#include <plat/omap_hwmod.h>
++#include <plat/serial.h>
++
++#include "omap_hwmod_common_data.h"
++
++struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
++ {
++ .pa_start = 0x4809c000,
++ .pa_end = 0x4809c1ff,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
++ {
++ .pa_start = 0x480b4000,
++ .pa_end = 0x480b41ff,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
++ {
++ .pa_start = 0x48070000,
++ .pa_end = 0x48070000 + SZ_128 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
++ {
++ .pa_start = 0x48072000,
++ .pa_end = 0x48072000 + SZ_128 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_dss_addrs[] = {
++ {
++ .pa_start = 0x48050000,
++ .pa_end = 0x48050000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
++ {
++ .pa_start = 0x48050400,
++ .pa_end = 0x48050400 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
++ {
++ .pa_start = 0x48050800,
++ .pa_end = 0x48050800 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
++ {
++ .pa_start = 0x48050C00,
++ .pa_end = 0x48050C00 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
++ {
++ .pa_start = 0x48086000,
++ .pa_end = 0x48086000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
++ {
++ .pa_start = 0x48088000,
++ .pa_end = 0x48088000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
++ {
++ .pa_start = 0x4808a000,
++ .pa_end = 0x4808a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
++ {
++ .pa_start = 0x48098000,
++ .pa_end = 0x48098000 + SZ_256 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
++ {
++ .pa_start = 0x4809a000,
++ .pa_end = 0x4809a000 + SZ_256 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
++ {
++ .pa_start = 0x480b8000,
++ .pa_end = 0x480b8000 + SZ_256 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
++ {
++ .pa_start = 0x48056000,
++ .pa_end = 0x48056000 + SZ_4K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
++ {
++ .pa_start = 0x48094000,
++ .pa_end = 0x48094000 + SZ_512 - 1,
++ .flags = ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48074000,
++ .pa_end = 0x480740ff,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+new file mode 100644
+index 0000000..4f3547c
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+@@ -0,0 +1,130 @@
++/*
++ * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
++ *
++ * Copyright (C) 2009-2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * XXX handle crossbar/shared link difference for L3?
++ * XXX these should be marked initdata for multi-OMAP kernels
++ */
++#include <asm/sizes.h>
++
++#include <plat/omap_hwmod.h>
++#include <plat/serial.h>
++
++#include "omap_hwmod_common_data.h"
++
++struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
++ {
++ .pa_start = OMAP2_UART1_BASE,
++ .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
++ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
++ {
++ .pa_start = OMAP2_UART2_BASE,
++ .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
++ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
++ {
++ .pa_start = OMAP2_UART3_BASE,
++ .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
++ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
++ {
++ .pa_start = 0x4802a000,
++ .pa_end = 0x4802a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
++ {
++ .pa_start = 0x48078000,
++ .pa_end = 0x48078000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
++ {
++ .pa_start = 0x4807a000,
++ .pa_end = 0x4807a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
++ {
++ .pa_start = 0x4807c000,
++ .pa_end = 0x4807c000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
++ {
++ .pa_start = 0x4807e000,
++ .pa_end = 0x4807e000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
++ {
++ .pa_start = 0x48080000,
++ .pa_end = 0x48080000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
++ {
++ .pa_start = 0x48082000,
++ .pa_end = 0x48082000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
++ {
++ .pa_start = 0x48084000,
++ .pa_end = 0x48084000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48076000,
++ .pa_end = 0x480760ff,
++ .flags = ADDR_TYPE_RT
++ },
++ { }
++};
++
++
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 6410779..791f9b2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+ };
+
+ /* L4 CORE -> MMC1 interface */
+-static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
+- {
+- .pa_start = 0x4809c000,
+- .pa_end = 0x4809c1ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+- .addr = omap3xxx_mmc1_addr_space,
++ .addr = omap2430_mmc1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+ };
+
+ /* L4 CORE -> MMC2 interface */
+-static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
+- {
+- .pa_start = 0x480b4000,
+- .pa_end = 0x480b41ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mmc2_hwmod,
+ .clk = "mmchs2_ick",
+- .addr = omap3xxx_mmc2_addr_space,
++ .addr = omap2430_mmc2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+ };
+@@ -318,24 +300,12 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+-/* I2C IP block address space length (in bytes) */
+-#define OMAP2_I2C_AS_LEN 128
+-
+ /* L4 CORE -> I2C1 interface */
+-static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+- {
+- .pa_start = 0x48070000,
+- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c1_hwmod,
+ .clk = "i2c1_ick",
+- .addr = omap3xxx_i2c1_addr_space,
++ .addr = omap2_i2c1_addr_space,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
+@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+ };
+
+ /* L4 CORE -> I2C2 interface */
+-static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+- {
+- .pa_start = 0x48072000,
+- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c2_hwmod,
+ .clk = "i2c2_ick",
+- .addr = omap3xxx_i2c2_addr_space,
++ .addr = omap2_i2c2_addr_space,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
+@@ -375,7 +336,7 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+ static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+ {
+ .pa_start = 0x48060000,
+- .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
++ .pa_end = 0x48060000 + SZ_128 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+@@ -1065,21 +1026,12 @@ static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+ { .irq = 46, },
+ };
+
+-static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+- {
+- .pa_start = 0x48086000,
+- .pa_end = 0x48086000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer10_hwmod,
+ .clk = "gpt10_ick",
+- .addr = omap3xxx_timer10_addrs,
++ .addr = omap2_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1115,21 +1067,12 @@ static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+ { .irq = 47, },
+ };
+
+-static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+- {
+- .pa_start = 0x48088000,
+- .pa_end = 0x48088000 + SZ_1K - 1,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer11_hwmod,
+ .clk = "gpt11_ick",
+- .addr = omap3xxx_timer11_addrs,
++ .addr = omap2_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -1491,21 +1434,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
+ &omap3xxx_dss__l3,
+ };
+
+-static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
+- {
+- .pa_start = 0x48050000,
+- .pa_end = 0x480503FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss */
+ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3430es1_dss_core_hwmod,
+ .clk = "dss_ick",
+- .addr = omap3xxx_dss_addrs,
++ .addr = omap2_dss_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1520,7 +1454,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_core_hwmod,
+ .clk = "dss_ick",
+- .addr = omap3xxx_dss_addrs,
++ .addr = omap2_dss_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+@@ -1625,21 +1559,12 @@ static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
+ { .irq = 25 },
+ };
+
+-static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
+- {
+- .pa_start = 0x48050400,
+- .pa_end = 0x480507FF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_dispc_hwmod,
+ .clk = "dss_ick",
+- .addr = omap3xxx_dss_dispc_addrs,
++ .addr = omap2_dss_dispc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+@@ -1760,21 +1685,12 @@ static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
+ .sysc = &omap3xxx_rfbi_sysc,
+ };
+
+-static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
+- {
+- .pa_start = 0x48050800,
+- .pa_end = 0x48050BFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+- .addr = omap3xxx_dss_rfbi_addrs,
++ .addr = omap2_dss_rfbi_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+@@ -1818,22 +1734,12 @@ static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
+ .name = "venc",
+ };
+
+-/* dss_venc */
+-static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
+- {
+- .pa_start = 0x48050C00,
+- .pa_end = 0x48050FFF,
+- .flags = ADDR_TYPE_RT
+- },
+- { }
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_venc_hwmod,
+ .clk = "dss_tv_fck",
+- .addr = omap3xxx_dss_venc_addrs,
++ .addr = omap2_dss_venc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+@@ -3070,56 +2976,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ };
+
+ /* l4 core -> mcspi1 interface */
+-static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+- {
+- .pa_start = 0x48098000,
+- .pa_end = 0x480980ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi1,
+ .clk = "mcspi1_ick",
+- .addr = omap34xx_mcspi1_addr_space,
++ .addr = omap2_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* l4 core -> mcspi2 interface */
+-static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
+- {
+- .pa_start = 0x4809a000,
+- .pa_end = 0x4809a0ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi2,
+ .clk = "mcspi2_ick",
+- .addr = omap34xx_mcspi2_addr_space,
++ .addr = omap2_mcspi2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ /* l4 core -> mcspi3 interface */
+-static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
+- {
+- .pa_start = 0x480b8000,
+- .pa_end = 0x480b80ff,
+- .flags = ADDR_TYPE_RT,
+- },
+- { }
+-};
+-
+ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi3,
+ .clk = "mcspi3_ick",
+- .addr = omap34xx_mcspi3_addr_space,
++ .addr = omap2430_mcspi3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+index c34e98b..76a2f11 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
++++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+@@ -1,10 +1,10 @@
+ /*
+ * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
+ *
+- * Copyright (C) 2010 Nokia Corporation
++ * Copyright (C) 2010-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+- * Copyright (C) 2010 Texas Instruments, Inc.
++ * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Benoît Cousson
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -16,10 +16,44 @@
+
+ #include <plat/omap_hwmod.h>
+
++/* Common address space across OMAP2xxx */
++extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
++extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
++extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
++extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
++extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
++
++/* Common address space across OMAP2xxx/3xxx */
++extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
++extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
++extern struct omap_hwmod_addr_space omap2_dss_addrs[];
++extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
++extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
++extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
++extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
++extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
++extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
++extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
++extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
++extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
++extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
++extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
++extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
++extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
++
+ /* OMAP hwmod classes - forward declarations */
+ extern struct omap_hwmod_class l3_hwmod_class;
+ extern struct omap_hwmod_class l4_hwmod_class;
+ extern struct omap_hwmod_class mpu_hwmod_class;
+ extern struct omap_hwmod_class iva_hwmod_class;
+
++
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0039-omap_hwmod-use-a-terminator-record-with-omap_hwmod_m.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0039-omap_hwmod-use-a-terminator-record-with-omap_hwmod_m.patch
--- /dev/null
@@ -0,0 +1,2904 @@
+From 4b977d1c5801e50b9277ed377bcebb7d920f8cc0 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:06 -0600
+Subject: [PATCH 039/149] omap_hwmod: use a terminator record with omap_hwmod_mpu_irqs arrays
+
+Previously, struct omap_hwmod_mpu_irqs arrays were unterminated; and
+users of these arrays used the ARRAY_SIZE() macro to determine the
+length of the array. However, ARRAY_SIZE() only works when the array
+is in the same scope as the macro user.
+
+So far this hasn't been a problem. However, to reduce duplicated
+data, a subsequent patch will move common data to a separate, shared
+file. When this is done, ARRAY_SIZE() will no longer be usable.
+
+This patch removes ARRAY_SIZE() usage for struct omap_hwmod_mpu_irqs
+arrays and uses a sentinel value (irq == -1) as the array terminator
+instead.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 30 ++++++-
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 56 ++++++------
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++++++-------
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 92 +++++++++---------
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 127 +++++++++++++-------------
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 8 +-
+ 6 files changed, 205 insertions(+), 180 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 73599f0..b761968 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -679,6 +679,29 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
+ }
+
+ /**
++ * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
++ * @oh: struct omap_hwmod *oh
++ *
++ * Count and return the number of MPU IRQs associated with the hwmod
++ * @oh. Used to allocate struct resource data. Returns 0 if @oh is
++ * NULL.
++ */
++static int _count_mpu_irqs(struct omap_hwmod *oh)
++{
++ struct omap_hwmod_irq_info *ohii;
++ int i = 0;
++
++ if (!oh || !oh->mpu_irqs)
++ return 0;
++
++ do {
++ ohii = &oh->mpu_irqs[i++];
++ } while (ohii->irq != -1);
++
++ return i;
++}
++
++/**
+ * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
+ * @oh: struct omap_hwmod *oh
+ *
+@@ -1984,7 +2007,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ {
+ int ret, i;
+
+- ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
++ ret = _count_mpu_irqs(oh) + oh->sdma_reqs_cnt;
+
+ for (i = 0; i < oh->slaves_cnt; i++)
+ ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+@@ -2004,12 +2027,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ */
+ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+ {
+- int i, j;
++ int i, j, mpu_irqs_cnt;
+ int r = 0;
+
+ /* For each IRQ, DMA, memory area, fill in array.*/
+
+- for (i = 0; i < oh->mpu_irqs_cnt; i++) {
++ mpu_irqs_cnt = _count_mpu_irqs(oh);
++ for (i = 0; i < mpu_irqs_cnt; i++) {
+ (res + r)->name = (oh->mpu_irqs + i)->name;
+ (res + r)->start = (oh->mpu_irqs + i)->irq;
+ (res + r)->end = (oh->mpu_irqs + i)->irq;
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 3ec625c..04730d3 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -296,6 +296,7 @@ static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+ static struct omap_hwmod omap2420_timer1_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+ { .irq = 37, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+@@ -325,7 +326,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+ static struct omap_hwmod omap2420_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2420_timer1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -346,6 +346,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
+ static struct omap_hwmod omap2420_timer2_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+ { .irq = 38, },
++ { .irq = -1 }
+ };
+
+
+@@ -367,7 +368,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+ static struct omap_hwmod omap2420_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2420_timer2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -388,6 +388,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
+ static struct omap_hwmod omap2420_timer3_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+ { .irq = 39, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer3 */
+@@ -408,7 +409,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+ static struct omap_hwmod omap2420_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2420_timer3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -429,6 +429,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
+ static struct omap_hwmod omap2420_timer4_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+ { .irq = 40, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer4 */
+@@ -449,7 +450,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+ static struct omap_hwmod omap2420_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2420_timer4_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -470,6 +470,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
+ static struct omap_hwmod omap2420_timer5_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+ { .irq = 41, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer5 */
+@@ -490,7 +491,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+ static struct omap_hwmod omap2420_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2420_timer5_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -512,6 +512,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
+ static struct omap_hwmod omap2420_timer6_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+ { .irq = 42, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer6 */
+@@ -532,7 +533,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+ static struct omap_hwmod omap2420_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2420_timer6_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -553,6 +553,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
+ static struct omap_hwmod omap2420_timer7_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+ { .irq = 43, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer7 */
+@@ -573,7 +574,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+ static struct omap_hwmod omap2420_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2420_timer7_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -594,6 +594,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
+ static struct omap_hwmod omap2420_timer8_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+ { .irq = 44, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer8 */
+@@ -614,7 +615,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+ static struct omap_hwmod omap2420_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2420_timer8_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -635,6 +635,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
+ static struct omap_hwmod omap2420_timer9_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+ { .irq = 45, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer9 */
+@@ -655,7 +656,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+ static struct omap_hwmod omap2420_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2420_timer9_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -676,6 +676,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
+ static struct omap_hwmod omap2420_timer10_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+ { .irq = 46, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer10 */
+@@ -696,7 +697,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+ static struct omap_hwmod omap2420_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2420_timer10_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -717,6 +717,7 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
+ static struct omap_hwmod omap2420_timer11_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+ { .irq = 47, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer11 */
+@@ -737,7 +738,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+ static struct omap_hwmod omap2420_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2420_timer11_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -758,6 +758,7 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
+ static struct omap_hwmod omap2420_timer12_hwmod;
+ static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+ { .irq = 48, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer12 */
+@@ -778,7 +779,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+ static struct omap_hwmod omap2420_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap2420_timer12_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+@@ -879,6 +879,7 @@ static struct omap_hwmod_class uart_class = {
+
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ { .irq = INT_24XX_UART1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+@@ -893,7 +894,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+ static struct omap_hwmod omap2420_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = uart1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -916,6 +916,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ { .irq = INT_24XX_UART2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+@@ -930,7 +931,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+ static struct omap_hwmod omap2420_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = uart2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -953,6 +953,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ { .irq = INT_24XX_UART3_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+@@ -967,7 +968,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+ static struct omap_hwmod omap2420_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = uart3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1087,6 +1087,7 @@ static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
+
+ static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
+ { .irq = 25 },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1113,7 +1114,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap2420_dispc_hwmod_class,
+ .mpu_irqs = omap2420_dispc_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1254,6 +1254,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
+
+ static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+@@ -1268,7 +1269,6 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+ static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+@@ -1293,6 +1293,7 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
+
+ static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+@@ -1307,7 +1308,6 @@ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+ static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+@@ -1430,6 +1430,7 @@ static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+ /* gpio1 */
+ static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+@@ -1440,7 +1441,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap242x_gpio1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1461,6 +1461,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
+ /* gpio2 */
+ static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+@@ -1471,7 +1472,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap242x_gpio2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1492,6 +1492,7 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
+ /* gpio3 */
+ static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+@@ -1502,7 +1503,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap242x_gpio3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1523,6 +1523,7 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
+ /* gpio4 */
+ static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+@@ -1533,7 +1534,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap242x_gpio4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1580,6 +1580,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
++ { .irq = -1 }
+ };
+
+ /* dma_system -> L3 */
+@@ -1613,7 +1614,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2420_dma_hwmod_class,
+ .mpu_irqs = omap2420_dma_system_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
+ .main_clk = "core_l3_ck",
+ .slaves = omap2420_dma_system_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
+@@ -1650,6 +1650,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = "dsp", .irq = 26 },
+ { .name = "iva", .irq = 34 },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> mailbox */
+@@ -1669,7 +1670,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2420_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+@@ -1711,6 +1711,7 @@ static struct omap_hwmod_class omap2420_mcspi_class = {
+ /* mcspi1 */
+ static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
+ { .irq = 65 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+@@ -1735,7 +1736,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2420_mcspi1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
+ .sdma_reqs = omap2420_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -1758,6 +1758,7 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ /* mcspi2 */
+ static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
+ { .irq = 66 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+@@ -1778,7 +1779,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2420_mcspi2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
+ .sdma_reqs = omap2420_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+@@ -1811,6 +1811,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
+ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+ { .name = "tx", .irq = 59 },
+ { .name = "rx", .irq = 60 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+@@ -1836,7 +1837,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
+ .sdma_reqs = omap2420_mcbsp1_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+@@ -1858,6 +1858,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+@@ -1883,7 +1884,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
+ .sdma_reqs = omap2420_mcbsp2_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 9531ef2..2c28468 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -369,6 +369,7 @@ static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+ static struct omap_hwmod omap2430_timer1_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+ { .irq = 37, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+@@ -398,7 +399,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+ static struct omap_hwmod omap2430_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2430_timer1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -419,6 +419,7 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
+ static struct omap_hwmod omap2430_timer2_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+ { .irq = 38, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer2 */
+@@ -439,7 +440,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+ static struct omap_hwmod omap2430_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2430_timer2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -460,6 +460,7 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
+ static struct omap_hwmod omap2430_timer3_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+ { .irq = 39, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer3 */
+@@ -480,7 +481,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+ static struct omap_hwmod omap2430_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2430_timer3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -501,6 +501,7 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
+ static struct omap_hwmod omap2430_timer4_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+ { .irq = 40, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer4 */
+@@ -521,7 +522,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+ static struct omap_hwmod omap2430_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2430_timer4_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -542,6 +542,7 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
+ static struct omap_hwmod omap2430_timer5_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+ { .irq = 41, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer5 */
+@@ -562,7 +563,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+ static struct omap_hwmod omap2430_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2430_timer5_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -583,6 +583,7 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
+ static struct omap_hwmod omap2430_timer6_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+ { .irq = 42, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer6 */
+@@ -603,7 +604,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+ static struct omap_hwmod omap2430_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2430_timer6_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -624,6 +624,7 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
+ static struct omap_hwmod omap2430_timer7_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+ { .irq = 43, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer7 */
+@@ -644,7 +645,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+ static struct omap_hwmod omap2430_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2430_timer7_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -665,6 +665,7 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
+ static struct omap_hwmod omap2430_timer8_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+ { .irq = 44, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer8 */
+@@ -685,7 +686,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+ static struct omap_hwmod omap2430_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2430_timer8_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -706,6 +706,7 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
+ static struct omap_hwmod omap2430_timer9_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+ { .irq = 45, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer9 */
+@@ -726,7 +727,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+ static struct omap_hwmod omap2430_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2430_timer9_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -747,6 +747,7 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
+ static struct omap_hwmod omap2430_timer10_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+ { .irq = 46, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer10 */
+@@ -767,7 +768,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+ static struct omap_hwmod omap2430_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2430_timer10_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -788,6 +788,7 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
+ static struct omap_hwmod omap2430_timer11_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+ { .irq = 47, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer11 */
+@@ -808,7 +809,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+ static struct omap_hwmod omap2430_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2430_timer11_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -829,6 +829,7 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
+ static struct omap_hwmod omap2430_timer12_hwmod;
+ static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+ { .irq = 48, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer12 */
+@@ -849,7 +850,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+ static struct omap_hwmod omap2430_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap2430_timer12_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+@@ -950,6 +950,7 @@ static struct omap_hwmod_class uart_class = {
+
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ { .irq = INT_24XX_UART1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+@@ -964,7 +965,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+ static struct omap_hwmod omap2430_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = uart1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -987,6 +987,7 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ { .irq = INT_24XX_UART2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+@@ -1001,7 +1002,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+ static struct omap_hwmod omap2430_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = uart2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -1024,6 +1024,7 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ { .irq = INT_24XX_UART3_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+@@ -1038,7 +1039,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+ static struct omap_hwmod omap2430_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = uart3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1152,6 +1152,7 @@ static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
+
+ static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
+ { .irq = 25 },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1172,7 +1173,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap2430_dispc_hwmod_class,
+ .mpu_irqs = omap2430_dispc_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1304,6 +1304,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
+
+ static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+@@ -1318,7 +1319,6 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2chs1_fck",
+@@ -1350,6 +1350,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
+
+ static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+@@ -1364,7 +1365,6 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+ static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2chs2_fck",
+@@ -1504,6 +1504,7 @@ static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+ /* gpio1 */
+ static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+@@ -1514,7 +1515,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1535,6 +1535,7 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
+ /* gpio2 */
+ static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+@@ -1545,7 +1546,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1566,6 +1566,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
+ /* gpio3 */
+ static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+@@ -1576,7 +1577,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1597,6 +1597,7 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
+ /* gpio4 */
+ static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+@@ -1607,7 +1608,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1628,6 +1628,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
+ /* gpio5 */
+ static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
+@@ -1638,7 +1639,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
+ .name = "gpio5",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
+ .main_clk = "gpio5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1685,6 +1685,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
++ { .irq = -1 }
+ };
+
+ /* dma_system -> L3 */
+@@ -1718,7 +1719,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2430_dma_hwmod_class,
+ .mpu_irqs = omap2430_dma_system_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
+ .main_clk = "core_l3_ck",
+ .slaves = omap2430_dma_system_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
+@@ -1754,6 +1754,7 @@ static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ static struct omap_hwmod omap2430_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .irq = 26 },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> mailbox */
+@@ -1773,7 +1774,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2430_mailbox_hwmod_class,
+ .mpu_irqs = omap2430_mailbox_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+@@ -1815,6 +1815,7 @@ static struct omap_hwmod_class omap2430_mcspi_class = {
+ /* mcspi1 */
+ static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
+ { .irq = 65 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+@@ -1839,7 +1840,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2430_mcspi1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
+ .sdma_reqs = omap2430_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -1862,6 +1862,7 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ /* mcspi2 */
+ static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
+ { .irq = 66 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+@@ -1882,7 +1883,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2430_mcspi2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
+ .sdma_reqs = omap2430_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+@@ -1905,6 +1905,7 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ /* mcspi3 */
+ static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
+ { .irq = 91 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+@@ -1925,7 +1926,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+ static struct omap_hwmod omap2430_mcspi3_hwmod = {
+ .name = "mcspi3_hwmod",
+ .mpu_irqs = omap2430_mcspi3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
+ .sdma_reqs = omap2430_mcspi3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+@@ -1970,12 +1970,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
+
+ { .name = "mc", .irq = 92 },
+ { .name = "dma", .irq = 93 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
+ .main_clk = "usbhs_ick",
+ .prcm = {
+ .omap2 = {
+@@ -2025,6 +2025,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+ { .name = "rx", .irq = 60 },
+ { .name = "ovr", .irq = 61 },
+ { .name = "common", .irq = 64 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+@@ -2050,7 +2051,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
+ .sdma_reqs = omap2430_mcbsp1_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+@@ -2073,6 +2073,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
+ { .name = "common", .irq = 16 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+@@ -2098,7 +2099,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
+ .sdma_reqs = omap2430_mcbsp2_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+@@ -2121,6 +2121,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+ { .name = "tx", .irq = 89 },
+ { .name = "rx", .irq = 90 },
+ { .name = "common", .irq = 17 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+@@ -2156,7 +2157,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
+ .sdma_reqs = omap2430_mcbsp3_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+ .main_clk = "mcbsp3_fck",
+@@ -2179,6 +2179,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+ { .name = "tx", .irq = 54 },
+ { .name = "rx", .irq = 55 },
+ { .name = "common", .irq = 18 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+@@ -2214,7 +2215,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
+ .sdma_reqs = omap2430_mcbsp4_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
+ .main_clk = "mcbsp4_fck",
+@@ -2237,6 +2237,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+ { .name = "tx", .irq = 81 },
+ { .name = "rx", .irq = 82 },
+ { .name = "common", .irq = 19 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+@@ -2272,7 +2273,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+ .name = "mcbsp5",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
+ .sdma_reqs = omap2430_mcbsp5_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
+ .main_clk = "mcbsp5_fck",
+@@ -2312,6 +2312,7 @@ static struct omap_hwmod_class omap2430_mmc_class = {
+
+ static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+ { .irq = 83 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+@@ -2335,7 +2336,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
+ .name = "mmc1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
+ .sdma_reqs = omap2430_mmc1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
+ .opt_clks = omap2430_mmc1_opt_clks,
+@@ -2361,6 +2361,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
+
+ static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+ { .irq = 86 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+@@ -2380,7 +2381,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
+ .name = "mmc2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
+ .sdma_reqs = omap2430_mmc2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
+ .opt_clks = omap2430_mmc2_opt_clks,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 791f9b2..cc178b5 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
+ { .irq = INT_34XX_L3_DBG_IRQ },
+ { .irq = INT_34XX_L3_APP_IRQ },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+@@ -151,7 +152,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &l3_hwmod_class,
+ .mpu_irqs = omap3xxx_l3_main_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
+ .masters = omap3xxx_l3_main_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
+ .slaves = omap3xxx_l3_main_slaves,
+@@ -574,6 +574,7 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+ static struct omap_hwmod omap3xxx_timer1_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+ { .irq = 37, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+@@ -603,7 +604,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap3xxx_timer1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -624,6 +624,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ static struct omap_hwmod omap3xxx_timer2_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+ { .irq = 38, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+@@ -653,7 +654,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap3xxx_timer2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -674,6 +674,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
+ static struct omap_hwmod omap3xxx_timer3_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+ { .irq = 39, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+@@ -703,7 +704,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap3xxx_timer3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -724,6 +724,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
+ static struct omap_hwmod omap3xxx_timer4_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+ { .irq = 40, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+@@ -753,7 +754,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap3xxx_timer4_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -774,6 +774,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
+ static struct omap_hwmod omap3xxx_timer5_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+ { .irq = 41, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+@@ -803,7 +804,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap3xxx_timer5_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -824,6 +824,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
+ static struct omap_hwmod omap3xxx_timer6_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+ { .irq = 42, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+@@ -853,7 +854,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap3xxx_timer6_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -874,6 +874,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
+ static struct omap_hwmod omap3xxx_timer7_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+ { .irq = 43, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+@@ -903,7 +904,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap3xxx_timer7_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -924,6 +924,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
+ static struct omap_hwmod omap3xxx_timer8_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+ { .irq = 44, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+@@ -953,7 +954,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap3xxx_timer8_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -974,6 +974,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
+ static struct omap_hwmod omap3xxx_timer9_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+ { .irq = 45, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+@@ -1003,7 +1004,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap3xxx_timer9_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1024,6 +1024,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
+ static struct omap_hwmod omap3xxx_timer10_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+ { .irq = 46, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer10 */
+@@ -1044,7 +1045,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap3xxx_timer10_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1065,6 +1065,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
+ static struct omap_hwmod omap3xxx_timer11_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+ { .irq = 47, },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> timer11 */
+@@ -1085,7 +1086,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap3xxx_timer11_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1106,6 +1106,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
+ static struct omap_hwmod omap3xxx_timer12_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
+ { .irq = 95, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+@@ -1135,7 +1136,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
+ static struct omap_hwmod omap3xxx_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap3xxx_timer12_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1256,6 +1256,7 @@ static struct omap_hwmod_class uart_class = {
+
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ { .irq = INT_24XX_UART1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+@@ -1270,7 +1271,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = uart1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -1293,6 +1293,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ { .irq = INT_24XX_UART2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+@@ -1307,7 +1308,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = uart2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -1330,6 +1330,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ { .irq = INT_24XX_UART3_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+@@ -1344,7 +1345,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = uart3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1367,6 +1367,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+
+ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+ { .irq = INT_36XX_UART4_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+@@ -1381,7 +1382,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ .name = "uart4",
+ .mpu_irqs = uart4_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
+ .sdma_reqs = uart4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
+ .main_clk = "uart4_fck",
+@@ -1557,6 +1557,7 @@ static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
+
+ static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
+ { .irq = 25 },
++ { .irq = -1 }
+ };
+
+ /* l4_core -> dss_dispc */
+@@ -1584,7 +1585,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap3xxx_dispc_hwmod_class,
+ .mpu_irqs = omap3xxx_dispc_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1612,6 +1612,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
+
+ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
+ { .irq = 25 },
++ { .irq = -1 }
+ };
+
+ /* dss_dsi1 */
+@@ -1648,7 +1649,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap3xxx_dsi_hwmod_class,
+ .mpu_irqs = omap3xxx_dsi1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1783,6 +1783,7 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
+
+ static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+@@ -1797,7 +1798,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+@@ -1825,6 +1825,7 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
+
+ static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+@@ -1839,7 +1840,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+@@ -1867,6 +1867,7 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
+
+ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = INT_34XX_I2C3_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+@@ -1881,7 +1882,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+ .name = "i2c3",
+ .mpu_irqs = i2c3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
+ .sdma_reqs = i2c3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+@@ -2034,6 +2034,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
+ /* gpio1 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+@@ -2048,7 +2049,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+ .main_clk = "gpio1_ick",
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+@@ -2071,6 +2071,7 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ /* gpio2 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+@@ -2085,7 +2086,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+ .main_clk = "gpio2_ick",
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+@@ -2108,6 +2108,7 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ /* gpio3 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+@@ -2122,7 +2123,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+ .main_clk = "gpio3_ick",
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+@@ -2145,6 +2145,7 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ /* gpio4 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+@@ -2159,7 +2160,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+ .main_clk = "gpio4_ick",
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+@@ -2182,6 +2182,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+ /* gpio5 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+@@ -2196,7 +2197,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+ .name = "gpio5",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
+ .main_clk = "gpio5_ick",
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+@@ -2219,6 +2219,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+ /* gpio6 */
+ static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
+ { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+@@ -2233,7 +2234,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
+ .name = "gpio6",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio6_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
+ .main_clk = "gpio6_ick",
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+@@ -2292,6 +2292,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
+ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+@@ -2326,7 +2327,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap3xxx_dma_hwmod_class,
+ .mpu_irqs = omap3xxx_dma_system_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+ .main_clk = "core_l3_ick",
+ .prcm = {
+ .omap2 = {
+@@ -2371,6 +2371,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+ { .name = "irq", .irq = 16 },
+ { .name = "tx", .irq = 59 },
+ { .name = "rx", .irq = 60 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
+@@ -2406,7 +2407,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
+ .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+@@ -2429,6 +2429,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+ { .name = "irq", .irq = 17 },
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
+@@ -2469,7 +2470,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
+ .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+@@ -2493,6 +2493,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+ { .name = "irq", .irq = 22 },
+ { .name = "tx", .irq = 89 },
+ { .name = "rx", .irq = 90 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
+@@ -2532,7 +2533,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
+ .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+ .main_clk = "mcbsp3_fck",
+@@ -2556,6 +2556,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
+ { .name = "irq", .irq = 23 },
+ { .name = "tx", .irq = 54 },
+ { .name = "rx", .irq = 55 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
+@@ -2591,7 +2592,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
+ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
+ .main_clk = "mcbsp4_fck",
+@@ -2614,6 +2614,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
+ { .name = "irq", .irq = 27 },
+ { .name = "tx", .irq = 81 },
+ { .name = "rx", .irq = 82 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
+@@ -2649,7 +2650,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
+ .name = "mcbsp5",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
+ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
+ .main_clk = "mcbsp5_fck",
+@@ -2682,6 +2682,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
+ /* mcbsp2_sidetone */
+ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
+ { .name = "irq", .irq = 4 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+@@ -2712,7 +2713,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
+ .name = "mcbsp2_sidetone",
+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2731,6 +2731,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
+ /* mcbsp3_sidetone */
+ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
+ { .name = "irq", .irq = 5 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+@@ -2761,7 +2762,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
+ .name = "mcbsp3_sidetone",
+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2931,6 +2931,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ static struct omap_hwmod omap3xxx_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .irq = 26 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+@@ -2959,7 +2960,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+@@ -3046,6 +3046,7 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
+ /* mcspi1 */
+ static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
+ { .name = "irq", .irq = 65 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+@@ -3070,7 +3071,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi1 = {
+ .name = "mcspi1",
+ .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
+ .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -3093,6 +3093,7 @@ static struct omap_hwmod omap34xx_mcspi1 = {
+ /* mcspi2 */
+ static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
+ { .name = "irq", .irq = 66 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+@@ -3113,7 +3114,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi2 = {
+ .name = "mcspi2",
+ .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
+ .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+@@ -3136,6 +3136,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
+ /* mcspi3 */
+ static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
+ { .name = "irq", .irq = 91 }, /* 91 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+@@ -3156,7 +3157,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi3 = {
+ .name = "mcspi3",
+ .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
+ .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+@@ -3179,6 +3179,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
+ /* SPI4 */
+ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+@@ -3197,7 +3198,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi4 = {
+ .name = "mcspi4",
+ .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
+ .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
+ .main_clk = "mcspi4_fck",
+@@ -3241,12 +3241,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
+
+ { .name = "mc", .irq = 92 },
+ { .name = "dma", .irq = 93 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
+ .main_clk = "hsotgusb_ick",
+ .prcm = {
+ .omap2 = {
+@@ -3278,6 +3278,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+ static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+ { .name = "mc", .irq = 71 },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_class am35xx_usbotg_class = {
+@@ -3288,7 +3289,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
+ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+ .name = "am35x_otg_hs",
+ .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+ .main_clk = NULL,
+ .prcm = {
+ .omap2 = {
+@@ -3324,6 +3324,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
+
+ static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
+ { .irq = 83, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
+@@ -3346,7 +3347,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
+ .sdma_reqs = omap34xx_mmc1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
+ .opt_clks = omap34xx_mmc1_opt_clks,
+@@ -3372,6 +3372,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+
+ static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
+ { .irq = INT_24XX_MMC2_IRQ, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
+@@ -3390,7 +3391,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
+ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+ .name = "mmc2",
+ .mpu_irqs = omap34xx_mmc2_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
+ .sdma_reqs = omap34xx_mmc2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
+ .opt_clks = omap34xx_mmc2_opt_clks,
+@@ -3415,6 +3415,7 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+
+ static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
+ { .irq = 94, },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
+@@ -3433,7 +3434,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
+ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
+ .name = "mmc3",
+ .mpu_irqs = omap34xx_mmc3_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
+ .sdma_reqs = omap34xx_mmc3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
+ .opt_clks = omap34xx_mmc3_opt_clks,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index f8ccc4a..f7ff937 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -115,6 +115,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+
+ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+ { .irq = 113 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod omap44xx_dmm_hwmod = {
+@@ -123,7 +124,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
+ .slaves = omap44xx_dmm_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
+ .mpu_irqs = omap44xx_dmm_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -268,6 +268,7 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+ static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
+ { .irq = 9 + OMAP44XX_IRQ_GIC_START },
+ { .irq = 10 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+@@ -303,7 +304,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap44xx_l3_hwmod_class,
+ .mpu_irqs = omap44xx_l3_targ_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -673,6 +673,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
+ /* aess */
+ static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
+ { .irq = 99 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
+@@ -737,7 +738,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .name = "aess",
+ .class = &omap44xx_aess_hwmod_class,
+ .mpu_irqs = omap44xx_aess_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
+ .sdma_reqs = omap44xx_aess_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
+ .main_clk = "aess_fck",
+@@ -876,6 +876,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
+ { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
+ { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
+ { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ /* dma_system master ports */
+@@ -910,7 +911,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &omap44xx_dma_hwmod_class,
+ .mpu_irqs = omap44xx_dma_system_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
+ .main_clk = "l3_div_ck",
+ .prcm = {
+ .omap4 = {
+@@ -949,6 +949,7 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
+ static struct omap_hwmod omap44xx_dmic_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
+ { .irq = 114 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
+@@ -1001,7 +1002,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .name = "dmic",
+ .class = &omap44xx_dmic_hwmod_class,
+ .mpu_irqs = omap44xx_dmic_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
+ .sdma_reqs = omap44xx_dmic_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
+ .main_clk = "dmic_fck",
+@@ -1027,6 +1027,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
+ /* dsp */
+ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
+ { .irq = 28 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
+@@ -1083,7 +1084,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .name = "dsp",
+ .class = &omap44xx_dsp_hwmod_class,
+ .mpu_irqs = omap44xx_dsp_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
+ .rst_lines = omap44xx_dsp_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
+ .main_clk = "dsp_fck",
+@@ -1216,6 +1216,7 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
+ static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+ { .irq = 25 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+@@ -1268,7 +1269,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap44xx_dispc_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
+ .main_clk = "dss_fck",
+@@ -1307,6 +1307,7 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
+ static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+ { .irq = 53 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
+@@ -1359,7 +1360,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
+ .main_clk = "dss_fck",
+@@ -1377,6 +1377,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+ { .irq = 84 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
+@@ -1429,7 +1430,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .name = "dss_dsi2",
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
+ .main_clk = "dss_fck",
+@@ -1467,6 +1467,7 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
+ static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
+ { .irq = 101 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
+@@ -1519,7 +1520,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &omap44xx_hdmi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_hdmi_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
+ .main_clk = "dss_fck",
+@@ -1717,6 +1717,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
+ static struct omap_hwmod omap44xx_gpio1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
+ { .irq = 29 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+@@ -1750,7 +1751,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &omap44xx_gpio_hwmod_class,
+ .mpu_irqs = omap44xx_gpio1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
+ .main_clk = "gpio1_ick",
+ .prcm = {
+ .omap4 = {
+@@ -1769,6 +1769,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ static struct omap_hwmod omap44xx_gpio2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
+ { .irq = 30 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+@@ -1803,7 +1804,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
+ .main_clk = "gpio2_ick",
+ .prcm = {
+ .omap4 = {
+@@ -1822,6 +1822,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ static struct omap_hwmod omap44xx_gpio3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
+ { .irq = 31 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+@@ -1856,7 +1857,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
+ .main_clk = "gpio3_ick",
+ .prcm = {
+ .omap4 = {
+@@ -1875,6 +1875,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ static struct omap_hwmod omap44xx_gpio4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
+ { .irq = 32 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+@@ -1909,7 +1910,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
+ .main_clk = "gpio4_ick",
+ .prcm = {
+ .omap4 = {
+@@ -1928,6 +1928,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ static struct omap_hwmod omap44xx_gpio5_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
+ { .irq = 33 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+@@ -1962,7 +1963,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
+ .main_clk = "gpio5_ick",
+ .prcm = {
+ .omap4 = {
+@@ -1981,6 +1981,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ static struct omap_hwmod omap44xx_gpio6_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
+ { .irq = 34 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+@@ -2015,7 +2016,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio6_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
+ .main_clk = "gpio6_ick",
+ .prcm = {
+ .omap4 = {
+@@ -2059,6 +2059,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
+ { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
+ { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
+ { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ /* hsi master ports */
+@@ -2093,7 +2094,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .name = "hsi",
+ .class = &omap44xx_hsi_hwmod_class,
+ .mpu_irqs = omap44xx_hsi_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
+ .main_clk = "hsi_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2132,6 +2132,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+ static struct omap_hwmod omap44xx_i2c1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+ { .irq = 56 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+@@ -2167,7 +2168,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+@@ -2185,6 +2185,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ static struct omap_hwmod omap44xx_i2c2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+ { .irq = 57 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+@@ -2220,7 +2221,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+@@ -2238,6 +2238,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ static struct omap_hwmod omap44xx_i2c3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+ { .irq = 61 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+@@ -2273,7 +2274,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+@@ -2291,6 +2291,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ static struct omap_hwmod omap44xx_i2c4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+ { .irq = 62 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+@@ -2326,7 +2327,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .class = &omap44xx_i2c_hwmod_class,
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+ .main_clk = "i2c4_fck",
+@@ -2352,6 +2352,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
+ /* ipu */
+ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
+ { .irq = 100 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+@@ -2418,7 +2419,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .name = "ipu",
+ .class = &omap44xx_ipu_hwmod_class,
+ .mpu_irqs = omap44xx_ipu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
+ .rst_lines = omap44xx_ipu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
+ .main_clk = "ipu_fck",
+@@ -2459,6 +2459,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
+ /* iss */
+ static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
+ { .irq = 24 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
+@@ -2504,7 +2505,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .name = "iss",
+ .class = &omap44xx_iss_hwmod_class,
+ .mpu_irqs = omap44xx_iss_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
+ .sdma_reqs = omap44xx_iss_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
+ .main_clk = "iss_fck",
+@@ -2536,6 +2536,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
+ { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
+ { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
+ { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
+@@ -2614,7 +2615,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .name = "iva",
+ .class = &omap44xx_iva_hwmod_class,
+ .mpu_irqs = omap44xx_iva_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
+ .rst_lines = omap44xx_iva_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
+ .main_clk = "iva_fck",
+@@ -2657,6 +2657,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
+ static struct omap_hwmod omap44xx_kbd_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
+ { .irq = 120 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+@@ -2686,7 +2687,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .name = "kbd",
+ .class = &omap44xx_kbd_hwmod_class,
+ .mpu_irqs = omap44xx_kbd_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
+ .main_clk = "kbd_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2722,6 +2722,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ static struct omap_hwmod omap44xx_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .irq = 26 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+@@ -2751,7 +2752,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+@@ -2785,6 +2785,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
+ static struct omap_hwmod omap44xx_mcbsp1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
+ { .irq = 17 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
+@@ -2840,7 +2841,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
+ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
+ .main_clk = "mcbsp1_fck",
+@@ -2858,6 +2858,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ static struct omap_hwmod omap44xx_mcbsp2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
+ { .irq = 22 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
+@@ -2913,7 +2914,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
+ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
+ .main_clk = "mcbsp2_fck",
+@@ -2931,6 +2931,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ static struct omap_hwmod omap44xx_mcbsp3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
+ { .irq = 23 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
+@@ -2986,7 +2987,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
+ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
+ .main_clk = "mcbsp3_fck",
+@@ -3004,6 +3004,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ static struct omap_hwmod omap44xx_mcbsp4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
+ { .irq = 16 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
+@@ -3038,7 +3039,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
+ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
+ .main_clk = "mcbsp4_fck",
+@@ -3077,6 +3077,7 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
+ static struct omap_hwmod omap44xx_mcpdm_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
+ { .irq = 112 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
+@@ -3130,7 +3131,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .name = "mcpdm",
+ .class = &omap44xx_mcpdm_hwmod_class,
+ .mpu_irqs = omap44xx_mcpdm_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
+ .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
+ .main_clk = "mcpdm_fck",
+@@ -3170,6 +3170,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+ static struct omap_hwmod omap44xx_mcspi1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+ { .irq = 65 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+@@ -3215,7 +3216,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+ .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -3234,6 +3234,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ static struct omap_hwmod omap44xx_mcspi2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+ { .irq = 66 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+@@ -3275,7 +3276,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+ .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+@@ -3294,6 +3294,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ static struct omap_hwmod omap44xx_mcspi3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+ { .irq = 91 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+@@ -3335,7 +3336,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+ .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+@@ -3354,6 +3354,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ static struct omap_hwmod omap44xx_mcspi4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+ { .irq = 48 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+@@ -3393,7 +3394,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+ .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+ .main_clk = "mcspi4_fck",
+@@ -3434,6 +3434,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
+
+ static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+ { .irq = 83 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
+@@ -3478,7 +3479,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
+ .sdma_reqs = omap44xx_mmc1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
+ .main_clk = "mmc1_fck",
+@@ -3498,6 +3498,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ /* mmc2 */
+ static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
+ { .irq = 86 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
+@@ -3537,7 +3538,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .name = "mmc2",
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
+ .sdma_reqs = omap44xx_mmc2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
+ .main_clk = "mmc2_fck",
+@@ -3557,6 +3557,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ static struct omap_hwmod omap44xx_mmc3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
+ { .irq = 94 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
+@@ -3591,7 +3592,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .name = "mmc3",
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
+ .sdma_reqs = omap44xx_mmc3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
+ .main_clk = "mmc3_fck",
+@@ -3609,6 +3609,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ static struct omap_hwmod omap44xx_mmc4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
+ { .irq = 96 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
+@@ -3643,7 +3644,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .name = "mmc4",
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
++
+ .sdma_reqs = omap44xx_mmc4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
+ .main_clk = "mmc4_fck",
+@@ -3661,6 +3662,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ static struct omap_hwmod omap44xx_mmc5_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
+ { .irq = 59 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
+@@ -3695,7 +3697,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .name = "mmc5",
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
+ .sdma_reqs = omap44xx_mmc5_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
+ .main_clk = "mmc5_fck",
+@@ -3723,6 +3724,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+ { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
+ { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
+ { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ /* mpu master ports */
+@@ -3737,7 +3739,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
+ .class = &omap44xx_mpu_hwmod_class,
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = omap44xx_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+@@ -3779,6 +3780,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+ static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+ { .irq = 19 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+@@ -3808,7 +3810,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .name = "smartreflex_core",
+ .class = &omap44xx_smartreflex_hwmod_class,
+ .mpu_irqs = omap44xx_smartreflex_core_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
++
+ .main_clk = "smartreflex_core_fck",
+ .vdd_name = "core",
+ .prcm = {
+@@ -3825,6 +3827,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+ { .irq = 102 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+@@ -3854,7 +3857,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .name = "smartreflex_iva",
+ .class = &omap44xx_smartreflex_hwmod_class,
+ .mpu_irqs = omap44xx_smartreflex_iva_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+ .main_clk = "smartreflex_iva_fck",
+ .vdd_name = "iva",
+ .prcm = {
+@@ -3871,6 +3873,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+ { .irq = 18 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+@@ -3900,7 +3903,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ .name = "smartreflex_mpu",
+ .class = &omap44xx_smartreflex_hwmod_class,
+ .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+ .main_clk = "smartreflex_mpu_fck",
+ .vdd_name = "mpu",
+ .prcm = {
+@@ -4016,6 +4018,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+ static struct omap_hwmod omap44xx_timer1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+@@ -4045,7 +4048,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4061,6 +4063,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ static struct omap_hwmod omap44xx_timer2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+@@ -4090,7 +4093,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4106,6 +4108,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ static struct omap_hwmod omap44xx_timer3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
+ { .irq = 39 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+@@ -4135,7 +4138,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4151,6 +4153,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ static struct omap_hwmod omap44xx_timer4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
+ { .irq = 40 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+@@ -4180,7 +4183,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4196,6 +4198,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ static struct omap_hwmod omap44xx_timer5_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
+ { .irq = 41 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+@@ -4244,7 +4247,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer5_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4260,6 +4262,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ static struct omap_hwmod omap44xx_timer6_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
+ { .irq = 42 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+@@ -4308,7 +4311,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer6_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
++
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4324,6 +4327,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ static struct omap_hwmod omap44xx_timer7_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
+ { .irq = 43 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+@@ -4372,7 +4376,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer7_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4388,6 +4391,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ static struct omap_hwmod omap44xx_timer8_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
+ { .irq = 44 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+@@ -4436,7 +4440,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer8_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
+ .main_clk = "timer8_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4452,6 +4455,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ static struct omap_hwmod omap44xx_timer9_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
+ { .irq = 45 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+@@ -4481,7 +4485,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer9_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
+ .main_clk = "timer9_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4497,6 +4500,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ static struct omap_hwmod omap44xx_timer10_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
+ { .irq = 46 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+@@ -4526,7 +4530,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer10_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
+ .main_clk = "timer10_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4542,6 +4545,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ static struct omap_hwmod omap44xx_timer11_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
+ { .irq = 47 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+@@ -4571,7 +4575,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer11_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
+ .main_clk = "timer11_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4609,6 +4612,7 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
+ static struct omap_hwmod omap44xx_uart1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+ { .irq = 72 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+@@ -4643,7 +4647,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart1_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
+ .sdma_reqs = omap44xx_uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -4661,6 +4664,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ static struct omap_hwmod omap44xx_uart2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+ { .irq = 73 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+@@ -4695,7 +4699,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
+ .sdma_reqs = omap44xx_uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -4713,6 +4716,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ static struct omap_hwmod omap44xx_uart3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+ { .irq = 74 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+@@ -4748,7 +4752,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .class = &omap44xx_uart_hwmod_class,
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = omap44xx_uart3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
+ .sdma_reqs = omap44xx_uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -4766,6 +4769,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ static struct omap_hwmod omap44xx_uart4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+ { .irq = 70 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+@@ -4800,7 +4804,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart4_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
+ .sdma_reqs = omap44xx_uart4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+ .main_clk = "uart4_fck",
+@@ -4841,6 +4844,7 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
+ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
+ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ /* usb_otg_hs master ports */
+@@ -4880,7 +4884,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .class = &omap44xx_usb_otg_hs_hwmod_class,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
+ .main_clk = "usb_otg_hs_ick",
+ .prcm = {
+ .omap4 = {
+@@ -4923,6 +4926,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+ static struct omap_hwmod omap44xx_wd_timer2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+ { .irq = 80 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+@@ -4952,7 +4956,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &omap44xx_wd_timer_hwmod_class,
+ .mpu_irqs = omap44xx_wd_timer2_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
+ .main_clk = "wd_timer2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4968,6 +4971,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ static struct omap_hwmod omap44xx_wd_timer3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
+ { .irq = 36 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+@@ -5016,7 +5020,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+ .name = "wd_timer3",
+ .class = &omap44xx_wd_timer_hwmod_class,
+ .mpu_irqs = omap44xx_wd_timer3_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
+ .main_clk = "wd_timer3_fck",
+ .prcm = {
+ .omap4 = {
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index f3a3bff..b8385e2 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -97,7 +97,7 @@ struct omap_hwmod_mux_info {
+ /**
+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ * @name: name of the IRQ channel (module local name)
+- * @irq_ch: IRQ channel ID
++ * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
+ *
+ * @name should be something short, e.g., "tx" or "rx". It is for use
+ * by platform_get_resource_byname(). It is defined locally to the
+@@ -105,7 +105,7 @@ struct omap_hwmod_mux_info {
+ */
+ struct omap_hwmod_irq_info {
+ const char *name;
+- u16 irq;
++ s16 irq;
+ };
+
+ /**
+@@ -466,7 +466,7 @@ struct omap_hwmod_class {
+ * @name: name of the hwmod
+ * @class: struct omap_hwmod_class * to the class of this hwmod
+ * @od: struct omap_device currently associated with this hwmod (internal use)
+- * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
++ * @mpu_irqs: ptr to an array of MPU IRQs
+ * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
+ * @prcm: PRCM data pertaining to this hwmod
+ * @main_clk: main clock: OMAP clock name
+@@ -480,7 +480,6 @@ struct omap_hwmod_class {
+ * @_sysc_cache: internal-use hwmod flags
+ * @_mpu_rt_va: cached register target start address (internal use)
+ * @_mpu_port_index: cached MPU register target slave ID (internal use)
+- * @mpu_irqs_cnt: number of @mpu_irqs
+ * @sdma_reqs_cnt: number of @sdma_reqs
+ * @opt_clks_cnt: number of @opt_clks
+ * @master_cnt: number of @master entries
+@@ -529,7 +528,6 @@ struct omap_hwmod {
+ u16 flags;
+ u8 _mpu_port_index;
+ u8 response_lat;
+- u8 mpu_irqs_cnt;
+ u8 sdma_reqs_cnt;
+ u8 rst_lines_cnt;
+ u8 opt_clks_cnt;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0040-omap_hwmod-share-identical-omap_hwmod_mpu_irqs-array.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0040-omap_hwmod-share-identical-omap_hwmod_mpu_irqs-array.patch
--- /dev/null
@@ -0,0 +1,1815 @@
+From 94ad621cdde526c292bbaf55f6969835b3286e81 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:07 -0600
+Subject: [PATCH 040/149] omap_hwmod: share identical omap_hwmod_mpu_irqs arrays
+
+To reduce kernel source file data duplication, share struct
+omap_hwmod_mpu_irqs arrays across OMAP2xxx and 3xxx hwmod data files.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/Makefile | 11 +-
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 167 +++-----------------
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 166 +++-----------------
+ .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 142 +++++++++++++++++
+ arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 21 +++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 162 +++----------------
+ arch/arm/mach-omap2/omap_hwmod_common_data.h | 29 ++++
+ 7 files changed, 275 insertions(+), 423 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+ create mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 8a75d17..f343365 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -145,13 +145,18 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
+ obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
+
+ # hwmod data
+-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o \
++obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
++ omap_hwmod_2xxx_3xxx_ipblock_data.o \
++ omap_hwmod_2xxx_interconnect_data.o \
+ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_2420_data.o
+-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o \
++obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
++ omap_hwmod_2xxx_3xxx_ipblock_data.o \
++ omap_hwmod_2xxx_interconnect_data.o \
+ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_2430_data.o
+-obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o \
++obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
++ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 04730d3..73157ee 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -294,10 +294,6 @@ static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+
+ /* timer1 */
+ static struct omap_hwmod omap2420_timer1_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+- { .irq = 37, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+ {
+@@ -325,7 +321,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+ /* timer1 hwmod */
+ static struct omap_hwmod omap2420_timer1_hwmod = {
+ .name = "timer1",
+- .mpu_irqs = omap2420_timer1_mpu_irqs,
++ .mpu_irqs = omap2_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -344,11 +340,6 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
+
+ /* timer2 */
+ static struct omap_hwmod omap2420_timer2_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+- { .irq = 38, },
+- { .irq = -1 }
+-};
+-
+
+ /* l4_core -> timer2 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+@@ -367,7 +358,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+ /* timer2 hwmod */
+ static struct omap_hwmod omap2420_timer2_hwmod = {
+ .name = "timer2",
+- .mpu_irqs = omap2420_timer2_mpu_irqs,
++ .mpu_irqs = omap2_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -386,10 +377,6 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
+
+ /* timer3 */
+ static struct omap_hwmod omap2420_timer3_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+- { .irq = 39, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer3 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+@@ -408,7 +395,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+ /* timer3 hwmod */
+ static struct omap_hwmod omap2420_timer3_hwmod = {
+ .name = "timer3",
+- .mpu_irqs = omap2420_timer3_mpu_irqs,
++ .mpu_irqs = omap2_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -427,10 +414,6 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
+
+ /* timer4 */
+ static struct omap_hwmod omap2420_timer4_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+- { .irq = 40, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer4 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+@@ -449,7 +432,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+ /* timer4 hwmod */
+ static struct omap_hwmod omap2420_timer4_hwmod = {
+ .name = "timer4",
+- .mpu_irqs = omap2420_timer4_mpu_irqs,
++ .mpu_irqs = omap2_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -468,10 +451,6 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
+
+ /* timer5 */
+ static struct omap_hwmod omap2420_timer5_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+- { .irq = 41, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer5 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+@@ -490,7 +469,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+ /* timer5 hwmod */
+ static struct omap_hwmod omap2420_timer5_hwmod = {
+ .name = "timer5",
+- .mpu_irqs = omap2420_timer5_mpu_irqs,
++ .mpu_irqs = omap2_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -510,10 +489,6 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
+
+ /* timer6 */
+ static struct omap_hwmod omap2420_timer6_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+- { .irq = 42, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer6 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+@@ -532,7 +507,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+ /* timer6 hwmod */
+ static struct omap_hwmod omap2420_timer6_hwmod = {
+ .name = "timer6",
+- .mpu_irqs = omap2420_timer6_mpu_irqs,
++ .mpu_irqs = omap2_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -551,10 +526,6 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
+
+ /* timer7 */
+ static struct omap_hwmod omap2420_timer7_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+- { .irq = 43, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer7 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+@@ -573,7 +544,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+ /* timer7 hwmod */
+ static struct omap_hwmod omap2420_timer7_hwmod = {
+ .name = "timer7",
+- .mpu_irqs = omap2420_timer7_mpu_irqs,
++ .mpu_irqs = omap2_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -592,10 +563,6 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
+
+ /* timer8 */
+ static struct omap_hwmod omap2420_timer8_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+- { .irq = 44, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer8 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+@@ -614,7 +581,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+ /* timer8 hwmod */
+ static struct omap_hwmod omap2420_timer8_hwmod = {
+ .name = "timer8",
+- .mpu_irqs = omap2420_timer8_mpu_irqs,
++ .mpu_irqs = omap2_timer8_mpu_irqs,
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -633,10 +600,6 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
+
+ /* timer9 */
+ static struct omap_hwmod omap2420_timer9_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+- { .irq = 45, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer9 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+@@ -655,7 +618,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+ /* timer9 hwmod */
+ static struct omap_hwmod omap2420_timer9_hwmod = {
+ .name = "timer9",
+- .mpu_irqs = omap2420_timer9_mpu_irqs,
++ .mpu_irqs = omap2_timer9_mpu_irqs,
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -674,10 +637,6 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
+
+ /* timer10 */
+ static struct omap_hwmod omap2420_timer10_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+- { .irq = 46, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+@@ -696,7 +655,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+ /* timer10 hwmod */
+ static struct omap_hwmod omap2420_timer10_hwmod = {
+ .name = "timer10",
+- .mpu_irqs = omap2420_timer10_mpu_irqs,
++ .mpu_irqs = omap2_timer10_mpu_irqs,
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -715,10 +674,6 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
+
+ /* timer11 */
+ static struct omap_hwmod omap2420_timer11_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+- { .irq = 47, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+@@ -737,7 +692,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+ /* timer11 hwmod */
+ static struct omap_hwmod omap2420_timer11_hwmod = {
+ .name = "timer11",
+- .mpu_irqs = omap2420_timer11_mpu_irqs,
++ .mpu_irqs = omap2_timer11_mpu_irqs,
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -756,10 +711,6 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
+
+ /* timer12 */
+ static struct omap_hwmod omap2420_timer12_hwmod;
+-static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+- { .irq = 48, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer12 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+@@ -778,7 +729,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+ /* timer12 hwmod */
+ static struct omap_hwmod omap2420_timer12_hwmod = {
+ .name = "timer12",
+- .mpu_irqs = omap2420_timer12_mpu_irqs,
++ .mpu_irqs = omap2xxx_timer12_mpu_irqs,
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+@@ -877,11 +828,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+- { .irq = INT_24XX_UART1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+@@ -893,7 +839,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+
+ static struct omap_hwmod omap2420_uart1_hwmod = {
+ .name = "uart1",
+- .mpu_irqs = uart1_mpu_irqs,
++ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -914,11 +860,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+- { .irq = INT_24XX_UART2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+@@ -930,7 +871,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+
+ static struct omap_hwmod omap2420_uart2_hwmod = {
+ .name = "uart2",
+- .mpu_irqs = uart2_mpu_irqs,
++ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -951,11 +892,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+- { .irq = INT_24XX_UART3_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+@@ -967,7 +903,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+
+ static struct omap_hwmod omap2420_uart3_hwmod = {
+ .name = "uart3",
+- .mpu_irqs = uart3_mpu_irqs,
++ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1085,11 +1021,6 @@ static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
+ .sysc = &omap2420_dispc_sysc,
+ };
+
+-static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
+- { .irq = 25 },
+- { .irq = -1 }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1113,7 +1044,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
+ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap2420_dispc_hwmod_class,
+- .mpu_irqs = omap2420_dispc_irqs,
++ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1252,11 +1183,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
+
+ /* I2C1 */
+
+-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+@@ -1268,7 +1194,7 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+
+ static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+- .mpu_irqs = i2c1_mpu_irqs,
++ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+@@ -1291,11 +1217,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
+
+ /* I2C2 */
+
+-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+@@ -1307,7 +1228,7 @@ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+
+ static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+- .mpu_irqs = i2c2_mpu_irqs,
++ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+@@ -1428,11 +1349,6 @@ static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+ };
+
+ /* gpio1 */
+-static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
+- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+ &omap2420_l4_wkup__gpio1,
+ };
+@@ -1440,7 +1356,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+ static struct omap_hwmod omap2420_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap242x_gpio1_irqs,
++ .mpu_irqs = omap2_gpio1_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1459,11 +1375,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
+ };
+
+ /* gpio2 */
+-static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
+- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+ &omap2420_l4_wkup__gpio2,
+ };
+@@ -1471,7 +1382,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+ static struct omap_hwmod omap2420_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap242x_gpio2_irqs,
++ .mpu_irqs = omap2_gpio2_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1490,11 +1401,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
+ };
+
+ /* gpio3 */
+-static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
+- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+ &omap2420_l4_wkup__gpio3,
+ };
+@@ -1502,7 +1408,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+ static struct omap_hwmod omap2420_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap242x_gpio3_irqs,
++ .mpu_irqs = omap2_gpio3_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1521,11 +1427,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
+ };
+
+ /* gpio4 */
+-static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
+- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+ &omap2420_l4_wkup__gpio4,
+ };
+@@ -1533,7 +1434,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+ static struct omap_hwmod omap2420_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap242x_gpio4_irqs,
++ .mpu_irqs = omap2_gpio4_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1575,14 +1476,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
+ .lch_count = 32,
+ };
+
+-static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+- { .irq = -1 }
+-};
+-
+ /* dma_system -> L3 */
+ static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
+ .master = &omap2420_dma_system_hwmod,
+@@ -1613,7 +1506,7 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
+ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2420_dma_hwmod_class,
+- .mpu_irqs = omap2420_dma_system_irqs,
++ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .slaves = omap2420_dma_system_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
+@@ -1709,11 +1602,6 @@ static struct omap_hwmod_class omap2420_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
+- { .irq = 65 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+@@ -1735,7 +1623,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+
+ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+- .mpu_irqs = omap2420_mcspi1_mpu_irqs,
++ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2420_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -1756,11 +1644,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
+- { .irq = 66 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+@@ -1778,7 +1661,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+
+ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+- .mpu_irqs = omap2420_mcspi2_mpu_irqs,
++ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2420_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 2c28468..62ecc68 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -367,10 +367,6 @@ static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+
+ /* timer1 */
+ static struct omap_hwmod omap2430_timer1_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+- { .irq = 37, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+ {
+@@ -398,7 +394,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+ /* timer1 hwmod */
+ static struct omap_hwmod omap2430_timer1_hwmod = {
+ .name = "timer1",
+- .mpu_irqs = omap2430_timer1_mpu_irqs,
++ .mpu_irqs = omap2_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -417,10 +413,6 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
+
+ /* timer2 */
+ static struct omap_hwmod omap2430_timer2_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+- { .irq = 38, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer2 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+@@ -439,7 +431,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+ /* timer2 hwmod */
+ static struct omap_hwmod omap2430_timer2_hwmod = {
+ .name = "timer2",
+- .mpu_irqs = omap2430_timer2_mpu_irqs,
++ .mpu_irqs = omap2_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -458,10 +450,6 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
+
+ /* timer3 */
+ static struct omap_hwmod omap2430_timer3_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+- { .irq = 39, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer3 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+@@ -480,7 +468,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+ /* timer3 hwmod */
+ static struct omap_hwmod omap2430_timer3_hwmod = {
+ .name = "timer3",
+- .mpu_irqs = omap2430_timer3_mpu_irqs,
++ .mpu_irqs = omap2_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -499,10 +487,6 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
+
+ /* timer4 */
+ static struct omap_hwmod omap2430_timer4_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+- { .irq = 40, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer4 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+@@ -521,7 +505,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+ /* timer4 hwmod */
+ static struct omap_hwmod omap2430_timer4_hwmod = {
+ .name = "timer4",
+- .mpu_irqs = omap2430_timer4_mpu_irqs,
++ .mpu_irqs = omap2_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -540,10 +524,6 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
+
+ /* timer5 */
+ static struct omap_hwmod omap2430_timer5_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+- { .irq = 41, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer5 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+@@ -562,7 +542,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+ /* timer5 hwmod */
+ static struct omap_hwmod omap2430_timer5_hwmod = {
+ .name = "timer5",
+- .mpu_irqs = omap2430_timer5_mpu_irqs,
++ .mpu_irqs = omap2_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -581,10 +561,6 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
+
+ /* timer6 */
+ static struct omap_hwmod omap2430_timer6_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+- { .irq = 42, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer6 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+@@ -603,7 +579,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+ /* timer6 hwmod */
+ static struct omap_hwmod omap2430_timer6_hwmod = {
+ .name = "timer6",
+- .mpu_irqs = omap2430_timer6_mpu_irqs,
++ .mpu_irqs = omap2_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -622,10 +598,6 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
+
+ /* timer7 */
+ static struct omap_hwmod omap2430_timer7_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+- { .irq = 43, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer7 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+@@ -644,7 +616,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+ /* timer7 hwmod */
+ static struct omap_hwmod omap2430_timer7_hwmod = {
+ .name = "timer7",
+- .mpu_irqs = omap2430_timer7_mpu_irqs,
++ .mpu_irqs = omap2_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -663,10 +635,6 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
+
+ /* timer8 */
+ static struct omap_hwmod omap2430_timer8_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+- { .irq = 44, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer8 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+@@ -685,7 +653,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+ /* timer8 hwmod */
+ static struct omap_hwmod omap2430_timer8_hwmod = {
+ .name = "timer8",
+- .mpu_irqs = omap2430_timer8_mpu_irqs,
++ .mpu_irqs = omap2_timer8_mpu_irqs,
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -704,10 +672,6 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
+
+ /* timer9 */
+ static struct omap_hwmod omap2430_timer9_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+- { .irq = 45, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer9 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+@@ -726,7 +690,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+ /* timer9 hwmod */
+ static struct omap_hwmod omap2430_timer9_hwmod = {
+ .name = "timer9",
+- .mpu_irqs = omap2430_timer9_mpu_irqs,
++ .mpu_irqs = omap2_timer9_mpu_irqs,
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -745,10 +709,6 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
+
+ /* timer10 */
+ static struct omap_hwmod omap2430_timer10_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+- { .irq = 46, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+@@ -767,7 +727,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+ /* timer10 hwmod */
+ static struct omap_hwmod omap2430_timer10_hwmod = {
+ .name = "timer10",
+- .mpu_irqs = omap2430_timer10_mpu_irqs,
++ .mpu_irqs = omap2_timer10_mpu_irqs,
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -786,10 +746,6 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
+
+ /* timer11 */
+ static struct omap_hwmod omap2430_timer11_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+- { .irq = 47, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+@@ -808,7 +764,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+ /* timer11 hwmod */
+ static struct omap_hwmod omap2430_timer11_hwmod = {
+ .name = "timer11",
+- .mpu_irqs = omap2430_timer11_mpu_irqs,
++ .mpu_irqs = omap2_timer11_mpu_irqs,
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -827,10 +783,6 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
+
+ /* timer12 */
+ static struct omap_hwmod omap2430_timer12_hwmod;
+-static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+- { .irq = 48, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer12 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+@@ -849,7 +801,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+ /* timer12 hwmod */
+ static struct omap_hwmod omap2430_timer12_hwmod = {
+ .name = "timer12",
+- .mpu_irqs = omap2430_timer12_mpu_irqs,
++ .mpu_irqs = omap2xxx_timer12_mpu_irqs,
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+@@ -948,11 +900,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+- { .irq = INT_24XX_UART1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+@@ -964,7 +911,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+
+ static struct omap_hwmod omap2430_uart1_hwmod = {
+ .name = "uart1",
+- .mpu_irqs = uart1_mpu_irqs,
++ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -985,11 +932,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+- { .irq = INT_24XX_UART2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+@@ -1001,7 +943,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+
+ static struct omap_hwmod omap2430_uart2_hwmod = {
+ .name = "uart2",
+- .mpu_irqs = uart2_mpu_irqs,
++ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -1022,11 +964,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+- { .irq = INT_24XX_UART3_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+@@ -1038,7 +975,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+
+ static struct omap_hwmod omap2430_uart3_hwmod = {
+ .name = "uart3",
+- .mpu_irqs = uart3_mpu_irqs,
++ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1150,11 +1087,6 @@ static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
+ .sysc = &omap2430_dispc_sysc,
+ };
+
+-static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
+- { .irq = 25 },
+- { .irq = -1 }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1172,7 +1104,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
+ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap2430_dispc_hwmod_class,
+- .mpu_irqs = omap2430_dispc_irqs,
++ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1302,11 +1234,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
+
+ /* I2C1 */
+
+-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+@@ -1318,7 +1245,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+
+ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+- .mpu_irqs = i2c1_mpu_irqs,
++ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2chs1_fck",
+@@ -1348,11 +1275,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
+
+ /* I2C2 */
+
+-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+@@ -1364,7 +1286,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+
+ static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+- .mpu_irqs = i2c2_mpu_irqs,
++ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2chs2_fck",
+@@ -1502,11 +1424,6 @@ static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+ };
+
+ /* gpio1 */
+-static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
+- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+ &omap2430_l4_wkup__gpio1,
+ };
+@@ -1514,7 +1431,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+ static struct omap_hwmod omap2430_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap243x_gpio1_irqs,
++ .mpu_irqs = omap2_gpio1_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1533,11 +1450,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
+ };
+
+ /* gpio2 */
+-static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
+- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+ &omap2430_l4_wkup__gpio2,
+ };
+@@ -1545,7 +1457,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+ static struct omap_hwmod omap2430_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap243x_gpio2_irqs,
++ .mpu_irqs = omap2_gpio2_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1564,11 +1476,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
+ };
+
+ /* gpio3 */
+-static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
+- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+ &omap2430_l4_wkup__gpio3,
+ };
+@@ -1576,7 +1483,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+ static struct omap_hwmod omap2430_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap243x_gpio3_irqs,
++ .mpu_irqs = omap2_gpio3_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1595,11 +1502,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
+ };
+
+ /* gpio4 */
+-static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
+- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+ &omap2430_l4_wkup__gpio4,
+ };
+@@ -1607,7 +1509,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+ static struct omap_hwmod omap2430_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap243x_gpio4_irqs,
++ .mpu_irqs = omap2_gpio4_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1680,14 +1582,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
+ .lch_count = 32,
+ };
+
+-static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+- { .irq = -1 }
+-};
+-
+ /* dma_system -> L3 */
+ static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+ .master = &omap2430_dma_system_hwmod,
+@@ -1718,7 +1612,7 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
+ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2430_dma_hwmod_class,
+- .mpu_irqs = omap2430_dma_system_irqs,
++ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .slaves = omap2430_dma_system_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
+@@ -1813,11 +1707,6 @@ static struct omap_hwmod_class omap2430_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
+- { .irq = 65 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+@@ -1839,7 +1728,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+
+ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+- .mpu_irqs = omap2430_mcspi1_mpu_irqs,
++ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -1860,11 +1749,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
+- { .irq = 66 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+@@ -1882,7 +1766,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+
+ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+- .mpu_irqs = omap2430_mcspi2_mpu_irqs,
++ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+new file mode 100644
+index 0000000..245294b
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+@@ -0,0 +1,142 @@
++/*
++ * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
++ *
++ * Copyright (C) 2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <plat/omap_hwmod.h>
++#include <plat/serial.h>
++
++#include <mach/irqs.h>
++
++#include "omap_hwmod_common_data.h"
++
++struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
++ { .irq = 37, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
++ { .irq = 38, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
++ { .irq = 39, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
++ { .irq = 40, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
++ { .irq = 41, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
++ { .irq = 42, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
++ { .irq = 43, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
++ { .irq = 44, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
++ { .irq = 45, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
++ { .irq = 46, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
++ { .irq = 47, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
++ { .irq = INT_24XX_UART1_IRQ, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
++ { .irq = INT_24XX_UART2_IRQ, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
++ { .irq = INT_24XX_UART3_IRQ, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
++ { .irq = 25 },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
++ { .irq = INT_24XX_I2C1_IRQ, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
++ { .irq = INT_24XX_I2C2_IRQ, },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
++ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
++ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
++ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
++ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
++ { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
++ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
++ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
++ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
++ { .irq = 65 },
++ { .irq = -1 }
++};
++
++struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
++ { .irq = 66 },
++ { .irq = -1 }
++};
++
++
++
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+new file mode 100644
+index 0000000..5a078a6
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+@@ -0,0 +1,21 @@
++/*
++ * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
++ *
++ * Copyright (C) 2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <plat/omap_hwmod.h>
++#include <plat/serial.h>
++
++#include <mach/irqs.h>
++
++#include "omap_hwmod_common_data.h"
++
++struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
++ { .irq = 48, },
++ { .irq = -1 }
++};
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index cc178b5..6bac4bb 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -151,7 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
+ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &l3_hwmod_class,
+- .mpu_irqs = omap3xxx_l3_main_irqs,
++ .mpu_irqs = omap3xxx_l3_main_irqs,
+ .masters = omap3xxx_l3_main_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
+ .slaves = omap3xxx_l3_main_slaves,
+@@ -572,10 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+
+ /* timer1 */
+ static struct omap_hwmod omap3xxx_timer1_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+- { .irq = 37, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+ {
+@@ -603,7 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+ /* timer1 hwmod */
+ static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ .name = "timer1",
+- .mpu_irqs = omap3xxx_timer1_mpu_irqs,
++ .mpu_irqs = omap2_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -622,10 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
+
+ /* timer2 */
+ static struct omap_hwmod omap3xxx_timer2_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+- { .irq = 38, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+ {
+@@ -653,7 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+ /* timer2 hwmod */
+ static struct omap_hwmod omap3xxx_timer2_hwmod = {
+ .name = "timer2",
+- .mpu_irqs = omap3xxx_timer2_mpu_irqs,
++ .mpu_irqs = omap2_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -672,10 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
+
+ /* timer3 */
+ static struct omap_hwmod omap3xxx_timer3_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+- { .irq = 39, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+ {
+@@ -703,7 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+ /* timer3 hwmod */
+ static struct omap_hwmod omap3xxx_timer3_hwmod = {
+ .name = "timer3",
+- .mpu_irqs = omap3xxx_timer3_mpu_irqs,
++ .mpu_irqs = omap2_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -722,10 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
+
+ /* timer4 */
+ static struct omap_hwmod omap3xxx_timer4_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+- { .irq = 40, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+ {
+@@ -753,7 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+ /* timer4 hwmod */
+ static struct omap_hwmod omap3xxx_timer4_hwmod = {
+ .name = "timer4",
+- .mpu_irqs = omap3xxx_timer4_mpu_irqs,
++ .mpu_irqs = omap2_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -772,10 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
+
+ /* timer5 */
+ static struct omap_hwmod omap3xxx_timer5_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+- { .irq = 41, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+ {
+@@ -803,7 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+ /* timer5 hwmod */
+ static struct omap_hwmod omap3xxx_timer5_hwmod = {
+ .name = "timer5",
+- .mpu_irqs = omap3xxx_timer5_mpu_irqs,
++ .mpu_irqs = omap2_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -822,10 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
+
+ /* timer6 */
+ static struct omap_hwmod omap3xxx_timer6_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+- { .irq = 42, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+ {
+@@ -853,7 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+ /* timer6 hwmod */
+ static struct omap_hwmod omap3xxx_timer6_hwmod = {
+ .name = "timer6",
+- .mpu_irqs = omap3xxx_timer6_mpu_irqs,
++ .mpu_irqs = omap2_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+@@ -872,10 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
+
+ /* timer7 */
+ static struct omap_hwmod omap3xxx_timer7_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+- { .irq = 43, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+ {
+@@ -903,7 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+ /* timer7 hwmod */
+ static struct omap_hwmod omap3xxx_timer7_hwmod = {
+ .name = "timer7",
+- .mpu_irqs = omap3xxx_timer7_mpu_irqs,
++ .mpu_irqs = omap2_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+@@ -922,10 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
+
+ /* timer8 */
+ static struct omap_hwmod omap3xxx_timer8_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+- { .irq = 44, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+ {
+@@ -953,7 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+ /* timer8 hwmod */
+ static struct omap_hwmod omap3xxx_timer8_hwmod = {
+ .name = "timer8",
+- .mpu_irqs = omap3xxx_timer8_mpu_irqs,
++ .mpu_irqs = omap2_timer8_mpu_irqs,
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+@@ -972,10 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
+
+ /* timer9 */
+ static struct omap_hwmod omap3xxx_timer9_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+- { .irq = 45, },
+- { .irq = -1 }
+-};
+
+ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+ {
+@@ -1003,7 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+ /* timer9 hwmod */
+ static struct omap_hwmod omap3xxx_timer9_hwmod = {
+ .name = "timer9",
+- .mpu_irqs = omap3xxx_timer9_mpu_irqs,
++ .mpu_irqs = omap2_timer9_mpu_irqs,
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1022,10 +986,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
+
+ /* timer10 */
+ static struct omap_hwmod omap3xxx_timer10_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+- { .irq = 46, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer10 */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+@@ -1044,7 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+ /* timer10 hwmod */
+ static struct omap_hwmod omap3xxx_timer10_hwmod = {
+ .name = "timer10",
+- .mpu_irqs = omap3xxx_timer10_mpu_irqs,
++ .mpu_irqs = omap2_timer10_mpu_irqs,
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1063,10 +1023,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
+
+ /* timer11 */
+ static struct omap_hwmod omap3xxx_timer11_hwmod;
+-static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+- { .irq = 47, },
+- { .irq = -1 }
+-};
+
+ /* l4_core -> timer11 */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+@@ -1085,7 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+ /* timer11 hwmod */
+ static struct omap_hwmod omap3xxx_timer11_hwmod = {
+ .name = "timer11",
+- .mpu_irqs = omap3xxx_timer11_mpu_irqs,
++ .mpu_irqs = omap2_timer11_mpu_irqs,
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1254,11 +1210,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+- { .irq = INT_24XX_UART1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+@@ -1270,7 +1221,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ .name = "uart1",
+- .mpu_irqs = uart1_mpu_irqs,
++ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+@@ -1291,11 +1242,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+- { .irq = INT_24XX_UART2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+@@ -1307,7 +1253,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ .name = "uart2",
+- .mpu_irqs = uart2_mpu_irqs,
++ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+@@ -1328,11 +1274,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+- { .irq = INT_24XX_UART3_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+@@ -1344,7 +1285,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ .name = "uart3",
+- .mpu_irqs = uart3_mpu_irqs,
++ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+@@ -1555,11 +1496,6 @@ static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
+ .sysc = &omap3xxx_dispc_sysc,
+ };
+
+-static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
+- { .irq = 25 },
+- { .irq = -1 }
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+ .master = &omap3xxx_l4_core_hwmod,
+@@ -1584,7 +1520,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
+ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap3xxx_dispc_hwmod_class,
+- .mpu_irqs = omap3xxx_dispc_irqs,
++ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1781,11 +1717,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ };
+
+-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C1_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+@@ -1797,7 +1728,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+- .mpu_irqs = i2c1_mpu_irqs,
++ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+@@ -1823,11 +1754,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ };
+
+-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+- { .irq = INT_24XX_I2C2_IRQ, },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+@@ -1839,7 +1765,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+- .mpu_irqs = i2c2_mpu_irqs,
++ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+@@ -2032,11 +1958,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
+ };
+
+ /* gpio1 */
+-static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
+- { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbck", },
+ };
+@@ -2048,7 +1969,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
+ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap3xxx_gpio1_irqs,
++ .mpu_irqs = omap2_gpio1_irqs,
+ .main_clk = "gpio1_ick",
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+@@ -2069,11 +1990,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ };
+
+ /* gpio2 */
+-static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
+- { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbck", },
+ };
+@@ -2085,7 +2001,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
+ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap3xxx_gpio2_irqs,
++ .mpu_irqs = omap2_gpio2_irqs,
+ .main_clk = "gpio2_ick",
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+@@ -2106,11 +2022,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ };
+
+ /* gpio3 */
+-static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
+- { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbck", },
+ };
+@@ -2122,7 +2033,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
+ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap3xxx_gpio3_irqs,
++ .mpu_irqs = omap2_gpio3_irqs,
+ .main_clk = "gpio3_ick",
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+@@ -2143,11 +2054,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ };
+
+ /* gpio4 */
+-static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
+- { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbck", },
+ };
+@@ -2159,7 +2065,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
+ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+- .mpu_irqs = omap3xxx_gpio4_irqs,
++ .mpu_irqs = omap2_gpio4_irqs,
+ .main_clk = "gpio4_ick",
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+@@ -2287,14 +2193,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
+ };
+
+ /* dma_system */
+-static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
+- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x48056000,
+@@ -2326,7 +2224,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
+ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap3xxx_dma_hwmod_class,
+- .mpu_irqs = omap3xxx_dma_system_irqs,
++ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ick",
+ .prcm = {
+ .omap2 = {
+@@ -3044,11 +2942,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
+- { .name = "irq", .irq = 65 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 35 },
+ { .name = "rx0", .dma_req = 36 },
+@@ -3070,7 +2963,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+
+ static struct omap_hwmod omap34xx_mcspi1 = {
+ .name = "mcspi1",
+- .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
++ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+@@ -3091,11 +2984,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
+- { .name = "irq", .irq = 66 },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 43 },
+ { .name = "rx0", .dma_req = 44 },
+@@ -3113,7 +3001,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+
+ static struct omap_hwmod omap34xx_mcspi2 = {
+ .name = "mcspi2",
+- .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
++ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+index 76a2f11..1ac878c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
++++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+@@ -49,6 +49,35 @@ extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
+ extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
+ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+
++/* Common IP block data across OMAP2xxx */
++extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
++
++/* Common IP block data across OMAP2/3 */
++extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
++extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
++extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
++extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
++extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
++extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
++extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
++extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
++
+ /* OMAP hwmod classes - forward declarations */
+ extern struct omap_hwmod_class l3_hwmod_class;
+ extern struct omap_hwmod_class l4_hwmod_class;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0041-omap_hwmod-use-a-terminator-record-with-omap_hwmod_d.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0041-omap_hwmod-use-a-terminator-record-with-omap_hwmod_d.patch
--- /dev/null
@@ -0,0 +1,1382 @@
+From f36679901eb8aa0201796d70e261da9a0aff25e1 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:07 -0600
+Subject: [PATCH 041/149] omap_hwmod: use a terminator record with omap_hwmod_dma_info arrays
+
+Previously, struct omap_hwmod_dma_info arrays were unterminated; and
+users of these arrays used the ARRAY_SIZE() macro to determine the
+length of the array. However, ARRAY_SIZE() only works when the array
+is in the same scope as the macro user.
+
+So far this hasn't been a problem. However, to reduce duplicated
+data, a subsequent patch will move common data to a separate, shared
+file. When this is done, ARRAY_SIZE() will no longer be usable.
+
+This patch removes ARRAY_SIZE() usage for struct omap_hwmod_dma_info
+arrays and uses a sentinel value (irq == -1) as the array terminator
+instead.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 30 ++++++++++++-
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 20 ++++----
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 32 +++++++-------
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 43 +++++++++----------
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 60 +++++++++++++-------------
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 8 +--
+ 6 files changed, 106 insertions(+), 87 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index b761968..7d242c9 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -702,6 +702,29 @@ static int _count_mpu_irqs(struct omap_hwmod *oh)
+ }
+
+ /**
++ * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
++ * @oh: struct omap_hwmod *oh
++ *
++ * Count and return the number of SDMA request lines associated with
++ * the hwmod @oh. Used to allocate struct resource data. Returns 0
++ * if @oh is NULL.
++ */
++static int _count_sdma_reqs(struct omap_hwmod *oh)
++{
++ struct omap_hwmod_dma_info *ohdi;
++ int i = 0;
++
++ if (!oh || !oh->sdma_reqs)
++ return 0;
++
++ do {
++ ohdi = &oh->sdma_reqs[i++];
++ } while (ohdi->dma_req != -1);
++
++ return i;
++}
++
++/**
+ * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
+ * @oh: struct omap_hwmod *oh
+ *
+@@ -2007,7 +2030,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ {
+ int ret, i;
+
+- ret = _count_mpu_irqs(oh) + oh->sdma_reqs_cnt;
++ ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
+
+ for (i = 0; i < oh->slaves_cnt; i++)
+ ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+@@ -2027,7 +2050,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ */
+ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+ {
+- int i, j, mpu_irqs_cnt;
++ int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+ int r = 0;
+
+ /* For each IRQ, DMA, memory area, fill in array.*/
+@@ -2041,7 +2064,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+ r++;
+ }
+
+- for (i = 0; i < oh->sdma_reqs_cnt; i++) {
++ sdma_reqs_cnt = _count_sdma_reqs(oh);
++ for (i = 0; i < sdma_reqs_cnt; i++) {
+ (res + r)->name = (oh->sdma_reqs + i)->name;
+ (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+ (res + r)->end = (oh->sdma_reqs + i)->dma_req;
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 73157ee..60c817e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -831,6 +831,7 @@ static struct omap_hwmod_class uart_class = {
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+@@ -841,7 +842,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -863,6 +863,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+@@ -873,7 +874,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -895,6 +895,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+@@ -905,7 +906,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -942,6 +942,7 @@ static struct omap_hwmod_class omap2420_dss_hwmod_class = {
+
+ static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
++ { .dma_req = -1 }
+ };
+
+ /* dss */
+@@ -980,7 +981,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
+ .class = &omap2420_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+ .sdma_reqs = omap2420_dss_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1186,6 +1186,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+@@ -1196,7 +1197,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1220,6 +1220,7 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+@@ -1230,7 +1231,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1611,6 +1611,7 @@ static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+@@ -1625,7 +1626,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2420_mcspi1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1649,6 +1649,7 @@ static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
+@@ -1663,7 +1664,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2420_mcspi2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1700,6 +1700,7 @@ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+ static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+ { .name = "rx", .dma_req = 32 },
+ { .name = "tx", .dma_req = 31 },
++ { .dma_req = -1 }
+ };
+
+ /* l4_core -> mcbsp1 */
+@@ -1721,7 +1722,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp1_irqs,
+ .sdma_reqs = omap2420_mcbsp1_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1747,6 +1747,7 @@ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+ static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+ { .name = "rx", .dma_req = 34 },
+ { .name = "tx", .dma_req = 33 },
++ { .dma_req = -1 }
+ };
+
+ /* l4_core -> mcbsp2 */
+@@ -1768,7 +1769,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp2_irqs,
+ .sdma_reqs = omap2420_mcbsp2_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 62ecc68..af758b3 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -903,6 +903,7 @@ static struct omap_hwmod_class uart_class = {
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+@@ -913,7 +914,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -935,6 +935,7 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+@@ -945,7 +946,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -967,6 +967,7 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+@@ -977,7 +978,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1014,6 +1014,7 @@ static struct omap_hwmod_class omap2430_dss_hwmod_class = {
+
+ static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
++ { .dma_req = -1 }
+ };
+
+ /* dss */
+@@ -1046,7 +1047,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
+ .class = &omap2430_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+ .sdma_reqs = omap2430_dss_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1237,6 +1237,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+@@ -1247,7 +1248,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2chs1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1278,6 +1278,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+@@ -1288,7 +1289,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2chs2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1716,6 +1716,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+@@ -1730,7 +1731,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1754,6 +1754,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
+@@ -1768,7 +1769,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1797,6 +1797,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
+ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
+ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
+@@ -1811,7 +1812,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
+ .name = "mcspi3_hwmod",
+ .mpu_irqs = omap2430_mcspi3_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1915,6 +1915,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+ { .name = "rx", .dma_req = 32 },
+ { .name = "tx", .dma_req = 31 },
++ { .dma_req = -1 }
+ };
+
+ /* l4_core -> mcbsp1 */
+@@ -1936,7 +1937,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp1_irqs,
+ .sdma_reqs = omap2430_mcbsp1_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1963,6 +1963,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+ { .name = "rx", .dma_req = 34 },
+ { .name = "tx", .dma_req = 33 },
++ { .dma_req = -1 }
+ };
+
+ /* l4_core -> mcbsp2 */
+@@ -1984,7 +1985,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp2_irqs,
+ .sdma_reqs = omap2430_mcbsp2_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2011,6 +2011,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+ { .name = "rx", .dma_req = 18 },
+ { .name = "tx", .dma_req = 17 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+@@ -2042,7 +2043,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp3_irqs,
+ .sdma_reqs = omap2430_mcbsp3_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2069,6 +2069,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+ { .name = "rx", .dma_req = 20 },
+ { .name = "tx", .dma_req = 19 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+@@ -2100,7 +2101,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp4_irqs,
+ .sdma_reqs = omap2430_mcbsp4_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
+ .main_clk = "mcbsp4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2127,6 +2127,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+ { .name = "rx", .dma_req = 22 },
+ { .name = "tx", .dma_req = 21 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+@@ -2158,7 +2159,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp5_irqs,
+ .sdma_reqs = omap2430_mcbsp5_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
+ .main_clk = "mcbsp5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2202,6 +2202,7 @@ static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
+ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
+@@ -2221,7 +2222,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc1_mpu_irqs,
+ .sdma_reqs = omap2430_mmc1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
+ .opt_clks = omap2430_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
+@@ -2251,6 +2251,7 @@ static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
+ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
+@@ -2266,7 +2267,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc2_mpu_irqs,
+ .sdma_reqs = omap2430_mmc2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
+ .opt_clks = omap2430_mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
+ .main_clk = "mmchs2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 6bac4bb..265f0b1 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1213,6 +1213,7 @@ static struct omap_hwmod_class uart_class = {
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+@@ -1223,7 +1224,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = uart1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1245,6 +1245,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+@@ -1255,7 +1256,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = uart2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1277,6 +1277,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+@@ -1287,7 +1288,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = uart3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1314,6 +1314,7 @@ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+ { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+@@ -1324,7 +1325,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ .name = "uart4",
+ .mpu_irqs = uart4_mpu_irqs,
+ .sdma_reqs = uart4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
+ .main_clk = "uart4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1367,6 +1367,7 @@ static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
+ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
+ { .name = "dsi1", .dma_req = 74 },
++ { .dma_req = -1 }
+ };
+
+ /* dss */
+@@ -1426,8 +1427,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+ .class = &omap3xxx_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+-
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1452,8 +1451,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+ .class = &omap3xxx_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+-
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1720,6 +1717,7 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+@@ -1730,7 +1728,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1757,6 +1754,7 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+@@ -1767,7 +1765,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1799,6 +1796,7 @@ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+ { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+@@ -1809,7 +1807,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+ .name = "i2c3",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2275,6 +2272,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
+ { .name = "rx", .dma_req = 32 },
+ { .name = "tx", .dma_req = 31 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+@@ -2306,7 +2304,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp1_irqs,
+ .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2333,6 +2330,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
+ { .name = "rx", .dma_req = 34 },
+ { .name = "tx", .dma_req = 33 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+@@ -2369,7 +2367,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_irqs,
+ .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2397,6 +2394,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
+ { .name = "rx", .dma_req = 18 },
+ { .name = "tx", .dma_req = 17 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+@@ -2432,7 +2430,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_irqs,
+ .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2460,6 +2457,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
+ { .name = "rx", .dma_req = 20 },
+ { .name = "tx", .dma_req = 19 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+@@ -2491,7 +2489,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp4_irqs,
+ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
+ .main_clk = "mcbsp4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2518,6 +2515,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
+ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
+ { .name = "rx", .dma_req = 22 },
+ { .name = "tx", .dma_req = 21 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+@@ -2549,7 +2547,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp5_irqs,
+ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
+ .main_clk = "mcbsp5_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2951,6 +2948,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+ { .name = "rx2", .dma_req = 40 },
+ { .name = "tx3", .dma_req = 41 },
+ { .name = "rx3", .dma_req = 42 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
+@@ -2965,7 +2963,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
+ .name = "mcspi1",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2989,6 +2986,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 44 },
+ { .name = "tx1", .dma_req = 45 },
+ { .name = "rx1", .dma_req = 46 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
+@@ -3003,7 +3001,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
+ .name = "mcspi2",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -3032,6 +3029,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 16 },
+ { .name = "tx1", .dma_req = 23 },
+ { .name = "rx1", .dma_req = 24 },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
+@@ -3046,7 +3044,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
+ .name = "mcspi3",
+ .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -3073,6 +3070,7 @@ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
+ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
+@@ -3087,7 +3085,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
+ .name = "mcspi4",
+ .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
+ .main_clk = "mcspi4_fck",
+ .prcm = {
+ .omap2 = {
+@@ -3218,6 +3215,7 @@ static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 61, },
+ { .name = "rx", .dma_req = 62, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
+@@ -3236,7 +3234,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
+ .opt_clks = omap34xx_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
+@@ -3266,6 +3263,7 @@ static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 47, },
+ { .name = "rx", .dma_req = 48, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
+@@ -3280,7 +3278,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+ .name = "mmc2",
+ .mpu_irqs = omap34xx_mmc2_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
+ .opt_clks = omap34xx_mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+ .main_clk = "mmchs2_fck",
+@@ -3309,6 +3306,7 @@ static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
+ static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 77, },
+ { .name = "rx", .dma_req = 78, },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
+@@ -3323,7 +3321,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
+ .name = "mmc3",
+ .mpu_irqs = omap34xx_mmc3_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
+ .opt_clks = omap34xx_mmc3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
+ .main_clk = "mmchs3_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index f7ff937..316e922 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -685,6 +685,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
+ { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
+ { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
+ { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ /* aess master ports */
+@@ -739,7 +740,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .class = &omap44xx_aess_hwmod_class,
+ .mpu_irqs = omap44xx_aess_irqs,
+ .sdma_reqs = omap44xx_aess_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
+ .main_clk = "aess_fck",
+ .prcm = {
+ .omap4 = {
+@@ -954,6 +954,7 @@ static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
+
+ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
+ { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+@@ -1003,7 +1004,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .class = &omap44xx_dmic_hwmod_class,
+ .mpu_irqs = omap44xx_dmic_irqs,
+ .sdma_reqs = omap44xx_dmic_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
+ .main_clk = "dmic_fck",
+ .prcm = {
+ .omap4 = {
+@@ -1221,6 +1221,7 @@ static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+ { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+@@ -1270,7 +1271,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .class = &omap44xx_dispc_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -1312,6 +1312,7 @@ static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
+ { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+@@ -1361,7 +1362,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi1_irqs,
+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -1382,6 +1382,7 @@ static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+
+ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
+ { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+@@ -1431,7 +1432,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -1472,6 +1472,7 @@ static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
+
+ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
+ { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+@@ -1521,7 +1522,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .class = &omap44xx_hdmi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_hdmi_irqs,
+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -1557,6 +1557,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
+ static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+ static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
+ { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+@@ -1605,7 +1606,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap44xx_rfbi_hwmod_class,
+ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2138,6 +2138,7 @@ static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+@@ -2169,7 +2170,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2191,6 +2191,7 @@ static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+@@ -2222,7 +2223,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2244,6 +2244,7 @@ static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+@@ -2275,7 +2276,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+ .main_clk = "i2c3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2297,6 +2297,7 @@ static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+@@ -2328,7 +2329,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+ .main_clk = "i2c4_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2467,6 +2467,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
+ { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
+ { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
+ { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ /* iss master ports */
+@@ -2506,7 +2507,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .class = &omap44xx_iss_hwmod_class,
+ .mpu_irqs = omap44xx_iss_irqs,
+ .sdma_reqs = omap44xx_iss_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
+ .main_clk = "iss_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2791,6 +2791,7 @@ static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+@@ -2842,7 +2843,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp1_irqs,
+ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2864,6 +2864,7 @@ static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+@@ -2915,7 +2916,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp2_irqs,
+ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -2937,6 +2937,7 @@ static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+@@ -2988,7 +2989,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp3_irqs,
+ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3010,6 +3010,7 @@ static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+@@ -3040,7 +3041,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .mpu_irqs = omap44xx_mcbsp4_irqs,
+ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
+ .main_clk = "mcbsp4_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3083,6 +3083,7 @@ static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
+ { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
+ { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+@@ -3132,7 +3133,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .class = &omap44xx_mcpdm_hwmod_class,
+ .mpu_irqs = omap44xx_mcpdm_irqs,
+ .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
+ .main_clk = "mcpdm_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3182,6 +3182,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+ { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+@@ -3217,7 +3218,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi1_irqs,
+ .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3242,6 +3242,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+@@ -3277,7 +3278,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi2_irqs,
+ .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3302,6 +3302,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+ { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+@@ -3337,7 +3338,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi3_irqs,
+ .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3360,6 +3360,7 @@ static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+@@ -3395,7 +3396,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi4_irqs,
+ .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+ .main_clk = "mcspi4_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3440,6 +3440,7 @@ static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ /* mmc1 master ports */
+@@ -3480,7 +3481,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc1_irqs,
+ .sdma_reqs = omap44xx_mmc1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
+ .main_clk = "mmc1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3504,6 +3504,7 @@ static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ /* mmc2 master ports */
+@@ -3539,7 +3540,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc2_irqs,
+ .sdma_reqs = omap44xx_mmc2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3563,6 +3563,7 @@ static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+@@ -3593,7 +3594,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc3_irqs,
+ .sdma_reqs = omap44xx_mmc3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
+ .main_clk = "mmc3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3615,6 +3615,7 @@ static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+@@ -3646,7 +3647,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .mpu_irqs = omap44xx_mmc4_irqs,
+
+ .sdma_reqs = omap44xx_mmc4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
+ .main_clk = "mmc4_fck",
+ .prcm = {
+ .omap4 = {
+@@ -3668,6 +3668,7 @@ static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+@@ -3698,7 +3699,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .class = &omap44xx_mmc_hwmod_class,
+ .mpu_irqs = omap44xx_mmc5_irqs,
+ .sdma_reqs = omap44xx_mmc5_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
+ .main_clk = "mmc5_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4618,6 +4618,7 @@ static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+@@ -4648,7 +4649,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart1_irqs,
+ .sdma_reqs = omap44xx_uart1_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4670,6 +4670,7 @@ static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+@@ -4700,7 +4701,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart2_irqs,
+ .sdma_reqs = omap44xx_uart2_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4722,6 +4722,7 @@ static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+@@ -4753,7 +4754,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .mpu_irqs = omap44xx_uart3_irqs,
+ .sdma_reqs = omap44xx_uart3_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap4 = {
+@@ -4775,6 +4775,7 @@ static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
++ { .dma_req = -1 }
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+@@ -4805,7 +4806,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .class = &omap44xx_uart_hwmod_class,
+ .mpu_irqs = omap44xx_uart4_irqs,
+ .sdma_reqs = omap44xx_uart4_sdma_reqs,
+- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+ .main_clk = "uart4_fck",
+ .prcm = {
+ .omap4 = {
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index b8385e2..ce06ac6 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -111,7 +111,7 @@ struct omap_hwmod_irq_info {
+ /**
+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
+ * @name: name of the DMA channel (module local name)
+- * @dma_req: DMA request ID
++ * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
+ *
+ * @name should be something short, e.g., "tx" or "rx". It is for use
+ * by platform_get_resource_byname(). It is defined locally to the
+@@ -119,7 +119,7 @@ struct omap_hwmod_irq_info {
+ */
+ struct omap_hwmod_dma_info {
+ const char *name;
+- u16 dma_req;
++ s16 dma_req;
+ };
+
+ /**
+@@ -467,7 +467,7 @@ struct omap_hwmod_class {
+ * @class: struct omap_hwmod_class * to the class of this hwmod
+ * @od: struct omap_device currently associated with this hwmod (internal use)
+ * @mpu_irqs: ptr to an array of MPU IRQs
+- * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
++ * @sdma_reqs: ptr to an array of System DMA request IDs
+ * @prcm: PRCM data pertaining to this hwmod
+ * @main_clk: main clock: OMAP clock name
+ * @_clk: pointer to the main struct clk (filled in at runtime)
+@@ -480,7 +480,6 @@ struct omap_hwmod_class {
+ * @_sysc_cache: internal-use hwmod flags
+ * @_mpu_rt_va: cached register target start address (internal use)
+ * @_mpu_port_index: cached MPU register target slave ID (internal use)
+- * @sdma_reqs_cnt: number of @sdma_reqs
+ * @opt_clks_cnt: number of @opt_clks
+ * @master_cnt: number of @master entries
+ * @slaves_cnt: number of @slave entries
+@@ -528,7 +527,6 @@ struct omap_hwmod {
+ u16 flags;
+ u8 _mpu_port_index;
+ u8 response_lat;
+- u8 sdma_reqs_cnt;
+ u8 rst_lines_cnt;
+ u8 opt_clks_cnt;
+ u8 masters_cnt;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0042-omap_hwmod-share-identical-omap_hwmod_dma_info-array.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0042-omap_hwmod-share-identical-omap_hwmod_dma_info-array.patch
--- /dev/null
@@ -0,0 +1,935 @@
+From 5d6b95653e3acd8d5f1d45b3668c29331a74c19e Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:07 -0600
+Subject: [PATCH 042/149] omap_hwmod: share identical omap_hwmod_dma_info arrays
+
+To reduce kernel source file data duplication, share struct
+omap_hwmod_dma_info arrays across OMAP2xxx and 3xxx hwmod data files.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 87 ++----------------
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 95 +++-----------------
+ .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 92 +++++++++++++++++++
+ arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 6 ++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 89 ++----------------
+ arch/arm/mach-omap2/omap_hwmod_common_data.c | 20 ----
+ arch/arm/mach-omap2/omap_hwmod_common_data.h | 15 +++
+ 7 files changed, 144 insertions(+), 260 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 60c817e..6acc01f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -828,12 +828,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+ &omap2_l4_core__uart1,
+ };
+@@ -841,7 +835,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+ static struct omap_hwmod omap2420_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+- .sdma_reqs = uart1_sdma_reqs,
++ .sdma_reqs = omap2_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -860,12 +854,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+ &omap2_l4_core__uart2,
+ };
+@@ -873,7 +861,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+ static struct omap_hwmod omap2420_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+- .sdma_reqs = uart2_sdma_reqs,
++ .sdma_reqs = omap2_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -892,12 +880,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+ &omap2_l4_core__uart3,
+ };
+@@ -905,7 +887,7 @@ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+ static struct omap_hwmod omap2420_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+- .sdma_reqs = uart3_sdma_reqs,
++ .sdma_reqs = omap2_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -940,11 +922,6 @@ static struct omap_hwmod_class omap2420_dss_hwmod_class = {
+ .sysc = &omap2420_dss_sysc,
+ };
+
+-static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
+- { .name = "dispc", .dma_req = 5 },
+- { .dma_req = -1 }
+-};
+-
+ /* dss */
+ /* dss master ports */
+ static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
+@@ -980,7 +957,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
+ .name = "dss_core",
+ .class = &omap2420_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+- .sdma_reqs = omap2420_dss_sdma_chs,
++ .sdma_reqs = omap2xxx_dss_sdma_chs,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1183,12 +1160,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
+
+ /* I2C1 */
+
+-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+ &omap2420_l4_core__i2c1,
+ };
+@@ -1196,7 +1167,7 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+ static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+- .sdma_reqs = i2c1_sdma_reqs,
++ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1217,12 +1188,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
+
+ /* I2C2 */
+
+-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+ &omap2420_l4_core__i2c2,
+ };
+@@ -1230,7 +1195,7 @@ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+ static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+- .sdma_reqs = i2c2_sdma_reqs,
++ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1602,18 +1567,6 @@ static struct omap_hwmod_class omap2420_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+- { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+- { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+- { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+- { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+- { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+- { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+- { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+ &omap2420_l4_core__mcspi1,
+ };
+@@ -1625,7 +1578,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+- .sdma_reqs = omap2420_mcspi1_sdma_reqs,
++ .sdma_reqs = omap2_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1644,14 +1597,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+- { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+- { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+- { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
+ &omap2420_l4_core__mcspi2,
+ };
+@@ -1663,7 +1608,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+- .sdma_reqs = omap2420_mcspi2_sdma_reqs,
++ .sdma_reqs = omap2_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1697,12 +1642,6 @@ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+- { .name = "rx", .dma_req = 32 },
+- { .name = "tx", .dma_req = 31 },
+- { .dma_req = -1 }
+-};
+-
+ /* l4_core -> mcbsp1 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1721,7 +1660,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp1_irqs,
+- .sdma_reqs = omap2420_mcbsp1_sdma_chs,
++ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1744,12 +1683,6 @@ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+- { .name = "rx", .dma_req = 34 },
+- { .name = "tx", .dma_req = 33 },
+- { .dma_req = -1 }
+-};
+-
+ /* l4_core -> mcbsp2 */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1768,7 +1701,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp2_irqs,
+- .sdma_reqs = omap2420_mcbsp2_sdma_chs,
++ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index af758b3..639acd5 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -900,12 +900,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+ &omap2_l4_core__uart1,
+ };
+@@ -913,7 +907,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+ static struct omap_hwmod omap2430_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+- .sdma_reqs = uart1_sdma_reqs,
++ .sdma_reqs = omap2_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -932,12 +926,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+ &omap2_l4_core__uart2,
+ };
+@@ -945,7 +933,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+ static struct omap_hwmod omap2430_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+- .sdma_reqs = uart2_sdma_reqs,
++ .sdma_reqs = omap2_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -964,12 +952,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+ &omap2_l4_core__uart3,
+ };
+@@ -977,7 +959,7 @@ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+ static struct omap_hwmod omap2430_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+- .sdma_reqs = uart3_sdma_reqs,
++ .sdma_reqs = omap2_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1012,11 +994,6 @@ static struct omap_hwmod_class omap2430_dss_hwmod_class = {
+ .sysc = &omap2430_dss_sysc,
+ };
+
+-static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
+- { .name = "dispc", .dma_req = 5 },
+- { .dma_req = -1 }
+-};
+-
+ /* dss */
+ /* dss master ports */
+ static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
+@@ -1046,7 +1023,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
+ .name = "dss_core",
+ .class = &omap2430_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+- .sdma_reqs = omap2430_dss_sdma_chs,
++ .sdma_reqs = omap2xxx_dss_sdma_chs,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -1234,12 +1211,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
+
+ /* I2C1 */
+
+-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+ &omap2430_l4_core__i2c1,
+ };
+@@ -1247,7 +1218,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+- .sdma_reqs = i2c1_sdma_reqs,
++ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2chs1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1275,12 +1246,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
+
+ /* I2C2 */
+
+-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+ &omap2430_l4_core__i2c2,
+ };
+@@ -1288,7 +1253,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+ static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+- .sdma_reqs = i2c2_sdma_reqs,
++ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2chs2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1707,18 +1672,6 @@ static struct omap_hwmod_class omap2430_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+- { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+- { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+- { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+- { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+- { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+- { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+- { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+ &omap2430_l4_core__mcspi1,
+ };
+@@ -1730,7 +1683,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ .name = "mcspi1_hwmod",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+- .sdma_reqs = omap2430_mcspi1_sdma_reqs,
++ .sdma_reqs = omap2_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1749,14 +1702,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+- { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+- { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+- { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
+ &omap2430_l4_core__mcspi2,
+ };
+@@ -1768,7 +1713,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ .name = "mcspi2_hwmod",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+- .sdma_reqs = omap2430_mcspi2_sdma_reqs,
++ .sdma_reqs = omap2_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1912,12 +1857,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+- { .name = "rx", .dma_req = 32 },
+- { .name = "tx", .dma_req = 31 },
+- { .dma_req = -1 }
+-};
+-
+ /* l4_core -> mcbsp1 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1936,7 +1875,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp1_irqs,
+- .sdma_reqs = omap2430_mcbsp1_sdma_chs,
++ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1960,12 +1899,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+- { .name = "rx", .dma_req = 34 },
+- { .name = "tx", .dma_req = 33 },
+- { .dma_req = -1 }
+-};
+-
+ /* l4_core -> mcbsp2 */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1984,7 +1917,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp2_irqs,
+- .sdma_reqs = omap2430_mcbsp2_sdma_chs,
++ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2008,12 +1941,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+- { .name = "rx", .dma_req = 18 },
+- { .name = "tx", .dma_req = 17 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+ {
+ .name = "mpu",
+@@ -2042,7 +1969,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp3_irqs,
+- .sdma_reqs = omap2430_mcbsp3_sdma_chs,
++ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+index 245294b..7c4f5ab 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+@@ -10,11 +10,35 @@
+ */
+ #include <plat/omap_hwmod.h>
+ #include <plat/serial.h>
++#include <plat/dma.h>
+
+ #include <mach/irqs.h>
+
+ #include "omap_hwmod_common_data.h"
+
++
++/*
++ * omap_hwmod class data
++ */
++
++struct omap_hwmod_class l3_hwmod_class = {
++ .name = "l3"
++};
++
++struct omap_hwmod_class l4_hwmod_class = {
++ .name = "l4"
++};
++
++struct omap_hwmod_class mpu_hwmod_class = {
++ .name = "mpu"
++};
++
++struct omap_hwmod_class iva_hwmod_class = {
++ .name = "iva"
++};
++
++/* Common MPU IRQ line data */
++
+ struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
+ { .irq = 37, },
+ { .irq = -1 }
+@@ -138,5 +162,73 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
+ { .irq = -1 }
+ };
+
++/* Common DMA request line data */
++struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 32 },
++ { .name = "tx", .dma_req = 31 },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 34 },
++ { .name = "tx", .dma_req = 33 },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 18 },
++ { .name = "tx", .dma_req = 17 },
++ { .dma_req = -1 }
++};
+
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+index 5a078a6..f5b63ef 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+@@ -10,6 +10,7 @@
+ */
+ #include <plat/omap_hwmod.h>
+ #include <plat/serial.h>
++#include <plat/dma.h>
+
+ #include <mach/irqs.h>
+
+@@ -19,3 +20,8 @@ struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
+ { .irq = 48, },
+ { .irq = -1 }
+ };
++
++struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
++ { .name = "dispc", .dma_req = 5 },
++ { .dma_req = -1 }
++};
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 265f0b1..001f67b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1210,12 +1210,6 @@ static struct omap_hwmod_class uart_class = {
+
+ /* UART1 */
+
+-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+ &omap3_l4_core__uart1,
+ };
+@@ -1223,7 +1217,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+- .sdma_reqs = uart1_sdma_reqs,
++ .sdma_reqs = omap2_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1242,12 +1236,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+
+ /* UART2 */
+
+-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+ &omap3_l4_core__uart2,
+ };
+@@ -1255,7 +1243,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+- .sdma_reqs = uart2_sdma_reqs,
++ .sdma_reqs = omap2_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1274,12 +1262,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+
+ /* UART3 */
+
+-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+ &omap3_l4_per__uart3,
+ };
+@@ -1287,7 +1269,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+- .sdma_reqs = uart3_sdma_reqs,
++ .sdma_reqs = omap2_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1714,12 +1696,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ };
+
+-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+ &omap3_l4_core__i2c1,
+ };
+@@ -1727,7 +1703,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+- .sdma_reqs = i2c1_sdma_reqs,
++ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1751,12 +1727,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ };
+
+-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+ &omap3_l4_core__i2c2,
+ };
+@@ -1764,7 +1734,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+- .sdma_reqs = i2c2_sdma_reqs,
++ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2269,12 +2239,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
+- { .name = "rx", .dma_req = 32 },
+- { .name = "tx", .dma_req = 31 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+ {
+ .name = "mpu",
+@@ -2303,7 +2267,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp1_irqs,
+- .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
++ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2327,12 +2291,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
+- { .name = "rx", .dma_req = 34 },
+- { .name = "tx", .dma_req = 33 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+ {
+ .name = "mpu",
+@@ -2349,7 +2307,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+ .slave = &omap3xxx_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap3xxx_mcbsp2_addrs,
+-
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -2366,7 +2323,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_irqs,
+- .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
++ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2391,12 +2348,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+ { .irq = -1 }
+ };
+
+-static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
+- { .name = "rx", .dma_req = 18 },
+- { .name = "tx", .dma_req = 17 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+ {
+ .name = "mpu",
+@@ -2429,7 +2380,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_irqs,
+- .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
++ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2939,18 +2890,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
+ };
+
+ /* mcspi1 */
+-static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 35 },
+- { .name = "rx0", .dma_req = 36 },
+- { .name = "tx1", .dma_req = 37 },
+- { .name = "rx1", .dma_req = 38 },
+- { .name = "tx2", .dma_req = 39 },
+- { .name = "rx2", .dma_req = 40 },
+- { .name = "tx3", .dma_req = 41 },
+- { .name = "rx3", .dma_req = 42 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
+ &omap34xx_l4_core__mcspi1,
+ };
+@@ -2962,7 +2901,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi1 = {
+ .name = "mcspi1",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+- .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
++ .sdma_reqs = omap2_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -2981,14 +2920,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
+ };
+
+ /* mcspi2 */
+-static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 43 },
+- { .name = "rx0", .dma_req = 44 },
+- { .name = "tx1", .dma_req = 45 },
+- { .name = "rx1", .dma_req = 46 },
+- { .dma_req = -1 }
+-};
+-
+ static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
+ &omap34xx_l4_core__mcspi2,
+ };
+@@ -3000,7 +2931,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ static struct omap_hwmod omap34xx_mcspi2 = {
+ .name = "mcspi2",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+- .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
++ .sdma_reqs = omap2_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
+index 08a1342..de832eb 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
+@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
+ .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
+ };
+
+-
+-/*
+- * omap_hwmod class data
+- */
+-
+-struct omap_hwmod_class l3_hwmod_class = {
+- .name = "l3"
+-};
+-
+-struct omap_hwmod_class l4_hwmod_class = {
+- .name = "l4"
+-};
+-
+-struct omap_hwmod_class mpu_hwmod_class = {
+- .name = "mpu"
+-};
+-
+-struct omap_hwmod_class iva_hwmod_class = {
+- .name = "iva"
+-};
+diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+index 1ac878c..b636cf6 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
++++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+@@ -51,6 +51,21 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+
+ /* Common IP block data across OMAP2xxx */
+ extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
++extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
++
++/* Common IP block data */
++extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
++extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
++
++/* Common IP block data on OMAP2430/OMAP3 */
++extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
+
+ /* Common IP block data across OMAP2/3 */
+ extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0043-omap_hwmod-share-identical-omap_hwmod_class-omap_hwm.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0043-omap_hwmod-share-identical-omap_hwmod_class-omap_hwm.patch
--- /dev/null
@@ -0,0 +1,1730 @@
+From ba46491cf72d4ef519dbdb43c16936e5641e8c17 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sat, 9 Jul 2011 19:14:08 -0600
+Subject: [PATCH 043/149] omap_hwmod: share identical omap_hwmod_class, omap_hwmod_class_sysconfig arrays
+
+To reduce kernel source file data duplication, share struct
+omap_hwmod_class and omap_hwmod_class_sysconfig arrays across OMAP2xxx
+and 3xxx hwmod data files.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 267 +++-----------------
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 273 +++-----------------
+ .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 228 +++++++++++-----
+ arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 123 +++++++++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 105 +-------
+ arch/arm/mach-omap2/omap_hwmod_common_data.h | 11 +
+ 6 files changed, 364 insertions(+), 643 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 6acc01f..f3901ab 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -274,24 +274,6 @@ static struct omap_hwmod omap2420_iva_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+-/* Timer Common */
+-static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+- .name = "timer",
+- .sysc = &omap2420_timer_sysc,
+- .rev = OMAP_TIMER_IP_VERSION_1,
+-};
+-
+ /* timer1 */
+ static struct omap_hwmod omap2420_timer1_hwmod;
+
+@@ -334,7 +316,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
+ },
+ .slaves = omap2420_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -371,7 +353,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
+ },
+ .slaves = omap2420_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -408,7 +390,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
+ },
+ .slaves = omap2420_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -445,7 +427,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
+ },
+ .slaves = omap2420_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -482,7 +464,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
+ },
+ .slaves = omap2420_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -520,7 +502,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
+ },
+ .slaves = omap2420_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -557,7 +539,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
+ },
+ .slaves = omap2420_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -594,7 +576,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
+ },
+ .slaves = omap2420_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -631,7 +613,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
+ },
+ .slaves = omap2420_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -668,7 +650,7 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
+ },
+ .slaves = omap2420_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -705,7 +687,7 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
+ },
+ .slaves = omap2420_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -742,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
+ },
+ .slaves = omap2420_timer12_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
+- .class = &omap2420_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
+@@ -764,27 +746,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+-/*
+- * 'wd_timer' class
+- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+- * overflow condition
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
+- .name = "wd_timer",
+- .sysc = &omap2420_wd_timer_sysc,
+- .pre_shutdown = &omap2_wd_timer_disable
+-};
+-
+ /* wd_timer2 */
+ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
+ &omap2420_l4_wkup__wd_timer2,
+@@ -792,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
+
+ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+- .class = &omap2420_wd_timer_hwmod_class,
++ .class = &omap2xxx_wd_timer_hwmod_class,
+ .main_clk = "mpu_wdt_fck",
+ .prcm = {
+ .omap2 = {
+@@ -808,24 +769,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+-/* UART */
+-
+-static struct omap_hwmod_class_sysconfig uart_sysc = {
+- .rev_offs = 0x50,
+- .sysc_offs = 0x54,
+- .syss_offs = 0x58,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class uart_class = {
+- .name = "uart",
+- .sysc = &uart_sysc,
+-};
+-
+ /* UART1 */
+
+ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+@@ -848,7 +791,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
+ },
+ .slaves = omap2420_uart1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+@@ -874,7 +817,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
+ },
+ .slaves = omap2420_uart2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+@@ -900,28 +843,10 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
+ },
+ .slaves = omap2420_uart3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+-/*
+- * 'dss' class
+- * display sub-system
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_dss_hwmod_class = {
+- .name = "dss",
+- .sysc = &omap2420_dss_sysc,
+-};
+-
+ /* dss */
+ /* dss master ports */
+ static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
+@@ -955,7 +880,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+
+ static struct omap_hwmod omap2420_dss_core_hwmod = {
+ .name = "dss_core",
+- .class = &omap2420_dss_hwmod_class,
++ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+ .sdma_reqs = omap2xxx_dss_sdma_chs,
+ .prcm = {
+@@ -977,27 +902,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'dispc' class
+- * display controller
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
+- .name = "dispc",
+- .sysc = &omap2420_dispc_sysc,
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1020,7 +924,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
+
+ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+- .class = &omap2420_dispc_hwmod_class,
++ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_fck",
+ .prcm = {
+@@ -1038,26 +942,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'rfbi' class
+- * remote frame buffer interface
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
+- .name = "rfbi",
+- .sysc = &omap2420_rfbi_sysc,
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1080,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
+
+ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+- .class = &omap2420_rfbi_hwmod_class,
++ .class = &omap2_rfbi_hwmod_class,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1095,15 +979,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'venc' class
+- * video encoder
+- */
+-
+-static struct omap_hwmod_class omap2420_venc_hwmod_class = {
+- .name = "venc",
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -1127,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
+
+ static struct omap_hwmod omap2420_dss_venc_hwmod = {
+ .name = "dss_venc",
+- .class = &omap2420_venc_hwmod_class,
++ .class = &omap2_venc_hwmod_class,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1292,27 +1167,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .dbck_flag = false,
+ };
+
+-static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+- SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-/*
+- * 'gpio' class
+- * general purpose io module
+- */
+-static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+- .name = "gpio",
+- .sysc = &omap242x_gpio_sysc,
+- .rev = 0,
+-};
+-
+ /* gpio1 */
+ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+ &omap2420_l4_wkup__gpio1,
+@@ -1334,7 +1188,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
+ },
+ .slaves = omap2420_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
+- .class = &omap242x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+@@ -1360,7 +1214,7 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
+ },
+ .slaves = omap2420_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
+- .class = &omap242x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+@@ -1386,7 +1240,7 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
+ },
+ .slaves = omap2420_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
+- .class = &omap242x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+@@ -1412,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
+ },
+ .slaves = omap2420_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
+- .class = &omap242x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+-/* system dma */
+-static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x002c,
+- .syss_offs = 0x0028,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_dma_hwmod_class = {
+- .name = "dma",
+- .sysc = &omap2420_dma_sysc,
+-};
+-
+ /* dma attributes */
+ static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+@@ -1470,7 +1307,7 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
+
+ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .name = "dma",
+- .class = &omap2420_dma_hwmod_class,
++ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .slaves = omap2420_dma_system_slaves,
+@@ -1482,27 +1319,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'mailbox' class
+- * mailbox module allowing communication between the on-chip processors
+- * using a queued mailbox-interrupt mechanism.
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+- .rev_offs = 0x000,
+- .sysc_offs = 0x010,
+- .syss_offs = 0x014,
+- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+- .name = "mailbox",
+- .sysc = &omap2420_mailbox_sysc,
+-};
+-
+ /* mailbox */
+ static struct omap_hwmod omap2420_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+@@ -1526,7 +1342,7 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+
+ static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = "mailbox",
+- .class = &omap2420_mailbox_hwmod_class,
++ .class = &omap2xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+@@ -1543,29 +1359,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+-/*
+- * 'mcspi' class
+- * multichannel serial port interface (mcspi) / master/slave synchronous serial
+- * bus
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2420_mcspi_class = {
+- .name = "mcspi",
+- .sysc = &omap2420_mcspi_sysc,
+- .rev = OMAP2_MCSPI_REV,
+-};
+-
+ /* mcspi1 */
+ static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+ &omap2420_l4_core__mcspi1,
+@@ -1591,8 +1384,8 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
+ },
+ .slaves = omap2420_mcspi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
+- .class = &omap2420_mcspi_class,
+- .dev_attr = &omap_mcspi1_dev_attr,
++ .class = &omap2xxx_mcspi_class,
++ .dev_attr = &omap_mcspi1_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+@@ -1621,8 +1414,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ },
+ .slaves = omap2420_mcspi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
+- .class = &omap2420_mcspi_class,
+- .dev_attr = &omap_mcspi2_dev_attr,
++ .class = &omap2xxx_mcspi_class,
++ .dev_attr = &omap_mcspi2_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 639acd5..2a52f02 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -347,24 +347,6 @@ static struct omap_hwmod omap2430_iva_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+-/* Timer Common */
+-static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+- .name = "timer",
+- .sysc = &omap2430_timer_sysc,
+- .rev = OMAP_TIMER_IP_VERSION_1,
+-};
+-
+ /* timer1 */
+ static struct omap_hwmod omap2430_timer1_hwmod;
+
+@@ -407,7 +389,7 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
+ },
+ .slaves = omap2430_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -444,7 +426,7 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
+ },
+ .slaves = omap2430_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -481,7 +463,7 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
+ },
+ .slaves = omap2430_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -518,7 +500,7 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
+ },
+ .slaves = omap2430_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -555,7 +537,7 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
+ },
+ .slaves = omap2430_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -592,7 +574,7 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
+ },
+ .slaves = omap2430_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -629,7 +611,7 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
+ },
+ .slaves = omap2430_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -666,7 +648,7 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
+ },
+ .slaves = omap2430_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -703,7 +685,7 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
+ },
+ .slaves = omap2430_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -740,7 +722,7 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
+ },
+ .slaves = omap2430_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -777,7 +759,7 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
+ },
+ .slaves = omap2430_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -814,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
+ },
+ .slaves = omap2430_timer12_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
+- .class = &omap2430_timer_hwmod_class,
++ .class = &omap2xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
+@@ -836,27 +818,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+-/*
+- * 'wd_timer' class
+- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+- * overflow condition
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
+- .rev_offs = 0x0,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
+- .name = "wd_timer",
+- .sysc = &omap2430_wd_timer_sysc,
+- .pre_shutdown = &omap2_wd_timer_disable
+-};
+-
+ /* wd_timer2 */
+ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
+ &omap2430_l4_wkup__wd_timer2,
+@@ -864,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
+
+ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+- .class = &omap2430_wd_timer_hwmod_class,
++ .class = &omap2xxx_wd_timer_hwmod_class,
+ .main_clk = "mpu_wdt_fck",
+ .prcm = {
+ .omap2 = {
+@@ -880,24 +841,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+-/* UART */
+-
+-static struct omap_hwmod_class_sysconfig uart_sysc = {
+- .rev_offs = 0x50,
+- .sysc_offs = 0x54,
+- .syss_offs = 0x58,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class uart_class = {
+- .name = "uart",
+- .sysc = &uart_sysc,
+-};
+-
+ /* UART1 */
+
+ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+@@ -920,7 +863,7 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
+ },
+ .slaves = omap2430_uart1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+@@ -946,7 +889,7 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
+ },
+ .slaves = omap2430_uart2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+@@ -972,28 +915,10 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
+ },
+ .slaves = omap2430_uart3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+-/*
+- * 'dss' class
+- * display sub-system
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_dss_hwmod_class = {
+- .name = "dss",
+- .sysc = &omap2430_dss_sysc,
+-};
+-
+ /* dss */
+ /* dss master ports */
+ static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
+@@ -1021,7 +946,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+
+ static struct omap_hwmod omap2430_dss_core_hwmod = {
+ .name = "dss_core",
+- .class = &omap2430_dss_hwmod_class,
++ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+ .sdma_reqs = omap2xxx_dss_sdma_chs,
+ .prcm = {
+@@ -1043,27 +968,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'dispc' class
+- * display controller
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
+- .name = "dispc",
+- .sysc = &omap2430_dispc_sysc,
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1080,7 +984,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
+
+ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+- .class = &omap2430_dispc_hwmod_class,
++ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_fck",
+ .prcm = {
+@@ -1098,26 +1002,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'rfbi' class
+- * remote frame buffer interface
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
+- .name = "rfbi",
+- .sysc = &omap2430_rfbi_sysc,
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1134,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
+
+ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+- .class = &omap2430_rfbi_hwmod_class,
++ .class = &omap2_rfbi_hwmod_class,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1149,15 +1033,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'venc' class
+- * video encoder
+- */
+-
+-static struct omap_hwmod_class omap2430_venc_hwmod_class = {
+- .name = "venc",
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+ .master = &omap2430_l4_core_hwmod,
+@@ -1175,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
+
+ static struct omap_hwmod omap2430_dss_venc_hwmod = {
+ .name = "dss_venc",
+- .class = &omap2430_venc_hwmod_class,
++ .class = &omap2_venc_hwmod_class,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1367,27 +1242,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .dbck_flag = false,
+ };
+
+-static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+- SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-/*
+- * 'gpio' class
+- * general purpose io module
+- */
+-static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+- .name = "gpio",
+- .sysc = &omap243x_gpio_sysc,
+- .rev = 0,
+-};
+-
+ /* gpio1 */
+ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+ &omap2430_l4_wkup__gpio1,
+@@ -1409,7 +1263,7 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
+ },
+ .slaves = omap2430_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
+- .class = &omap243x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+@@ -1435,7 +1289,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
+ },
+ .slaves = omap2430_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
+- .class = &omap243x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+@@ -1461,7 +1315,7 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
+ },
+ .slaves = omap2430_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
+- .class = &omap243x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+@@ -1487,7 +1341,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
+ },
+ .slaves = omap2430_gpio4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
+- .class = &omap243x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+@@ -1518,28 +1372,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
+ },
+ .slaves = omap2430_gpio5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
+- .class = &omap243x_gpio_hwmod_class,
++ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+-/* dma_system */
+-static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x002c,
+- .syss_offs = 0x0028,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_dma_hwmod_class = {
+- .name = "dma",
+- .sysc = &omap2430_dma_sysc,
+-};
+-
+ /* dma attributes */
+ static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+@@ -1576,7 +1413,7 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
+
+ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .name = "dma",
+- .class = &omap2430_dma_hwmod_class,
++ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .slaves = omap2430_dma_system_slaves,
+@@ -1588,27 +1425,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'mailbox' class
+- * mailbox module allowing communication between the on-chip processors
+- * using a queued mailbox-interrupt mechanism.
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+- .rev_offs = 0x000,
+- .sysc_offs = 0x010,
+- .syss_offs = 0x014,
+- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+- .name = "mailbox",
+- .sysc = &omap2430_mailbox_sysc,
+-};
+-
+ /* mailbox */
+ static struct omap_hwmod omap2430_mailbox_hwmod;
+ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+@@ -1631,7 +1447,7 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+
+ static struct omap_hwmod omap2430_mailbox_hwmod = {
+ .name = "mailbox",
+- .class = &omap2430_mailbox_hwmod_class,
++ .class = &omap2xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap2430_mailbox_irqs,
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+@@ -1648,29 +1464,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+-/*
+- * 'mcspi' class
+- * multichannel serial port interface (mcspi) / master/slave synchronous serial
+- * bus
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap2430_mcspi_class = {
+- .name = "mcspi",
+- .sysc = &omap2430_mcspi_sysc,
+- .rev = OMAP2_MCSPI_REV,
+-};
+-
+ /* mcspi1 */
+ static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+ &omap2430_l4_core__mcspi1,
+@@ -1696,8 +1489,8 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
+ },
+ .slaves = omap2430_mcspi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
+- .class = &omap2430_mcspi_class,
+- .dev_attr = &omap_mcspi1_dev_attr,
++ .class = &omap2xxx_mcspi_class,
++ .dev_attr = &omap_mcspi1_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+@@ -1726,8 +1519,8 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
+ },
+ .slaves = omap2430_mcspi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
+- .class = &omap2430_mcspi_class,
+- .dev_attr = &omap_mcspi2_dev_attr,
++ .class = &omap2xxx_mcspi_class,
++ .dev_attr = &omap_mcspi2_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+@@ -1769,8 +1562,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
+ },
+ .slaves = omap2430_mcspi3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
+- .class = &omap2430_mcspi_class,
+- .dev_attr = &omap_mcspi3_dev_attr,
++ .class = &omap2xxx_mcspi_class,
++ .dev_attr = &omap_mcspi3_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+index 7c4f5ab..c451729 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+@@ -16,6 +16,164 @@
+
+ #include "omap_hwmod_common_data.h"
+
++/* UART */
++
++static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
++ .rev_offs = 0x50,
++ .sysc_offs = 0x54,
++ .syss_offs = 0x58,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2_uart_class = {
++ .name = "uart",
++ .sysc = &omap2_uart_sysc,
++};
++
++/*
++ * 'dss' class
++ * display sub-system
++ */
++
++static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2_dss_hwmod_class = {
++ .name = "dss",
++ .sysc = &omap2_dss_sysc,
++};
++
++/*
++ * 'dispc' class
++ * display controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2_dispc_hwmod_class = {
++ .name = "dispc",
++ .sysc = &omap2_dispc_sysc,
++};
++
++/*
++ * 'rfbi' class
++ * remote frame buffer interface
++ */
++
++static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2_rfbi_hwmod_class = {
++ .name = "rfbi",
++ .sysc = &omap2_rfbi_sysc,
++};
++
++/*
++ * 'venc' class
++ * video encoder
++ */
++
++struct omap_hwmod_class omap2_venc_hwmod_class = {
++ .name = "venc",
++};
++
++
++/* Common DMA request line data */
++struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 32 },
++ { .name = "tx", .dma_req = 31 },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 34 },
++ { .name = "tx", .dma_req = 33 },
++ { .dma_req = -1 }
++};
++
++struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
++ { .name = "rx", .dma_req = 18 },
++ { .name = "tx", .dma_req = 17 },
++ { .dma_req = -1 }
++};
++
++/* Other IP block data */
++
+
+ /*
+ * omap_hwmod class data
+@@ -162,73 +320,3 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
+ { .irq = -1 }
+ };
+
+-/* Common DMA request line data */
+-struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
+- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
+- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+- { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+- { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+- { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+- { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+- { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+- { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+- { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
+- { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+- { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+- { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+- { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
+- { .name = "rx", .dma_req = 32 },
+- { .name = "tx", .dma_req = 31 },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
+- { .name = "rx", .dma_req = 34 },
+- { .name = "tx", .dma_req = 33 },
+- { .dma_req = -1 }
+-};
+-
+-struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
+- { .name = "rx", .dma_req = 18 },
+- { .name = "tx", .dma_req = 17 },
+- { .dma_req = -1 }
+-};
+-
+-
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+index f5b63ef..177dee2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+@@ -11,10 +11,13 @@
+ #include <plat/omap_hwmod.h>
+ #include <plat/serial.h>
+ #include <plat/dma.h>
++#include <plat/dmtimer.h>
++#include <plat/mcspi.h>
+
+ #include <mach/irqs.h>
+
+ #include "omap_hwmod_common_data.h"
++#include "wd_timer.h"
+
+ struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
+ { .irq = 48, },
+@@ -25,3 +28,123 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
+ { .dma_req = -1 }
+ };
++/* OMAP2xxx Timer Common */
++static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap2xxx_timer_sysc,
++ .rev = OMAP_TIMER_IP_VERSION_1,
++};
++
++/*
++ * 'wd_timer' class
++ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
++ * overflow condition
++ */
++
++static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
++ .name = "wd_timer",
++ .sysc = &omap2xxx_wd_timer_sysc,
++ .pre_shutdown = &omap2_wd_timer_disable
++};
++
++/*
++ * 'gpio' class
++ * general purpose io module
++ */
++static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
++ .name = "gpio",
++ .sysc = &omap2xxx_gpio_sysc,
++ .rev = 0,
++};
++
++/* system dma */
++static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x002c,
++ .syss_offs = 0x0028,
++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
++ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
++ .name = "dma",
++ .sysc = &omap2xxx_dma_sysc,
++};
++
++/*
++ * 'mailbox' class
++ * mailbox module allowing communication between the on-chip processors
++ * using a queued mailbox-interrupt mechanism.
++ */
++
++static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
++ .rev_offs = 0x000,
++ .sysc_offs = 0x010,
++ .syss_offs = 0x014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
++ .name = "mailbox",
++ .sysc = &omap2xxx_mailbox_sysc,
++};
++
++/*
++ * 'mcspi' class
++ * multichannel serial port interface (mcspi) / master/slave synchronous serial
++ * bus
++ */
++
++static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++struct omap_hwmod_class omap2xxx_mcspi_class = {
++ .name = "mcspi",
++ .sysc = &omap2xxx_mcspi_sysc,
++ .rev = OMAP2_MCSPI_REV,
++};
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 001f67b..1a52716 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1190,24 +1190,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+ .flags = HWMOD_SWSUP_SIDLE,
+ };
+
+-/* UART common */
+-
+-static struct omap_hwmod_class_sysconfig uart_sysc = {
+- .rev_offs = 0x50,
+- .sysc_offs = 0x54,
+- .syss_offs = 0x58,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class uart_class = {
+- .name = "uart",
+- .sysc = &uart_sysc,
+-};
+-
+ /* UART1 */
+
+ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+@@ -1230,7 +1212,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ },
+ .slaves = omap3xxx_uart1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+@@ -1256,7 +1238,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ },
+ .slaves = omap3xxx_uart2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+@@ -1282,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ },
+ .slaves = omap3xxx_uart3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+@@ -1319,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ },
+ .slaves = omap3xxx_uart4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
+- .class = &uart_class,
++ .class = &omap2_uart_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ };
+
+@@ -1328,24 +1310,6 @@ static struct omap_hwmod_class i2c_class = {
+ .sysc = &i2c_sysc,
+ };
+
+-/*
+- * 'dss' class
+- * display sub-system
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
+- .name = "dss",
+- .sysc = &omap3xxx_dss_sysc,
+-};
+-
+ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
+ { .name = "dsi1", .dma_req = 74 },
+@@ -1406,7 +1370,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+
+ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+ .name = "dss_core",
+- .class = &omap3xxx_dss_hwmod_class,
++ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
+ .prcm = {
+@@ -1430,7 +1394,7 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+
+ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+ .name = "dss_core",
+- .class = &omap3xxx_dss_hwmod_class,
++ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
+ .prcm = {
+@@ -1453,28 +1417,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+ CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
+ };
+
+-/*
+- * 'dispc' class
+- * display controller
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+- SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
+- .name = "dispc",
+- .sysc = &omap3xxx_dispc_sysc,
+-};
+-
+ /* l4_core -> dss_dispc */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+ .master = &omap3xxx_l4_core_hwmod,
+@@ -1498,7 +1440,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+- .class = &omap3xxx_dispc_hwmod_class,
++ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+@@ -1580,26 +1522,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'rfbi' class
+- * remote frame buffer interface
+- */
+-
+-static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
+- .rev_offs = 0x0000,
+- .sysc_offs = 0x0010,
+- .syss_offs = 0x0014,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
+-};
+-
+-static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
+- .name = "rfbi",
+- .sysc = &omap3xxx_rfbi_sysc,
+-};
+-
+ /* l4_core -> dss_rfbi */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+ .master = &omap3xxx_l4_core_hwmod,
+@@ -1623,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+- .class = &omap3xxx_rfbi_hwmod_class,
++ .class = &omap2_rfbi_hwmod_class,
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+ .omap2 = {
+@@ -1640,15 +1562,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
+-/*
+- * 'venc' class
+- * video encoder
+- */
+-
+-static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
+- .name = "venc",
+-};
+-
+ /* l4_core -> dss_venc */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+ .master = &omap3xxx_l4_core_hwmod,
+@@ -1673,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
+ .name = "dss_venc",
+- .class = &omap3xxx_venc_hwmod_class,
++ .class = &omap2_venc_hwmod_class,
+ .main_clk = "dss1_alwon_fck",
+ .prcm = {
+ .omap2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+index b636cf6..39a7c37 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
++++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
+@@ -98,6 +98,17 @@ extern struct omap_hwmod_class l3_hwmod_class;
+ extern struct omap_hwmod_class l4_hwmod_class;
+ extern struct omap_hwmod_class mpu_hwmod_class;
+ extern struct omap_hwmod_class iva_hwmod_class;
++extern struct omap_hwmod_class omap2_uart_class;
++extern struct omap_hwmod_class omap2_dss_hwmod_class;
++extern struct omap_hwmod_class omap2_dispc_hwmod_class;
++extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
++extern struct omap_hwmod_class omap2_venc_hwmod_class;
+
++extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
++extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
++extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
++extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
++extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
++extern struct omap_hwmod_class omap2xxx_mcspi_class;
+
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0044-OMAP4-hwmod-data-Fix-L3-interconnect-data-order-and-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0044-OMAP4-hwmod-data-Fix-L3-interconnect-data-order-and-.patch
--- /dev/null
@@ -0,0 +1,116 @@
+From 96fade0623664f946eceba792415d3dc78e3ec52 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:27 -0600
+Subject: [PATCH 044/149] OMAP4: hwmod data: Fix L3 interconnect data order and alignement
+
+Change the position of the ocp_if structure to match the template.
+
+Remove unneeded comma at the end of address space flag field.
+
+Remove USER_SDMA since this ocp link is only from the l3_main_1
+path that is accessible only from the MPU in that case and not
+the SDMA.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 27 +++++++++++++--------------
+ 1 files changed, 13 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 316e922..94c0b60 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -216,6 +216,12 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ };
+
+ /* l3_main_1 interface data */
++static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
++ { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
++ { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
++};
++
+ /* dsp -> l3_main_1 */
+ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+ .master = &omap44xx_dsp_hwmod,
+@@ -264,18 +270,11 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+-/* L3 target configuration and error log registers */
+-static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
+- { .irq = 9 + OMAP44XX_IRQ_GIC_START },
+- { .irq = 10 + OMAP44XX_IRQ_GIC_START },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+ {
+ .pa_start = 0x44000000,
+ .pa_end = 0x44000fff,
+- .flags = ADDR_TYPE_RT,
++ .flags = ADDR_TYPE_RT
+ },
+ { }
+ };
+@@ -286,7 +285,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_1_addrs,
+- .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .user = OCP_USER_MPU,
+ };
+
+ /* l3_main_1 slave ports */
+@@ -303,9 +302,9 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap44xx_l3_hwmod_class,
+- .mpu_irqs = omap44xx_l3_targ_irqs,
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
++ .mpu_irqs = omap44xx_l3_main_1_irqs,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -354,7 +353,7 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+ {
+ .pa_start = 0x44800000,
+ .pa_end = 0x44801fff,
+- .flags = ADDR_TYPE_RT,
++ .flags = ADDR_TYPE_RT
+ },
+ { }
+ };
+@@ -365,7 +364,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_2_addrs,
+- .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .user = OCP_USER_MPU,
+ };
+
+ /* l4_cfg -> l3_main_2 */
+@@ -409,7 +408,7 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+ {
+ .pa_start = 0x45000000,
+ .pa_end = 0x45000fff,
+- .flags = ADDR_TYPE_RT,
++ .flags = ADDR_TYPE_RT
+ },
+ { }
+ };
+@@ -420,7 +419,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_3_addrs,
+- .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .user = OCP_USER_MPU,
+ };
+
+ /* l3_main_2 -> l3_main_3 */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0045-OMAP4-hwmod-data-Remove-un-needed-parens.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0045-OMAP4-hwmod-data-Remove-un-needed-parens.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0045-OMAP4-hwmod-data-Remove-un-needed-parens.patch
@@ -0,0 +1,42 @@
+From 526bd55990b58164ec3f96c5cc6c365418112e35 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:28 -0600
+Subject: [PATCH 045/149] OMAP4: hwmod data: Remove un-needed parens
+
+A couple of parens were added around some flags.
+
+Remove them, since they are not needed and not used
+for any other hwmods.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 94c0b60..7eed6a2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -3736,7 +3736,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
+ static struct omap_hwmod omap44xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &omap44xx_mpu_hwmod_class,
+- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
++ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+@@ -4750,7 +4750,7 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &omap44xx_uart_hwmod_class,
+- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
++ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_uart3_irqs,
+ .sdma_reqs = omap44xx_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0046-OMAP4-hwmod-data-Fix-bad-alignement.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0046-OMAP4-hwmod-data-Fix-bad-alignement.patch
--- /dev/null
@@ -0,0 +1,218 @@
+From 834f307ec9057bbdfb5136714f7a1e7ba629d556 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:28 -0600
+Subject: [PATCH 046/149] OMAP4: hwmod data: Fix bad alignement
+
+Fix .prcm alignement and usb_otg_hs class and hwmod structures.
+
+Add a couple of more potential hwmods in the comment.
+Remove hsi, since it is already included in the data.
+
+Remove one blank line.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 45 ++++++++++++++-------------
+ 1 files changed, 23 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 7eed6a2..1975b05 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -632,7 +632,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * gpmc
+ * gpu
+ * hdq1w
+- * hsi
++ * mcasp
++ * mpu_c0
++ * mpu_c1
+ * ocmc_ram
+ * ocp2scp_usb_phy
+ * ocp_wp_noc
+@@ -740,7 +742,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .mpu_irqs = omap44xx_aess_irqs,
+ .sdma_reqs = omap44xx_aess_sdma_reqs,
+ .main_clk = "aess_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+ },
+@@ -769,7 +771,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
+ static struct omap_hwmod omap44xx_bandgap_hwmod = {
+ .name = "bandgap",
+ .class = &omap44xx_bandgap_hwmod_class,
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+ },
+@@ -828,7 +830,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+ .class = &omap44xx_counter_hwmod_class,
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "sys_32k_ck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
+ },
+@@ -1004,7 +1006,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .mpu_irqs = omap44xx_dmic_irqs,
+ .sdma_reqs = omap44xx_dmic_sdma_reqs,
+ .main_clk = "dmic_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+ },
+@@ -2094,7 +2096,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .class = &omap44xx_hsi_hwmod_class,
+ .mpu_irqs = omap44xx_hsi_irqs,
+ .main_clk = "hsi_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+ },
+@@ -2391,7 +2393,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_ipu_c0_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ },
+@@ -2406,7 +2408,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_ipu_c1_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ },
+@@ -2421,7 +2423,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .rst_lines = omap44xx_ipu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
+ .main_clk = "ipu_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+@@ -2507,7 +2509,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .mpu_irqs = omap44xx_iss_irqs,
+ .sdma_reqs = omap44xx_iss_sdma_reqs,
+ .main_clk = "iss_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
+ },
+@@ -2687,7 +2689,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .class = &omap44xx_kbd_hwmod_class,
+ .mpu_irqs = omap44xx_kbd_irqs,
+ .main_clk = "kbd_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+ },
+@@ -2751,7 +2753,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+@@ -3133,7 +3135,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .mpu_irqs = omap44xx_mcpdm_irqs,
+ .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
+ .main_clk = "mcpdm_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+ },
+@@ -3430,7 +3432,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
+ };
+
+ /* mmc1 */
+-
+ static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+ { .irq = 83 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+@@ -3481,7 +3482,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .mpu_irqs = omap44xx_mmc1_irqs,
+ .sdma_reqs = omap44xx_mmc1_sdma_reqs,
+ .main_clk = "mmc1_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+ },
+@@ -3540,7 +3541,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .mpu_irqs = omap44xx_mmc2_irqs,
+ .sdma_reqs = omap44xx_mmc2_sdma_reqs,
+ .main_clk = "mmc2_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+ },
+@@ -3594,7 +3595,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .mpu_irqs = omap44xx_mmc3_irqs,
+ .sdma_reqs = omap44xx_mmc3_sdma_reqs,
+ .main_clk = "mmc3_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+ },
+@@ -3647,7 +3648,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+
+ .sdma_reqs = omap44xx_mmc4_sdma_reqs,
+ .main_clk = "mmc4_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+ },
+@@ -3699,7 +3700,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .mpu_irqs = omap44xx_mmc5_irqs,
+ .sdma_reqs = omap44xx_mmc5_sdma_reqs,
+ .main_clk = "mmc5_fck",
+- .prcm = {
++ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+ },
+@@ -4835,8 +4836,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
+ };
+
+ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+- .name = "usb_otg_hs",
+- .sysc = &omap44xx_usb_otg_hs_sysc,
++ .name = "usb_otg_hs",
++ .sysc = &omap44xx_usb_otg_hs_sysc,
+ };
+
+ /* usb_otg_hs */
+@@ -4890,7 +4891,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+- .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
++ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+ .slaves = omap44xx_usb_otg_hs_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
+ .masters = omap44xx_usb_otg_hs_masters,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0047-OMAP4-hwmod-data-Align-interconnect-format-with-regu.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0047-OMAP4-hwmod-data-Align-interconnect-format-with-regu.patch
--- /dev/null
@@ -0,0 +1,154 @@
+From ade0c25089e78eb5df97faf56924d9e65ec4a096 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:28 -0600
+Subject: [PATCH 047/149] OMAP4: hwmod data: Align interconnect format with regular modules
+
+The interconnect modules were using a slightly different layout than
+the regular modules.
+Align the layout for better consitency.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 36 ++++++++++++++--------------
+ 1 files changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 1975b05..e011437 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -80,7 +80,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
+ .name = "dmm",
+ };
+
+-/* dmm interface data */
++/* dmm */
++static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
++ { .irq = 113 + OMAP44XX_IRQ_GIC_START },
++ { .irq = -1 }
++};
++
+ /* l3_main_1 -> dmm */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+ .master = &omap44xx_l3_main_1_hwmod,
+@@ -113,17 +118,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+ &omap44xx_mpu__dmm,
+ };
+
+-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+- { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+- { .irq = -1 }
+-};
+-
+ static struct omap_hwmod omap44xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &omap44xx_dmm_hwmod_class,
++ .mpu_irqs = omap44xx_dmm_irqs,
+ .slaves = omap44xx_dmm_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
+- .mpu_irqs = omap44xx_dmm_irqs,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -135,7 +135,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+ };
+
+-/* emif_fw interface data */
++/* emif_fw */
+ /* dmm -> emif_fw */
+ static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+ .master = &omap44xx_dmm_hwmod,
+@@ -184,7 +184,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
+ .name = "l3",
+ };
+
+-/* l3_instr interface data */
++/* l3_instr */
+ /* iva -> l3_instr */
+ static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+ .master = &omap44xx_iva_hwmod,
+@@ -215,7 +215,7 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l3_main_1 interface data */
++/* l3_main_1 */
+ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
+ { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
+ { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
+@@ -302,13 +302,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap44xx_l3_hwmod_class,
++ .mpu_irqs = omap44xx_l3_main_1_irqs,
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+- .mpu_irqs = omap44xx_l3_main_1_irqs,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l3_main_2 interface data */
++/* l3_main_2 */
+ /* dma_system -> l3_main_2 */
+ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+ .master = &omap44xx_dma_system_hwmod,
+@@ -403,7 +403,7 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l3_main_3 interface data */
++/* l3_main_3 */
+ static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+ {
+ .pa_start = 0x45000000,
+@@ -461,7 +461,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
+ .name = "l4",
+ };
+
+-/* l4_abe interface data */
++/* l4_abe */
+ /* aess -> l4_abe */
+ static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+ .master = &omap44xx_aess_hwmod,
+@@ -510,7 +510,7 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l4_cfg interface data */
++/* l4_cfg */
+ /* l3_main_1 -> l4_cfg */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+ .master = &omap44xx_l3_main_1_hwmod,
+@@ -532,7 +532,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l4_per interface data */
++/* l4_per */
+ /* l3_main_2 -> l4_per */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+ .master = &omap44xx_l3_main_2_hwmod,
+@@ -554,7 +554,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-/* l4_wkup interface data */
++/* l4_wkup */
+ /* l4_cfg -> l4_wkup */
+ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+ .master = &omap44xx_l4_cfg_hwmod,
+@@ -584,7 +584,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
+ .name = "mpu_bus",
+ };
+
+-/* mpu_private interface data */
++/* mpu_private */
+ /* mpu -> mpu_private */
+ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+ .master = &omap44xx_mpu_hwmod,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0048-OMAP4-clock-data-Add-sddiv-to-USB-DPLL.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0048-OMAP4-clock-data-Add-sddiv-to-USB-DPLL.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0048-OMAP4-clock-data-Add-sddiv-to-USB-DPLL.patch
@@ -0,0 +1,31 @@
+From 8324148fb1a7879854e2afdf20f911ac9ea57210 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:45 -0600
+Subject: [PATCH 048/149] OMAP4: clock data: Add sddiv to USB DPLL
+
+The USB DPLL is a J-Type DPLL with the sddiv extra parameter. Add it
+in USB DPLL.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+[paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 8c96567..f28a9c9 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -1015,6 +1015,7 @@ static struct dpll_data dpll_usb_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
++ .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
+ .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+ .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .min_divider = 1,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0049-OMAP4-clock-data-Remove-usb_host_fs-clkdev-with-NULL.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0049-OMAP4-clock-data-Remove-usb_host_fs-clkdev-with-NULL.patch
--- /dev/null
@@ -0,0 +1,48 @@
+From e5deffffe7722ea30862908bc7bcfe933ee98dbf Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:45 -0600
+Subject: [PATCH 049/149] OMAP4: clock data: Remove usb_host_fs clkdev with NULL dev
+
+usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0"
+and "fs_fck" alias used by the driver.
+The entry with NULL dev is thus not needed anymore.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index f28a9c9..0fa1cb8 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3205,7 +3205,6 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
+ CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
+- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
+ CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
+ CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
+ CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
+@@ -3217,7 +3216,6 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
+- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
+ CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
+ CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
+@@ -3227,7 +3225,6 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
+ CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
+ CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
+- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
+ CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
+ CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
+ CLK(NULL, "usim_ck", &usim_ck, CK_443X),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0050-OMAP4-clock-data-Re-order-some-clock-nodes-and-struc.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0050-OMAP4-clock-data-Re-order-some-clock-nodes-and-struc.patch
--- /dev/null
@@ -0,0 +1,229 @@
+From 64e6adf28c555e90d22260217e56f393b504262f Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:45 -0600
+Subject: [PATCH 050/149] OMAP4: clock data: Re-order some clock nodes and structure fields
+
+A couple of fieds were edited manually and thus do not stick
+to the template used by the generator and by other structures.
+
+Move them to the correct location.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+[paul@pwsan.com: dropped the UNIPRO changes since those will be removed
+ in a later patch]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 66 +++++++++++++++++----------------
+ 1 files changed, 34 insertions(+), 32 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 0fa1cb8..4b57d55 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
+ static struct clk pad_clks_ck = {
+ .name = "pad_clks_ck",
+ .rate = 12000000,
+- .ops = &clkops_omap2_dflt,
+- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+- .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
++ .ops = &clkops_omap2_dflt,
++ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
++ .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
+ };
+
+ static struct clk pad_slimbus_core_clks_ck = {
+@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
+ static struct clk slimbus_clk = {
+ .name = "slimbus_clk",
+ .rate = 12000000,
+- .ops = &clkops_omap2_dflt,
+- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+- .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
++ .ops = &clkops_omap2_dflt,
++ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
++ .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+ };
+
+ static struct clk sys_32k_ck = {
+@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
+ static struct clk dpll_abe_x2_ck = {
+ .name = "dpll_abe_x2_ck",
+ .parent = &dpll_abe_ck,
++ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap3_clkoutx2_recalc,
+- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ };
+
+ static const struct clksel_rate div31_1to31_rates[] = {
+@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
+ .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+ .ops = &clkops_omap2_dflt,
+- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
+- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
++ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
++ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+ };
+
+ static struct clk dpll_core_m7x2_ck = {
+@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
+ static struct clk dpll_per_x2_ck = {
+ .name = "dpll_per_x2_ck",
+ .parent = &dpll_per_ck,
++ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap3_clkoutx2_recalc,
+- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ };
+
+ static const struct clksel dpll_per_m2x2_div[] = {
+@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
+ .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
+ .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+ .ops = &clkops_omap2_dflt,
+- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
+- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
++ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
++ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+ };
+
+ static struct clk dpll_per_m4x2_ck = {
+@@ -970,8 +970,9 @@ static struct clk dpll_unipro_ck = {
+ static struct clk dpll_unipro_x2_ck = {
+ .name = "dpll_unipro_x2_ck",
+ .parent = &dpll_unipro_ck,
++ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+ .flags = CLOCK_CLKOUTX2,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap3_clkoutx2_recalc,
+ };
+
+@@ -1036,8 +1037,8 @@ static struct clk dpll_usb_ck = {
+ static struct clk dpll_usb_clkdcoldo_ck = {
+ .name = "dpll_usb_clkdcoldo_ck",
+ .parent = &dpll_usb_ck,
+- .ops = &clkops_omap4_dpllmx_ops,
+ .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &followparent_recalc,
+ };
+
+@@ -1847,8 +1848,8 @@ static struct clk l3_instr_ick = {
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
+ .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
+- .clkdm_name = "l3_instr_clkdm",
+ .flags = ENABLE_ON_INIT,
++ .clkdm_name = "l3_instr_clkdm",
+ .parent = &l3_div_ck,
+ .recalc = &followparent_recalc,
+ };
+@@ -1858,8 +1859,8 @@ static struct clk l3_main_3_ick = {
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
+ .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
+- .clkdm_name = "l3_instr_clkdm",
+ .flags = ENABLE_ON_INIT,
++ .clkdm_name = "l3_instr_clkdm",
+ .parent = &l3_div_ck,
+ .recalc = &followparent_recalc,
+ };
+@@ -2163,8 +2164,8 @@ static struct clk ocp_wp_noc_ick = {
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+ .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
+- .clkdm_name = "l3_instr_clkdm",
+ .flags = ENABLE_ON_INIT,
++ .clkdm_name = "l3_instr_clkdm",
+ .parent = &l3_div_ck,
+ .recalc = &followparent_recalc,
+ };
+@@ -2896,6 +2897,7 @@ static struct clk auxclk2_ck = {
+ .enable_reg = OMAP4_SCRM_AUXCLK2,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
++
+ static struct clk auxclk3_ck = {
+ .name = "auxclk3_ck",
+ .parent = &sys_clkin_ck,
+@@ -3217,7 +3219,6 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
+ CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
+- CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
+ CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
+ CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
+@@ -3226,15 +3227,25 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
+ CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
+ CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
+- CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
+ CLK(NULL, "usim_ck", &usim_ck, CK_443X),
+ CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
+ CLK(NULL, "usim_fck", &usim_fck, CK_443X),
+ CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
+- CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
+ CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
+ CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
++ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
++ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
++ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
++ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
++ CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
++ CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
++ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
++ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
++ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
++ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
++ CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
++ CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
+@@ -3251,6 +3262,7 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
++ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
+ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
+ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
+ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
+@@ -3268,19 +3280,9 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
++ CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
++ CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
+ CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
+- CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
+- CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
+- CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
+- CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
+- CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
+- CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
+- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
+- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
+- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
+- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
+- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
+- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
+ };
+
+ int __init omap4xxx_clk_init(void)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0051-OMAP4-clock-data-Fix-max-mult-and-div-for-USB-DPLL.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0051-OMAP4-clock-data-Fix-max-mult-and-div-for-USB-DPLL.patch
--- /dev/null
@@ -0,0 +1,143 @@
+From 6bf20dc93c089368a608a08926b8ac386102815f Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:14:46 -0600
+Subject: [PATCH 051/149] OMAP4: clock data: Fix max mult and div for USB DPLL
+
+The DPLL USB can generate higher speed (x2) than the regular ones.
+The max multiplication value is then twice the previous value.
+
+Fix both max_mult and max_div with that correct values.
+
+Change the max_div variable type to u16 to allow storing up to 256.
+
+Replace as well the define with the value to avoid
+unneeded indirection and provide a better readability.
+
+Remove the defines that become useless.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx.h | 7 -------
+ arch/arm/mach-omap2/clock44xx_data.c | 29 ++++++++++++++---------------
+ arch/arm/plat-omap/include/plat/clock.h | 2 +-
+ 3 files changed, 15 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
+index 6be1095..7ceb870 100644
+--- a/arch/arm/mach-omap2/clock44xx.h
++++ b/arch/arm/mach-omap2/clock44xx.h
+@@ -8,13 +8,6 @@
+ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
+ #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
+
+-/*
+- * XXX Missing values for the OMAP4 DPLL_USB
+- * XXX Missing min_multiplier values for all OMAP4 DPLLs
+- */
+-#define OMAP4430_MAX_DPLL_MULT 2047
+-#define OMAP4430_MAX_DPLL_DIV 128
+-
+ int omap4xxx_clk_init(void);
+
+ #endif
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 4b57d55..8307c9e 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -949,9 +949,8 @@ static struct dpll_data dpll_unipro_dd = {
+ .enable_mask = OMAP4430_DPLL_EN_MASK,
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 2047,
++ .max_divider = 128,
+ .min_divider = 1,
+ };
+
+@@ -1017,8 +1016,8 @@ static struct dpll_data dpll_usb_dd = {
+ .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+ .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
+- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+- .max_divider = OMAP4430_MAX_DPLL_DIV,
++ .max_multiplier = 4095,
++ .max_divider = 256,
+ .min_divider = 1,
+ };
+
+diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
+index 006e599..f57e064 100644
+--- a/arch/arm/plat-omap/include/plat/clock.h
++++ b/arch/arm/plat-omap/include/plat/clock.h
+@@ -152,7 +152,7 @@ struct dpll_data {
+ u16 max_multiplier;
+ u8 last_rounded_n;
+ u8 min_divider;
+- u8 max_divider;
++ u16 max_divider;
+ u8 modes;
+ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+ void __iomem *autoidle_reg;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0052-OMAP4-prcm-Fix-errors-in-few-defines-name.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0052-OMAP4-prcm-Fix-errors-in-few-defines-name.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0052-OMAP4-prcm-Fix-errors-in-few-defines-name.patch
@@ -0,0 +1,256 @@
+From 911f0274537657d1697f1bce1ba9594281d4fbf6 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:04 -0600
+Subject: [PATCH 052/149] OMAP4: prcm: Fix errors in few defines name
+
+A couple of macros were wrongly changed during the _MOD to _INST
+rename done in the following commit:
+
+ OMAP4: PRCM: rename _MOD macros to _INST
+ cdb54c4457d68994da7c2e16907adfbfc130060d
+
+Fix them to their original name.
+
+Some CM and PRM instances were not well aligned. Align them.
+
+Remove one blank line in cm2_44xx.h to align the output with
+the other (cm1_44xx.h, prm44xx.h) files.
+
+Update header copyright date.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cm1_44xx.h | 28 ++++++++++++++--------------
+ arch/arm/mach-omap2/cm2_44xx.h | 23 +++++++++++------------
+ arch/arm/mach-omap2/prm44xx.h | 22 +++++++++++-----------
+ 3 files changed, 36 insertions(+), 37 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
+index e2d7a56..fc649f5 100644
+--- a/arch/arm/mach-omap2/cm1_44xx.h
++++ b/arch/arm/mach-omap2/cm1_44xx.h
+@@ -1,7 +1,7 @@
+ /*
+ * OMAP44xx CM1 instance offset macros
+ *
+- * Copyright (C) 2009-2010 Texas Instruments, Inc.
++ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+@@ -41,9 +41,9 @@
+ #define OMAP4430_CM1_INSTR_INST 0x0f00
+
+ /* CM1 clockdomain register offsets (from instance start) */
+-#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
+-#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
+-#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
++#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
++#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
++#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
+
+ /* CM1 */
+
+@@ -82,8 +82,8 @@
+ #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
+ #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
+ #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
+ #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
+@@ -98,8 +98,8 @@
+ #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
+ #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
+ #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
+ #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
+@@ -116,8 +116,8 @@
+ #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
+ #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
+ #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
+ #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
+@@ -134,8 +134,8 @@
+ #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
+ #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
+ #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
+ #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
+@@ -154,8 +154,8 @@
+ #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
+ #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
+ #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
+ #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
+diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
+index aa47450..8036a16 100644
+--- a/arch/arm/mach-omap2/cm2_44xx.h
++++ b/arch/arm/mach-omap2/cm2_44xx.h
+@@ -1,7 +1,7 @@
+ /*
+ * OMAP44xx CM2 instance offset macros
+ *
+- * Copyright (C) 2009-2010 Texas Instruments, Inc.
++ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+@@ -40,9 +40,9 @@
+ #define OMAP4430_CM2_CAM_INST 0x1000
+ #define OMAP4430_CM2_DSS_INST 0x1100
+ #define OMAP4430_CM2_GFX_INST 0x1200
+-#define OMAP4430_CM2_L3INIT_INST 0x1300
++#define OMAP4430_CM2_L3INIT_INST 0x1300
+ #define OMAP4430_CM2_L4PER_INST 0x1400
+-#define OMAP4430_CM2_CEFUSE_INST 0x1600
++#define OMAP4430_CM2_CEFUSE_INST 0x1600
+ #define OMAP4430_CM2_RESTORE_INST 0x1e00
+ #define OMAP4430_CM2_INSTR_INST 0x1f00
+
+@@ -65,7 +65,6 @@
+ #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
+ #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
+
+-
+ /* CM2 */
+
+ /* CM2.OCP_SOCKET_CM2 register offsets */
+@@ -121,8 +120,8 @@
+ #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
+ #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
+ #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
+ #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
+@@ -135,8 +134,8 @@
+ #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
+ #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
+ #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
+ #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
+@@ -151,8 +150,8 @@
+ #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
+ #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
+ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
++#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
++#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
+
+ /* CM2.ALWAYS_ON_CM2 register offsets */
+ #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
+@@ -227,8 +226,8 @@
+ #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
+ #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
+ #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
+-#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
+-#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
++#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
++#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
+ #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
+ #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
+ #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 67a0d3f..2aec8c8 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -31,7 +31,7 @@
+ #define OMAP4430_PRM_BASE 0x4a306000
+
+ #define OMAP44XX_PRM_REGADDR(inst, reg) \
+- OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
++ OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+
+
+ /* PRM instances */
+@@ -46,14 +46,14 @@
+ #define OMAP4430_PRM_CAM_INST 0x1000
+ #define OMAP4430_PRM_DSS_INST 0x1100
+ #define OMAP4430_PRM_GFX_INST 0x1200
+-#define OMAP4430_PRM_L3INIT_INST 0x1300
++#define OMAP4430_PRM_L3INIT_INST 0x1300
+ #define OMAP4430_PRM_L4PER_INST 0x1400
+-#define OMAP4430_PRM_CEFUSE_INST 0x1600
++#define OMAP4430_PRM_CEFUSE_INST 0x1600
+ #define OMAP4430_PRM_WKUP_INST 0x1700
+ #define OMAP4430_PRM_WKUP_CM_INST 0x1800
+ #define OMAP4430_PRM_EMU_INST 0x1900
+-#define OMAP4430_PRM_EMU_CM_INST 0x1a00
+-#define OMAP4430_PRM_DEVICE_INST 0x1b00
++#define OMAP4430_PRM_EMU_CM_INST 0x1a00
++#define OMAP4430_PRM_DEVICE_INST 0x1b00
+ #define OMAP4430_PRM_INSTR_INST 0x1f00
+
+ /* PRM clockdomain register offsets (from instance start) */
+@@ -247,8 +247,8 @@
+ #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
+ #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
+ #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
+-#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
+-#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
++#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
++#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
+ #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
+ #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
+ #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
+@@ -713,8 +713,8 @@
+ #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
+ #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
+ #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
+-#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
+-#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
++#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
++#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
+ #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
+ #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
+ #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
+@@ -751,8 +751,8 @@
+ #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
+ #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
+ #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
+-#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
+-#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
++#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
++#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
+ #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
+ #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0053-OMAP4-prm-Remove-wrong-clockdomain-offsets.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0053-OMAP4-prm-Remove-wrong-clockdomain-offsets.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0053-OMAP4-prm-Remove-wrong-clockdomain-offsets.patch
@@ -0,0 +1,50 @@
+From e81a8c54e4567ecfdadb83d1574cc8a1cd865eac Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:04 -0600
+Subject: [PATCH 053/149] OMAP4: prm: Remove wrong clockdomain offsets
+
+The following commit introduced new macros to define an offset
+per clock domain in an instance.
+
+commit e4156ee52fe617c2c2d80b5db993ff4bf07d7c3c
+
+ OMAP4: CM instances: add clockdomain register offsets
+
+The PRM contains only two clock controls management entities:
+EMU and WKUP.
+Remove the other ones.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/prm44xx.h | 12 ------------
+ 1 files changed, 0 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 2aec8c8..6e53120 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -57,19 +57,7 @@
+ #define OMAP4430_PRM_INSTR_INST 0x1f00
+
+ /* PRM clockdomain register offsets (from instance start) */
+-#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
+-#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
+-#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
+-#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
+-#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
+-#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
+-#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
+-#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
+-#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
+-#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
+-#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
+ #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
+-#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
+ #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
+
+ /* OMAP4 specific register offsets */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0054-OMAP4-powerdomain-data-Fix-indentation.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0054-OMAP4-powerdomain-data-Fix-indentation.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0054-OMAP4-powerdomain-data-Fix-indentation.patch
@@ -0,0 +1,109 @@
+From 5e989827a7af4f126e5e6ecbcadf6b28eddfeb5f Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:05 -0600
+Subject: [PATCH 054/149] OMAP4: powerdomain data: Fix indentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Indent flags to be aligned with other fields.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+[paul@pwsan.com: split this patch from an earlier patch by Benoît;
+ edited commit message]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 18 +++++++++---------
+ 1 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index c4222c7..3a7e678 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -53,7 +53,7 @@ static struct powerdomain core_44xx_pwrdm = {
+ [3] = PWRSTS_ON, /* ducati_l2ram */
+ [4] = PWRSTS_ON, /* ducati_unicache */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* gfx_44xx_pwrdm: 3D accelerator power domain */
+@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* gfx_mem */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* abe_44xx_pwrdm: Audio back end power domain */
+@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
+ [0] = PWRSTS_ON, /* aessmem */
+ [1] = PWRSTS_ON, /* periphmem */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* dss_44xx_pwrdm: Display subsystem power domain */
+@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* dss_mem */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* tesla_44xx_pwrdm: Tesla processor power domain */
+@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
+ [1] = PWRSTS_ON, /* tesla_l1 */
+ [2] = PWRSTS_ON, /* tesla_l2 */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* wkup_44xx_pwrdm: Wake-up power domain */
+@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
+ [2] = PWRSTS_ON, /* tcm1_mem */
+ [3] = PWRSTS_ON, /* tcm2_mem */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* cam_44xx_pwrdm: Camera subsystem power domain */
+@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cam_mem */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
+@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* l3init_bank1 */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /* l4per_44xx_pwrdm: Target peripherals power domain */
+@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
+ [0] = PWRSTS_ON, /* nonretained_bank */
+ [1] = PWRSTS_ON, /* retained_bank */
+ },
+- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /*
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0055-OMAP4-cm-Remove-RESTORE-macros-to-avoid-access-from-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0055-OMAP4-cm-Remove-RESTORE-macros-to-avoid-access-from-.patch
--- /dev/null
@@ -0,0 +1,1523 @@
+From ead4460a58caf68513708f027f962e7dc16060a6 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:05 -0600
+Subject: [PATCH 055/149] OMAP4: cm: Remove RESTORE macros to avoid access from SW
+
+The restore part of the CM is an alias of some regular registers
+used only during the SAR restore to facilate the dma to write
+a contiguous set of registers.
+The registers should never be used by the SW, only the original
+register have to be used.
+
+Remove them from cmX_44xx.h files to avoid anybody to use them by
+mistake.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cm-regbits-44xx.h | 623 ++++++++++++++-------------------
+ arch/arm/mach-omap2/cm1_44xx.h | 36 --
+ arch/arm/mach-omap2/cm2_44xx.h | 50 ---
+ 3 files changed, 254 insertions(+), 455 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
+index 9d47a05..0e77945 100644
+--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
++++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
+@@ -22,22 +22,18 @@
+ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+ #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+
+-/*
+- * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
+- * CM_TESLA_DYNAMICDEP
+- */
++/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+ #define OMAP4430_ABE_DYNDEP_SHIFT 3
+ #define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
+
+ /*
+- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
++ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_ABE_STATDEP_SHIFT 3
+ #define OMAP4430_ABE_STATDEP_MASK (1 << 3)
+
+-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
++/* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
+ #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
+
+@@ -47,14 +43,13 @@
+
+ /*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
+- * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
+- * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
++ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
++ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
+ */
+ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
+ #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
+
+-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
++/* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
+ #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
+
+@@ -82,15 +77,15 @@
+ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
+ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
+ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
+ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
+
+@@ -110,31 +105,31 @@
+ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
+ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
+ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
+ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
+ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
+
+@@ -158,7 +153,7 @@
+ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
+ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
+
+@@ -170,55 +165,55 @@
+ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
+ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
+ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
+ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
+ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
+ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
+ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
+ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
+ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
+ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
+ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
+ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
+ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
+
+@@ -234,11 +229,11 @@
+ #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
+
+-/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
++/* Used by CM_L3_1_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
+
+-/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
++/* Used by CM_L3_2_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
+
+@@ -254,7 +249,7 @@
+ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
+
+@@ -262,7 +257,7 @@
+ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
+
+@@ -282,7 +277,7 @@
+ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
+
+-/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
++/* Used by CM_L4CFG_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
+
+@@ -290,11 +285,11 @@
+ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
+
+@@ -306,7 +301,7 @@
+ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
+ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
+
+-/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
++/* Used by CM_MPU_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
+
+@@ -314,43 +309,43 @@
+ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
+ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
+ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
+ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
+ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
+ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
+ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
+ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
+ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
+ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
+
+-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
++/* Used by CM_L4PER_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
+ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
+
+-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
++/* Used by CM_MEMIF_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
+
+@@ -378,27 +373,27 @@
+ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
+ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
+ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
+ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
+ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
+ #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
+ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
+
+@@ -406,11 +401,11 @@
+ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
+ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
+ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
+
+-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
++/* Used by CM_L3INIT_CLKSTCTRL */
+ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
+ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
+
+@@ -432,7 +427,7 @@
+
+ /*
+ * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
+- * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
++ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
+ */
+ #define OMAP4430_CLKSEL_0_0_SHIFT 0
+ #define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
+@@ -453,14 +448,11 @@
+ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
+ #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
+
+-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
++/* Used by CM_CLKSEL_CORE */
+ #define OMAP4430_CLKSEL_CORE_SHIFT 0
+ #define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
+
+-/*
+- * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+- * CM_SHADOW_FREQ_CONFIG2
+- */
++/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
+ #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
+
+@@ -484,18 +476,15 @@
+ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
+ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
+
+-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
++/* Used by CM_CLKSEL_CORE */
+ #define OMAP4430_CLKSEL_L3_SHIFT 4
+ #define OMAP4430_CLKSEL_L3_MASK (1 << 4)
+
+-/*
+- * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+- * CM_SHADOW_FREQ_CONFIG2
+- */
++/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
+ #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
+
+-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
++/* Used by CM_CLKSEL_CORE */
+ #define OMAP4430_CLKSEL_L4_SHIFT 8
+ #define OMAP4430_CLKSEL_L4_MASK (1 << 8)
+
+@@ -526,11 +515,11 @@
+ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
+ #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
+ #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
+ #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
+
+@@ -538,13 +527,10 @@
+ * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
+- * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
+- * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
+- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
+- * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
+- * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
+- * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+- * CM_WKUP_CLKSTCTRL
++ * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
++ * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
++ * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
++ * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
+ */
+ #define OMAP4430_CLKTRCTRL_SHIFT 0
+ #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
+@@ -561,10 +547,7 @@
+ #define OMAP4430_CUSTOM_SHIFT 6
+ #define OMAP4430_CUSTOM_MASK (0x3 << 6)
+
+-/*
+- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE
+- */
++/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_D2D_DYNDEP_SHIFT 18
+ #define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
+
+@@ -574,31 +557,29 @@
+
+ /*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+- * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
+- * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+- * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+- * CM_SSC_DELTAMSTEP_DPLL_USB
++ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
++ * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
++ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+ #define OMAP4430_DELTAMSTEP_SHIFT 0
+ #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+-#define OMAP4430_DLL_OVERRIDE_SHIFT 2
+-#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
++/* Used by CM_DLL_CTRL */
++#define OMAP4430_DLL_OVERRIDE_SHIFT 0
++#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
+
+-/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
+-#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0
+-#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0)
++/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
++#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
++#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG1 */
+ #define OMAP4430_DLL_RESET_SHIFT 3
+ #define OMAP4430_DLL_RESET_MASK (1 << 3)
+
+ /*
+- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+- * CM_CLKSEL_DPLL_USB
++ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
++ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
++ * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
+ */
+ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
+ #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
+@@ -607,28 +588,19 @@
+ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
+ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
+
+-/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
++/* Used by CM_CLKSEL_DPLL_CORE */
+ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
+ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
+
+-/*
+- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
+- */
++/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
+ #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
+
+-/*
+- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
+- */
++/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
+ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
+
+-/*
+- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
+- */
++/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
+ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
+
+@@ -637,9 +609,8 @@
+ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
+
+ /*
+- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
++ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
++ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
+ #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+@@ -649,9 +620,8 @@
+ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
+
+ /*
+- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
++ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
++ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
+ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
+@@ -661,29 +631,28 @@
+ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
+
+ /*
+- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
++ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
++ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ */
+ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
+ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG1 */
+ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
+ #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG1 */
+ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
+ #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG2 */
+ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
+ #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
+
+ /*
+- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
++ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
++ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
++ * CM_CLKSEL_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_DIV_SHIFT 0
+ #define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
+@@ -693,9 +662,8 @@
+ #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
+ #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+@@ -705,26 +673,25 @@
+ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+- * CM_CLKMODE_DPLL_USB
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+ #define OMAP4430_DPLL_EN_SHIFT 0
+ #define OMAP4430_DPLL_EN_MASK (0x7 << 0)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
+ #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
+
+ /*
+- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
++ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
++ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
++ * CM_CLKSEL_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_MULT_SHIFT 8
+ #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
+@@ -734,9 +701,9 @@
+ #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO
+ */
+ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11
+ #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
+@@ -746,55 +713,46 @@
+ #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+- * CM_CLKMODE_DPLL_USB
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13
+ #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+- * CM_CLKMODE_DPLL_USB
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
+ #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
+
+ /*
+- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+- * CM_CLKMODE_DPLL_USB
++ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
++ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
++ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+ #define OMAP4430_DPLL_SSC_EN_SHIFT 12
+ #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
+
+-/*
+- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+- */
++/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ #define OMAP4430_DSS_DYNDEP_SHIFT 8
+ #define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
+
+-/*
+- * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+- * CM_SDMA_STATICDEP_RESTORE
+- */
++/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+ #define OMAP4430_DSS_STATDEP_SHIFT 8
+ #define OMAP4430_DSS_STATDEP_MASK (1 << 8)
+
+-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
++/* Used by CM_L3_2_DYNAMICDEP */
+ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0
+ #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
+
+-/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
++/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+ #define OMAP4430_DUCATI_STATDEP_SHIFT 0
+ #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG1 */
+ #define OMAP4430_FREQ_UPDATE_SHIFT 0
+ #define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
+
+@@ -802,7 +760,7 @@
+ #define OMAP4430_FUNC_SHIFT 16
+ #define OMAP4430_FUNC_MASK (0xfff << 16)
+
+-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
++/* Used by CM_L3_2_DYNAMICDEP */
+ #define OMAP4430_GFX_DYNDEP_SHIFT 10
+ #define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
+
+@@ -810,119 +768,95 @@
+ #define OMAP4430_GFX_STATDEP_SHIFT 10
+ #define OMAP4430_GFX_STATDEP_MASK (1 << 10)
+
+-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
++/* Used by CM_SHADOW_FREQ_CONFIG2 */
+ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
+ #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
+
+ /*
+- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
++ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
++ * CM_DIV_M4_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
+ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
+
+ /*
+- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
++ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
++ * CM_DIV_M4_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
+ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
+
+ /*
+- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
++ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
++ * CM_DIV_M4_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
+ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
+
+ /*
+- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
++ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
++ * CM_DIV_M4_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
+ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
+
+ /*
+- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
++ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
++ * CM_DIV_M5_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
+ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
+
+ /*
+- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
++ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
++ * CM_DIV_M5_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
+ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
+
+ /*
+- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
++ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
++ * CM_DIV_M5_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
+ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
+
+ /*
+- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
++ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
++ * CM_DIV_M5_DPLL_PER
+ */
+ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
+ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
+
+-/*
+- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
+- */
++/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
+ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
+
+-/*
+- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
+- */
++/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
+ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
+
+-/*
+- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
+- */
++/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
+ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
+
+-/*
+- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
+- */
++/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
+ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
+
+-/*
+- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+- * CM_DIV_M7_DPLL_PER
+- */
++/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
+ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
+
+-/*
+- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+- * CM_DIV_M7_DPLL_PER
+- */
++/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
+ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
+
+-/*
+- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+- * CM_DIV_M7_DPLL_PER
+- */
++/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
+ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
+
+-/*
+- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+- * CM_DIV_M7_DPLL_PER
+- */
++/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
+ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
+
+@@ -934,8 +868,7 @@
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
++ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+@@ -944,30 +877,24 @@
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
++ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
++ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
++ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
++ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
++ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
++ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
++ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
++ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
++ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
++ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
++ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
++ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+@@ -983,166 +910,148 @@
+ #define OMAP4430_IDLEST_SHIFT 16
+ #define OMAP4430_IDLEST_MASK (0x3 << 16)
+
+-/*
+- * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
+- */
++/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_ISS_DYNDEP_SHIFT 9
+ #define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
+
+ /*
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_ISS_STATDEP_SHIFT 9
+ #define OMAP4430_ISS_STATDEP_MASK (1 << 9)
+
+-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
++/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2
+ #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
+
+ /*
+- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
+- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
++ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
++ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_IVAHD_STATDEP_SHIFT 2
+ #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
+
+-/*
+- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+- */
++/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7
+ #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
+
+ /*
+- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+- * CM_TESLA_STATICDEP
++ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
++ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L3INIT_STATDEP_SHIFT 7
+ #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
+
+ /*
+ * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
++ * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+ #define OMAP4430_L3_1_DYNDEP_SHIFT 5
+ #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
+
+ /*
+- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
++ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
++ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L3_1_STATDEP_SHIFT 5
+ #define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
+
+ /*
+- * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
+- * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
+- * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
+- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
++ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
++ * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
++ * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
++ * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
+ */
+ #define OMAP4430_L3_2_DYNDEP_SHIFT 6
+ #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
+
+ /*
+- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
++ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
++ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L3_2_STATDEP_SHIFT 6
+ #define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
+
+-/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
++/* Used by CM_L3_1_DYNAMICDEP */
+ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12
+ #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
+
+ /*
+- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
++ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L4CFG_STATDEP_SHIFT 12
+ #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
+
+-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
++/* Used by CM_L3_2_DYNAMICDEP */
+ #define OMAP4430_L4PER_DYNDEP_SHIFT 13
+ #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
+
+ /*
+- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
++ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L4PER_STATDEP_SHIFT 13
+ #define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
+
+-/*
+- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+- * CM_L4PER_DYNAMICDEP_RESTORE
+- */
++/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14
+ #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
+
+ /*
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
++ * CM_SDMA_STATICDEP
+ */
+ #define OMAP4430_L4SEC_STATDEP_SHIFT 14
+ #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
+
+-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
++/* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
+ #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
+
+ /*
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15
+ #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
+
+ /*
+- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
+- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
++ * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
++ * CM_MPU_DYNAMICDEP
+ */
+ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4
+ #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
+
+ /*
+- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
++ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
++ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
++ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ */
+ #define OMAP4430_MEMIF_STATDEP_SHIFT 4
+ #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
+
+ /*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+- * CM_SSC_MODFREQDIV_DPLL_USB
++ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
++ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
++ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
+ #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
+
+ /*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+- * CM_SSC_MODFREQDIV_DPLL_USB
++ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
++ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
++ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
+ #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
+@@ -1155,8 +1064,7 @@
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
++ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+@@ -1165,30 +1073,24 @@
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
++ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
++ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
++ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
++ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
++ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
++ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
++ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
++ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
++ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
++ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
++ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
++ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+@@ -1221,11 +1123,9 @@
+ #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
+
+ /*
+- * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
++ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
++ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
++ * CM_WKUP_GPIO1_CLKCTRL
+ */
+ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
+ #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
+@@ -1254,23 +1154,23 @@
+ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
+ #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
+ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
+ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
+ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
+ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
+ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
+
+@@ -1306,27 +1206,27 @@
+ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
+ #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
+
+-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
+ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
+
+-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
+ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
+
+-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
+ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
+ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
+ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
+
+-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
+ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
+
+@@ -1374,7 +1274,7 @@
+ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
+ #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
+
+-/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
++/* Used by CM_DYN_DEP_PRESCAL */
+ #define OMAP4430_PRESCAL_SHIFT 0
+ #define OMAP4430_PRESCAL_MASK (0x3f << 0)
+
+@@ -1382,10 +1282,7 @@
+ #define OMAP4430_R_RTL_SHIFT 11
+ #define OMAP4430_R_RTL_MASK (0x1f << 11)
+
+-/*
+- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+- */
++/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
+ #define OMAP4430_SAR_MODE_SHIFT 4
+ #define OMAP4430_SAR_MODE_MASK (1 << 4)
+
+@@ -1397,7 +1294,7 @@
+ #define OMAP4430_SCHEME_SHIFT 30
+ #define OMAP4430_SCHEME_MASK (0x3 << 30)
+
+-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
++/* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_SDMA_DYNDEP_SHIFT 11
+ #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
+
+@@ -1417,10 +1314,10 @@
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+- * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+- * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
++ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
++ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
++ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
++ * CM_TESLA_TESLA_CLKCTRL
+ */
+ #define OMAP4430_STBYST_SHIFT 18
+ #define OMAP4430_STBYST_MASK (1 << 18)
+@@ -1438,17 +1335,13 @@
+ #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
+
+ /*
+- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
++ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
++ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ */
+ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
+ #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
+
+-/*
+- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
+- */
++/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
+ #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
+
+@@ -1457,30 +1350,24 @@
+ #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
+
+ /*
+- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
++ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
++ * CM_DIV_M4_DPLL_PER
+ */
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
+
+ /*
+- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
++ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
++ * CM_DIV_M5_DPLL_PER
+ */
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
+
+-/*
+- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
+- */
++/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
+
+-/*
+- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+- * CM_DIV_M7_DPLL_PER
+- */
++/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
+ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
+
+@@ -1496,7 +1383,7 @@
+ #define OMAP4430_SYS_CLKSEL_SHIFT 0
+ #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
+
+-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
++/* Used by CM_L4CFG_DYNAMICDEP */
+ #define OMAP4430_TESLA_DYNDEP_SHIFT 1
+ #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
+
+@@ -1505,11 +1392,9 @@
+ #define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
+
+ /*
+- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
+- * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
+- * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+- * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
++ * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
++ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
++ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+ #define OMAP4430_WINDOWSIZE_SHIFT 24
+ #define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
+diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
+index fc649f5..1bc00dc 100644
+--- a/arch/arm/mach-omap2/cm1_44xx.h
++++ b/arch/arm/mach-omap2/cm1_44xx.h
+@@ -217,42 +217,6 @@
+ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
+ #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
+
+-/* CM1.RESTORE_CM1 register offsets */
+-#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
+-#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
+-#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
+-#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
+-#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
+-#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
+-#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
+-#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
+-#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
+-#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
+-#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
+-#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
+-#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
+-#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
+-#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
+-#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
+-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
+-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
+-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
+-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
+-#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
+-#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
+-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
+-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
+-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
+-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
+-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
+-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
+-#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
+-#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
+-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
+-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
+-#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
+-#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
+-
+ /* Function prototypes */
+ extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+ extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
+index 8036a16..b9de72d 100644
+--- a/arch/arm/mach-omap2/cm2_44xx.h
++++ b/arch/arm/mach-omap2/cm2_44xx.h
+@@ -449,56 +449,6 @@
+ #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
+ #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
+
+-/* CM2.RESTORE_CM2 register offsets */
+-#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
+-#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
+-#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
+-#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
+-#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
+-#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
+-#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
+-#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
+-#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
+-#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
+-#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
+-#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
+-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
+-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
+-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
+-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
+-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
+-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
+-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
+-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
+-#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
+-#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
+-#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
+-#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
+-#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
+-#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
+-#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
+-#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
+-#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
+-#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
+-#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
+-#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
+-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
+-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
+-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
+-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
+-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
+-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
+-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
+-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
+-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
+-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
+-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
+-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
+-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
+-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
+-#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
+-#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
+-
+ /* Function prototypes */
+ extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+ extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0056-OMAP4-prcm_mpu-Fix-indent-in-few-macros.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0056-OMAP4-prcm_mpu-Fix-indent-in-few-macros.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0056-OMAP4-prcm_mpu-Fix-indent-in-few-macros.patch
@@ -0,0 +1,111 @@
+From 947ba5ed8ddd22fded6dd2a8a16741a43742857b Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:06 -0600
+Subject: [PATCH 056/149] OMAP4: prcm_mpu: Fix indent in few macros
+
+Some maros were not well aligned. Re-align them.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/prcm_mpu44xx.h | 69 +++++++++++++++++------------------
+ 1 files changed, 34 insertions(+), 35 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
+index d22d1b4..8a6e250 100644
+--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
++++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
+@@ -31,7 +31,6 @@
+ OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
+
+ /* PRCM_MPU instances */
+-
+ #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
+ #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
+ #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
+@@ -52,46 +51,46 @@
+ */
+
+ /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
+-#define OMAP4_REVISION_PRCM_OFFSET 0x0000
+-#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
++#define OMAP4_REVISION_PRCM_OFFSET 0x0000
++#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
+
+ /* PRCM_MPU.DEVICE_PRM register offsets */
+-#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
+-#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
+-#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
+-#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
++#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
++#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
++#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
++#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
+
+ /* PRCM_MPU.CPU0 register offsets */
+-#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
+-#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
+-#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
+-#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
+-#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
+-#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
+-#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
+-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
+-#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
+-#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
+-#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
+-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
+-#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
+-#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
++#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
++#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
++#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
++#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
++#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
++#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
++#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
++#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
++#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
++#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
++#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
++#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
++#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
++#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
+
+ /* PRCM_MPU.CPU1 register offsets */
+-#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
+-#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
+-#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
+-#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
+-#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
+-#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
+-#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
+-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
+-#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
+-#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
+-#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
+-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
+-#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
+-#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
++#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
++#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
++#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
++#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
++#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
++#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
++#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
++#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
++#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
++#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
++#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
++#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
++#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
++#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
+
+ /* Function prototypes */
+ # ifndef __ASSEMBLER__
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0057-OMAP4-clockdomain-data-Fix-data-order-and-wrong-name.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0057-OMAP4-clockdomain-data-Fix-data-order-and-wrong-name.patch
--- /dev/null
@@ -0,0 +1,294 @@
+From 80cd994630a18bc3e6854fec1d47c837ebd97082 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 19:15:06 -0600
+Subject: [PATCH 057/149] OMAP4: clockdomain data: Fix data order and wrong name
+
+MPUSS was renamed MPU and L3_D2D D2D.
+The rename will slightly change the order of the structure
+and thus generate some structures moves.
+
+Add a comment and remove a comma.
+
+Update Copyright for TI and Nokia and add back Paul
+in the author list.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 124 ++++++++++++++-------------
+ 1 files changed, 63 insertions(+), 61 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index a607ec1..66090f2 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -1,11 +1,12 @@
+ /*
+ * OMAP4 Clock domains framework
+ *
+- * Copyright (C) 2009 Texas Instruments, Inc.
+- * Copyright (C) 2009 Nokia Corporation
++ * Copyright (C) 2009-2011 Texas Instruments, Inc.
++ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
++ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+@@ -32,7 +33,7 @@
+
+ /* Static Dependencies for OMAP4 Clock Domains */
+
+-static struct clkdm_dep ducati_wkup_sleep_deps[] = {
++static struct clkdm_dep d2d_wkup_sleep_deps[] = {
+ {
+ .clkdm_name = "abe_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_dss_clkdm",
++ .clkdm_name = "l3_emif_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_emif_clkdm",
++ .clkdm_name = "l3_init_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_gfx_clkdm",
++ .clkdm_name = "l4_cfg_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_init_clkdm",
++ .clkdm_name = "l4_per_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
++ { NULL },
++};
++
++static struct clkdm_dep ducati_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "l4_cfg_clkdm",
++ .clkdm_name = "abe_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l4_per_clkdm",
++ .clkdm_name = "ivahd_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l4_secure_clkdm",
++ .clkdm_name = "l3_1_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l4_wkup_clkdm",
++ .clkdm_name = "l3_2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "tesla_clkdm",
++ .clkdm_name = "l3_dss_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+- { NULL },
+-};
+-
+-static struct clkdm_dep iss_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "ivahd_clkdm",
++ .clkdm_name = "l3_emif_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_1_clkdm",
++ .clkdm_name = "l3_gfx_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_emif_clkdm",
++ .clkdm_name = "l3_init_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+- { NULL },
+-};
+-
+-static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "l3_1_clkdm",
++ .clkdm_name = "l4_cfg_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_emif_clkdm",
++ .clkdm_name = "l4_per_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+- { NULL },
+-};
+-
+-static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "abe_clkdm",
++ .clkdm_name = "l4_secure_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "ivahd_clkdm",
++ .clkdm_name = "l4_wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_1_clkdm",
++ .clkdm_name = "tesla_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
++ { NULL },
++};
++
++static struct clkdm_dep iss_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "l3_2_clkdm",
++ .clkdm_name = "ivahd_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_emif_clkdm",
++ .clkdm_name = "l3_1_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l3_init_clkdm",
++ .clkdm_name = "l3_emif_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
++ { NULL },
++};
++
++static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
+ {
+- .clkdm_name = "l4_cfg_clkdm",
++ .clkdm_name = "l3_1_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ {
+- .clkdm_name = "l4_per_clkdm",
++ .clkdm_name = "l3_emif_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+ },
+ { NULL },
+@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
+ { NULL },
+ };
+
+-static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
++static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+ {
+ .clkdm_name = "abe_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-static struct clockdomain mpuss_44xx_clkdm = {
+- .name = "mpuss_clkdm",
+- .pwrdm = { .name = "mpu_pwrdm" },
+- .prcm_partition = OMAP4430_CM1_PARTITION,
+- .cm_inst = OMAP4430_CM1_MPU_INST,
+- .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
+- .wkdep_srcs = mpuss_wkup_sleep_deps,
+- .sleepdep_srcs = mpuss_wkup_sleep_deps,
++static struct clockdomain d2d_44xx_clkdm = {
++ .name = "d2d_clkdm",
++ .pwrdm = { .name = "core_pwrdm" },
++ .prcm_partition = OMAP4430_CM2_PARTITION,
++ .cm_inst = OMAP4430_CM2_CORE_INST,
++ .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
++ .wkdep_srcs = d2d_wkup_sleep_deps,
++ .sleepdep_srcs = d2d_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
++static struct clockdomain mpu_44xx_clkdm = {
++ .name = "mpu_clkdm",
++ .pwrdm = { .name = "mpu_pwrdm" },
++ .prcm_partition = OMAP4430_CM1_PARTITION,
++ .cm_inst = OMAP4430_CM1_MPU_INST,
++ .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
++ .wkdep_srcs = mpu_wkup_sleep_deps,
++ .sleepdep_srcs = mpu_wkup_sleep_deps,
++ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
+ static struct clockdomain l3_2_44xx_clkdm = {
+ .name = "l3_2_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+-static struct clockdomain l3_d2d_44xx_clkdm = {
+- .name = "l3_d2d_clkdm",
+- .pwrdm = { .name = "core_pwrdm" },
+- .prcm_partition = OMAP4430_CM2_PARTITION,
+- .cm_inst = OMAP4430_CM2_CORE_INST,
+- .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
+- .wkdep_srcs = l3_d2d_wkup_sleep_deps,
+- .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
+- .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+-};
+-
+ static struct clockdomain iss_44xx_clkdm = {
+ .name = "iss_clkdm",
+ .pwrdm = { .name = "cam_pwrdm" },
+@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
++/* As clockdomains are added or removed above, this list must also be changed */
+ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+ &l4_cefuse_44xx_clkdm,
+ &l4_cfg_44xx_clkdm,
+@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+ &abe_44xx_clkdm,
+ &l3_instr_44xx_clkdm,
+ &l3_init_44xx_clkdm,
+- &mpuss_44xx_clkdm,
++ &d2d_44xx_clkdm,
+ &mpu0_44xx_clkdm,
+ &mpu1_44xx_clkdm,
+ &l3_emif_44xx_clkdm,
+ &l4_ao_44xx_clkdm,
+ &ducati_44xx_clkdm,
++ &mpu_44xx_clkdm,
+ &l3_2_44xx_clkdm,
+ &l3_1_44xx_clkdm,
+- &l3_d2d_44xx_clkdm,
+ &iss_44xx_clkdm,
+ &l3_dss_44xx_clkdm,
+ &l4_wkup_44xx_clkdm,
+ &emu_sys_44xx_clkdm,
+ &l3_dma_44xx_clkdm,
+- NULL,
++ NULL
+ };
+
+ void __init omap44xx_clockdomains_init(void)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0058-OMAP-omap_device-replace-_find_by_pdev-with-to_omap_.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0058-OMAP-omap_device-replace-_find_by_pdev-with-to_omap_.patch
--- /dev/null
@@ -0,0 +1,84 @@
+From 2033d2c00170e64c9d634cafaf8bd1cf1a5f3ee1 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Sat, 9 Jul 2011 19:15:20 -0600
+Subject: [PATCH 058/149] OMAP: omap_device: replace _find_by_pdev() with to_omap_device()
+
+The omap_device layer currently has two ways of getting an omap_device
+pointer from a platform_device pointer.
+
+Replace current usage of _find_by_pdev() with to_omap_device() since
+to_omap_device() is more familiar to the existing to_platform_device()
+used when getting a platform_device pointer from a struct device pointer.
+
+Cc: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Reviewed-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/omap_device.c | 15 +++++----------
+ 1 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
+index 49fc0df..c8b9cd1 100644
+--- a/arch/arm/plat-omap/omap_device.c
++++ b/arch/arm/plat-omap/omap_device.c
+@@ -236,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
+ return 0;
+ }
+
+-static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+-{
+- return container_of(pdev, struct omap_device, pdev);
+-}
+-
+ /**
+ * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * @od: struct omap_device *od
+@@ -316,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
+ struct omap_device *od;
+ u32 ret = 0;
+
+- od = _find_by_pdev(pdev);
++ od = to_omap_device(pdev);
+
+ if (od->hwmods_cnt)
+ ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
+@@ -611,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev)
+ int ret;
+ struct omap_device *od;
+
+- od = _find_by_pdev(pdev);
++ od = to_omap_device(pdev);
+
+ if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+ WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+@@ -650,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev)
+ int ret;
+ struct omap_device *od;
+
+- od = _find_by_pdev(pdev);
++ od = to_omap_device(pdev);
+
+ if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
+ WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+@@ -681,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev)
+ int ret, i;
+ struct omap_device *od;
+
+- od = _find_by_pdev(pdev);
++ od = to_omap_device(pdev);
+
+ if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
+ od->_state != OMAP_DEVICE_STATE_IDLE) {
+@@ -722,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
+ int ret = -EINVAL;
+ struct omap_device *od;
+
+- od = _find_by_pdev(pdev);
++ od = to_omap_device(pdev);
+
+ if (new_wakeup_lat_limit == od->dev_wakeup_lat)
+ return 0;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0059-OMAP-PM-remove-OMAP_PM_NONE-config-option.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0059-OMAP-PM-remove-OMAP_PM_NONE-config-option.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0059-OMAP-PM-remove-OMAP_PM_NONE-config-option.patch
@@ -0,0 +1,63 @@
+From f0b12908ee88cda0e51a3b416387cc6d7605b809 Mon Sep 17 00:00:00 2001
+From: Jean Pihet <jean.pihet@newoldbits.com>
+Date: Sat, 9 Jul 2011 19:15:41 -0600
+Subject: [PATCH 059/149] OMAP PM: remove OMAP_PM_NONE config option
+
+The current code base is not linking with the OMAP_PM_NONE
+option set.
+Since the option OMAP_PM_NOOP provides a no-op/debug layer,
+OMAP_PM_NONE can be removed.
+OMAP_PM_NOOP is enabled by default by Kconfig.
+
+Signed-off-by: Jean Pihet <j-pihet@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/Kconfig | 3 ---
+ arch/arm/plat-omap/include/plat/omap-pm.h | 8 --------
+ 2 files changed, 0 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index 49a4c75..6e6735f 100644
+--- a/arch/arm/plat-omap/Kconfig
++++ b/arch/arm/plat-omap/Kconfig
+@@ -211,9 +211,6 @@ choice
+ depends on ARCH_OMAP
+ default OMAP_PM_NOOP
+
+-config OMAP_PM_NONE
+- bool "No PM layer"
+-
+ config OMAP_PM_NOOP
+ bool "No-op/debug PM layer"
+
+diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
+index c0a7520..0840df8 100644
+--- a/arch/arm/plat-omap/include/plat/omap-pm.h
++++ b/arch/arm/plat-omap/include/plat/omap-pm.h
+@@ -40,11 +40,7 @@
+ * framework starts. The "_if_" is to avoid name collisions with the
+ * PM idle-loop code.
+ */
+-#ifdef CONFIG_OMAP_PM_NONE
+-#define omap_pm_if_early_init() 0
+-#else
+ int __init omap_pm_if_early_init(void);
+-#endif
+
+ /**
+ * omap_pm_if_init - OMAP PM init code called after clock fw init
+@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
+ * The main initialization code. OPP tables are passed in here. The
+ * "_if_" is to avoid name collisions with the PM idle-loop code.
+ */
+-#ifdef CONFIG_OMAP_PM_NONE
+-#define omap_pm_if_init() 0
+-#else
+ int __init omap_pm_if_init(void);
+-#endif
+
+ /**
+ * omap_pm_if_exit - OMAP PM exit code
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0060-OMAP4-clock-data-Remove-McASP2-McASP3-and-MMC6-clock.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0060-OMAP4-clock-data-Remove-McASP2-McASP3-and-MMC6-clock.patch
--- /dev/null
@@ -0,0 +1,178 @@
+From a5224876877da3dce7971e82d89a58d58f4917fb Mon Sep 17 00:00:00 2001
+From: Jon Hunter <jon-hunter@ti.com>
+Date: Sat, 9 Jul 2011 19:14:47 -0600
+Subject: [PATCH 060/149] OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocks
+
+McASP2, 3 and MMC6 modules are not present in the OMAP4 family.
+Remove the fclk and the clksel related to these nodes.
+Rename the references that were potentially re-used in order nodes.
+
+Remove related macros in prcm header files.
+
+Update TI copyright date.
+
+Signed-off-by: Jon Hunter <jon-hunter@ti.com>
+[b-cousson@ti.com: Update the patch according to autogen output]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+[paul@pwsan.com: split PRCM data changes into a separate patch]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 86 ++++++++++++---------------------
+ 1 files changed, 31 insertions(+), 55 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 8307c9e..96bc668 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -1170,19 +1170,6 @@ static struct clk func_96m_fclk = {
+ .set_rate = &omap2_clksel_set_rate,
+ };
+
+-static const struct clksel hsmmc6_fclk_sel[] = {
+- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+- { .parent = NULL },
+-};
+-
+-static struct clk hsmmc6_fclk = {
+- .name = "hsmmc6_fclk",
+- .parent = &func_64m_fclk,
+- .ops = &clkops_null,
+- .recalc = &followparent_recalc,
+-};
+-
+ static const struct clksel_rate div2_1to8_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+ { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+@@ -1265,6 +1252,21 @@ static struct clk l4_wkup_clk_mux_ck = {
+ .recalc = &omap2_clksel_recalc,
+ };
+
++static struct clk ocp_abe_iclk = {
++ .name = "ocp_abe_iclk",
++ .parent = &aess_fclk,
++ .ops = &clkops_null,
++ .recalc = &followparent_recalc,
++};
++
++static struct clk per_abe_24m_fclk = {
++ .name = "per_abe_24m_fclk",
++ .parent = &dpll_abe_m2_ck,
++ .ops = &clkops_null,
++ .fixed_div = 4,
++ .recalc = &omap_fixed_divisor_recalc,
++};
++
+ static const struct clksel per_abe_nc_fclk_div[] = {
+ { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
+ { .parent = NULL },
+@@ -1282,41 +1284,6 @@ static struct clk per_abe_nc_fclk = {
+ .set_rate = &omap2_clksel_set_rate,
+ };
+
+-static const struct clksel mcasp2_fclk_sel[] = {
+- { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+- { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+- { .parent = NULL },
+-};
+-
+-static struct clk mcasp2_fclk = {
+- .name = "mcasp2_fclk",
+- .parent = &func_96m_fclk,
+- .ops = &clkops_null,
+- .recalc = &followparent_recalc,
+-};
+-
+-static struct clk mcasp3_fclk = {
+- .name = "mcasp3_fclk",
+- .parent = &func_96m_fclk,
+- .ops = &clkops_null,
+- .recalc = &followparent_recalc,
+-};
+-
+-static struct clk ocp_abe_iclk = {
+- .name = "ocp_abe_iclk",
+- .parent = &aess_fclk,
+- .ops = &clkops_null,
+- .recalc = &followparent_recalc,
+-};
+-
+-static struct clk per_abe_24m_fclk = {
+- .name = "per_abe_24m_fclk",
+- .parent = &dpll_abe_m2_ck,
+- .ops = &clkops_null,
+- .fixed_div = 4,
+- .recalc = &omap_fixed_divisor_recalc,
+-};
+-
+ static const struct clksel pmd_stm_clock_mux_sel[] = {
+ { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
+@@ -1996,10 +1963,16 @@ static struct clk mcbsp3_fck = {
+ .clkdm_name = "abe_clkdm",
+ };
+
++static const struct clksel mcbsp4_sync_mux_sel[] = {
++ { .parent = &func_96m_fclk, .rates = div_1_0_rates },
++ { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
++ { .parent = NULL },
++};
++
+ static struct clk mcbsp4_sync_mux_ck = {
+ .name = "mcbsp4_sync_mux_ck",
+ .parent = &func_96m_fclk,
+- .clksel = mcasp2_fclk_sel,
++ .clksel = mcbsp4_sync_mux_sel,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+ .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+@@ -2078,11 +2051,17 @@ static struct clk mcspi4_fck = {
+ .recalc = &followparent_recalc,
+ };
+
++static const struct clksel hsmmc1_fclk_sel[] = {
++ { .parent = &func_64m_fclk, .rates = div_1_0_rates },
++ { .parent = &func_96m_fclk, .rates = div_1_1_rates },
++ { .parent = NULL },
++};
++
+ /* Merged hsmmc1_fclk into mmc1 */
+ static struct clk mmc1_fck = {
+ .name = "mmc1_fck",
+ .parent = &func_64m_fclk,
+- .clksel = hsmmc6_fclk_sel,
++ .clksel = hsmmc1_fclk_sel,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+ .clksel_mask = OMAP4430_CLKSEL_MASK,
+@@ -2097,7 +2076,7 @@ static struct clk mmc1_fck = {
+ static struct clk mmc2_fck = {
+ .name = "mmc2_fck",
+ .parent = &func_64m_fclk,
+- .clksel = hsmmc6_fclk_sel,
++ .clksel = hsmmc1_fclk_sel,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+ .clksel_mask = OMAP4430_CLKSEL_MASK,
+@@ -3094,17 +3073,14 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
+ CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
+ CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
+- CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
+ CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
+ CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
+ CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
+ CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
+ CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
+- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
+- CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
+- CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
+ CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
+ CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
++ CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
+ CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
+ CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
+ CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0061-OMAP4-clock-data-Remove-UNIPRO-clock-nodes.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0061-OMAP4-clock-data-Remove-UNIPRO-clock-nodes.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0061-OMAP4-clock-data-Remove-UNIPRO-clock-nodes.patch
@@ -0,0 +1,99 @@
+From 12b5876bb1ee9c2bc2ba266c759358235d3cd2bc Mon Sep 17 00:00:00 2001
+From: Jon Hunter <jon-hunter@ti.com>
+Date: Sat, 9 Jul 2011 19:14:47 -0600
+Subject: [PATCH 061/149] OMAP4: clock data: Remove UNIPRO clock nodes
+
+UNIPRO was removed from OMAP4 devices from ES2.0 onwards.
+Since this IP was anyway non-functional and not supported,
+it is best to remove it completely.
+
+Signed-off-by: Jon Hunter <jon-hunter@ti.com>
+[b-cousson@ti.com: Update the changelog]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+[paul@pwsan.com: split PRCM header file changes into a separate patch]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 60 ----------------------------------
+ 1 files changed, 0 insertions(+), 60 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 96bc668..044df38 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
+ .set_rate = &omap2_clksel_set_rate,
+ };
+
+-/* DPLL_UNIPRO */
+-static struct dpll_data dpll_unipro_dd = {
+- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
+- .clk_bypass = &sys_clkin_ck,
+- .clk_ref = &sys_clkin_ck,
+- .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
+- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
+- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
+- .mult_mask = OMAP4430_DPLL_MULT_MASK,
+- .div1_mask = OMAP4430_DPLL_DIV_MASK,
+- .enable_mask = OMAP4430_DPLL_EN_MASK,
+- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
+- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
+- .max_multiplier = 2047,
+- .max_divider = 128,
+- .min_divider = 1,
+-};
+-
+-
+-static struct clk dpll_unipro_ck = {
+- .name = "dpll_unipro_ck",
+- .parent = &sys_clkin_ck,
+- .dpll_data = &dpll_unipro_dd,
+- .init = &omap2_init_dpll_parent,
+- .ops = &clkops_omap3_noncore_dpll_ops,
+- .recalc = &omap3_dpll_recalc,
+- .round_rate = &omap2_dpll_round_rate,
+- .set_rate = &omap3_noncore_dpll_set_rate,
+-};
+-
+-static struct clk dpll_unipro_x2_ck = {
+- .name = "dpll_unipro_x2_ck",
+- .parent = &dpll_unipro_ck,
+- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+- .flags = CLOCK_CLKOUTX2,
+- .ops = &clkops_omap4_dpllmx_ops,
+- .recalc = &omap3_clkoutx2_recalc,
+-};
+-
+-static const struct clksel dpll_unipro_m2x2_div[] = {
+- { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
+- { .parent = NULL },
+-};
+-
+-static struct clk dpll_unipro_m2x2_ck = {
+- .name = "dpll_unipro_m2x2_ck",
+- .parent = &dpll_unipro_x2_ck,
+- .clksel = dpll_unipro_m2x2_div,
+- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+- .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_omap4_dpllmx_ops,
+- .recalc = &omap2_clksel_recalc,
+- .round_rate = &omap2_clksel_round_rate,
+- .set_rate = &omap2_clksel_set_rate,
+-};
+-
+ static struct clk usb_hs_clk_div_ck = {
+ .name = "usb_hs_clk_div_ck",
+ .parent = &dpll_abe_m3x2_ck,
+@@ -3058,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
+- CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
+- CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
+- CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
+ CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
+ CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
+ CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0062-OMAP4-hwmod-data-Modify-DSS-opt-clocks.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0062-OMAP4-hwmod-data-Modify-DSS-opt-clocks.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0062-OMAP4-hwmod-data-Modify-DSS-opt-clocks.patch
@@ -0,0 +1,153 @@
+From 884e583d87b2acda00edb3bfb96f2d7516bd58f6 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Sat, 9 Jul 2011 20:39:44 -0600
+Subject: [PATCH 062/149] OMAP4: hwmod data: Modify DSS opt clocks
+
+Add missing DSS optional clocks to HWMOD data for OMAP4xxx.
+
+Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+[b-cousson@ti.com: Remove a comment and update the subject]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
+[paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's
+ request]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 8 +++---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 33 ++++++++++++++++++++++++++++
+ 2 files changed, 37 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 044df38..7a0b112 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3032,10 +3032,10 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
+ CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
+- CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
+- CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
+- CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
+- CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
++ CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
++ CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
++ CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
++ CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
+ CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
+ CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
+ CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index e011437..a7fbe5c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -1267,9 +1267,16 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
+ &omap44xx_l4_per__dss_dispc,
+ };
+
++static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
++ { .role = "sys_clk", .clk = "dss_sys_clk" },
++ { .role = "tv_clk", .clk = "dss_tv_clk" },
++ { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
++};
++
+ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap44xx_dispc_hwmod_class,
++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+ .main_clk = "dss_fck",
+@@ -1278,6 +1285,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
++ .opt_clks = dss_dispc_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
+ .slaves = omap44xx_dss_dispc_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -1358,6 +1367,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
+ &omap44xx_l4_per__dss_dsi1,
+ };
+
++static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
++ { .role = "sys_clk", .clk = "dss_sys_clk" },
++};
++
+ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap44xx_dsi_hwmod_class,
+@@ -1369,6 +1382,8 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
++ .opt_clks = dss_dsi1_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
+ .slaves = omap44xx_dss_dsi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -1428,6 +1443,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
+ &omap44xx_l4_per__dss_dsi2,
+ };
+
++static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
++ { .role = "sys_clk", .clk = "dss_sys_clk" },
++};
++
+ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .name = "dss_dsi2",
+ .class = &omap44xx_dsi_hwmod_class,
+@@ -1439,6 +1458,8 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
++ .opt_clks = dss_dsi2_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
+ .slaves = omap44xx_dss_dsi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -1518,6 +1539,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
+ &omap44xx_l4_per__dss_hdmi,
+ };
+
++static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
++ { .role = "sys_clk", .clk = "dss_sys_clk" },
++};
++
+ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &omap44xx_hdmi_hwmod_class,
+@@ -1529,6 +1554,8 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
++ .opt_clks = dss_hdmi_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
+ .slaves = omap44xx_dss_hdmi_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -1603,6 +1630,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
+ &omap44xx_l4_per__dss_rfbi,
+ };
+
++static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
++ { .role = "ick", .clk = "dss_fck" },
++};
++
+ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap44xx_rfbi_hwmod_class,
+@@ -1613,6 +1644,8 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
++ .opt_clks = dss_rfbi_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
+ .slaves = omap44xx_dss_rfbi_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0063-OMAP2-PM-Initialise-sleep_switch-to-a-non-valid-valu.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0063-OMAP2-PM-Initialise-sleep_switch-to-a-non-valid-valu.patch
--- /dev/null
@@ -0,0 +1,39 @@
+From 65037bbeca82d31f8d9d6bd7183a16a0021acddd Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Sat, 9 Jul 2011 20:42:11 -0600
+Subject: [PATCH 063/149] OMAP2+: PM: Initialise sleep_switch to a non-valid value
+
+sleep_switch which is initialised to 0 in omap_set_pwrdm_state
+happens to be a valid sleep_switch type (FORCEWAKEUP_SWITCH)
+which are defined as:
+
+ #define FORCEWAKEUP_SWITCH 0
+ #define LOWPOWERSTATE_SWITCH 1
+
+This causes the function to wrongly program some clock domains
+even when the Powerdomain is in ON state.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Acked-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/pm.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 49486f5..d48813f 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -106,7 +106,7 @@ static void omap2_init_processor_devices(void)
+ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ {
+ u32 cur_state;
+- int sleep_switch = 0;
++ int sleep_switch = -1;
+ int ret = 0;
+
+ if (pwrdm == NULL || IS_ERR(pwrdm))
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0064-OMAP4-powerdomain-data-Fix-core-mem-states-and-missi.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0064-OMAP4-powerdomain-data-Fix-core-mem-states-and-missi.patch
--- /dev/null
@@ -0,0 +1,68 @@
+From 1b1789929e1329fe61d65c142890045ab1c38d56 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sat, 9 Jul 2011 20:42:11 -0600
+Subject: [PATCH 064/149] OMAP4: powerdomain data: Fix core mem states and missing cefuse flag
+
+Since ES2.0, the core ocmram does not support a different state
+than the main power domain anymore during both ON and RET power
+domain state.
+Since PM is not supported at all in ES1.0, update the common
+structure.
+
+LOWPOWERSTATECHANGE is supported by the cefuse power domain but
+the flag was missing.
+Add the PWRDM_HAS_LOWPOWERSTATECHANGE in flags field.
+
+Update the TI copyright date to 2011.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+[paul@pwsan.com: moved the indentation changes to a different patch set]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 7 ++++---
+ 1 files changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index 3a7e678..8f46e7d 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -1,7 +1,7 @@
+ /*
+ * OMAP4 Power domains framework
+ *
+- * Copyright (C) 2009-2010 Texas Instruments, Inc.
++ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+@@ -41,14 +41,14 @@ static struct powerdomain core_44xx_pwrdm = {
+ .banks = 5,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF, /* core_nret_bank */
+- [1] = PWRSTS_OFF_RET, /* core_ocmram */
++ [1] = PWRSTS_RET, /* core_ocmram */
+ [2] = PWRSTS_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ducati_unicache */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* core_nret_bank */
+- [1] = PWRSTS_OFF_RET, /* core_ocmram */
++ [1] = PWRSTS_ON, /* core_ocmram */
+ [2] = PWRSTS_ON, /* core_other_bank */
+ [3] = PWRSTS_ON, /* ducati_l2ram */
+ [4] = PWRSTS_ON, /* ducati_unicache */
+@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_ON,
++ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+
+ /*
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0065-OMAP4-clock-data-Keep-GPMC-clocks-always-enabled-and.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0065-OMAP4-clock-data-Keep-GPMC-clocks-always-enabled-and.patch
--- /dev/null
@@ -0,0 +1,45 @@
+From bee17d851a4354f1b5fed60e5464b42e5e4cc31c Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sat, 9 Jul 2011 20:42:59 -0600
+Subject: [PATCH 065/149] OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed
+
+On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by
+L3 interconnect. Because of CPU speculative nature, such accesses are
+possible which can lead to indirect access to GPMC and if it's clock is
+not running, it can result in hang/abort on the platform.
+
+Above makes access to GPMC unpredictable during the execution, so it's
+module mode needs to be kept under hardware control instead of software
+control.
+Since the auto gating is supported for GPMC, there isn't any power impact
+because of this change.
+
+The issue was un-covered with security middleware running along with HLOS.
+In this case GPMC had a valid MMU descriptor on secure side where as HLOS
+didn't map the GMPC because it isn't being used.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+[b-cousson@ti.com: Update subject and fix typos in the changelog]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 7a0b112..2578820 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -1605,6 +1605,7 @@ static struct clk gpmc_ick = {
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
+ .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
++ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "l3_2_clkdm",
+ .parent = &l3_div_ck,
+ .recalc = &followparent_recalc,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0066-OMAP4-powerdomain-data-Remove-unsupported-MPU-powerd.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0066-OMAP4-powerdomain-data-Remove-unsupported-MPU-powerd.patch
--- /dev/null
@@ -0,0 +1,44 @@
+From 7ea06e2b39c9e51734c6c8b542a823c3698ad1b5 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sat, 9 Jul 2011 20:42:59 -0600
+Subject: [PATCH 066/149] OMAP4: powerdomain data: Remove unsupported MPU powerdomain state
+
+On OMAP4430 devices, because of boot ROM code bug, MPU OFF state can't
+be attempted independently. When coming out of MPU OFF state, ROM code
+disables the clocks of IVAHD, TESLA which is not desirable. Hence the
+MPU OFF state is not usable on OMAP4430 devices.
+
+OMAP4460 onwards, MPU OFF state will be descoped completely because
+the DDR firewall falls in MPU power domain. When the MPU hit OFF state,
+DDR won't be accessible for other initiators. The deepest state supported
+is open switch retention (OSWR) just like CORE and PER PD on OMAP4430.
+
+So in summary MPU power domain OFF state is not supported on OMAP4
+and onwards designs. Thanks to new PRCM design, device off mode can
+still be achieved with power domains hitting OSWR state.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[b-cousson@ti.com: Fix changelog typos]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index 8f46e7d..247e794 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
+ .prcm_offs = OMAP4430_PRM_MPU_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+- .pwrsts = PWRSTS_OFF_RET_ON,
++ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0067-OMAP4-hwmod-data-Change-DSS-main_clk-scheme.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0067-OMAP4-hwmod-data-Change-DSS-main_clk-scheme.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0067-OMAP4-hwmod-data-Change-DSS-main_clk-scheme.patch
@@ -0,0 +1,163 @@
+From 51ebacf719349b5ec6f1743a27a865c36777145f Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Sat, 9 Jul 2011 20:39:45 -0600
+Subject: [PATCH 067/149] OMAP4: hwmod data: Change DSS main_clk scheme
+
+Currently using pm_runtime with DSS requires the DSS driver to enable
+the DSS functional clock before calling pm_runtime_get(). That makes it
+impossible to use pm_runtime in DSS as it is meant to be used, with
+pm_runtime callbacks.
+
+This patch changes the hwmod database for OMAP4 so that enabling the
+hwmod via pm_runtime will also enable the DSS functional clock, allowing
+us to use pm_runtime properly in DSS driver.
+
+The DSS HWMOD side is not really correct, not before nor after this
+patch, and getting DSS to retention will probably not work currently.
+However, it is not supported in the mainline kernel anyway, so this
+won't break anything.
+
+So this patch allows us to write the pm_runtime adaptation for the DSS
+driver the way it should be done, and the HWMOD/PM side can be fixed
+later.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 28 ++++++++++++++--------------
+ 1 files changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index a7fbe5c..b25ab83 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -1136,7 +1136,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1175,7 +1175,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_hwmod = {
+ .name = "dss_core",
+ .class = &omap44xx_dss_hwmod_class,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1238,7 +1238,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dispc_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_dispc_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1279,7 +1279,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1338,7 +1338,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi1_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_dsi1_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1376,7 +1376,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi1_irqs,
+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1414,7 +1414,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi2_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_dsi2_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1452,7 +1452,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1510,7 +1510,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hdmi_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_hdmi_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1548,7 +1548,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .class = &omap44xx_hdmi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_hdmi_irqs,
+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1601,7 +1601,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_rfbi_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_rfbi_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1638,7 +1638,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap44xx_rfbi_hwmod_class,
+ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+@@ -1675,7 +1675,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_venc_hwmod,
+- .clk = "l3_div_ck",
++ .clk = "dss_fck",
+ .addr = omap44xx_dss_venc_dma_addrs,
+ .user = OCP_USER_SDMA,
+ };
+@@ -1707,7 +1707,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap44xx_venc_hwmod_class,
+- .main_clk = "dss_fck",
++ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0068-I2C-OMAP2-Set-hwmod-flags-to-only-allow-16-bit-acces.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0068-I2C-OMAP2-Set-hwmod-flags-to-only-allow-16-bit-acces.patch
--- /dev/null
@@ -0,0 +1,133 @@
+From 2fd56de083cbb8ebd7750ac29d462bc38bb6b368 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:14 -0600
+Subject: [PATCH 068/149] I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2c
+
+Peter Maydell noticed when running under QEMU he was getting
+errors reporting 32-bit access to I2C peripheral unit registers
+that are documented to be 8 or 16-bit only[1][2]
+
+The I2C driver is blameless as it wraps its accesses in a
+function using __raw_writew and __raw_readw, it turned out it
+is the hwmod stuff.
+
+However the hwmod code already has a flag to force a
+perhipheral unit to only be accessed using 16-bit operations.
+
+This patch applies the 16-bit only flag to the 2430,
+OMAP3xxx and OMAP44xx hwmod structs. 2420 was already
+correctly marked up as 16-bit.
+
+The 2430 change will need testing by TI as arranged
+in the comments to the previous patch version.
+
+When the 16-bit flag is or-ed with other flags, it is placed
+first as requested in comments.
+
+[1] OMAP4430 Technical reference manual section 23.1.6.2
+[2] OMAP3530 Techincal reference manual section 18.6
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 ++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 3 +++
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++----
+ 3 files changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 2a52f02..19ddf08 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1092,6 +1092,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+
+ static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2chs1_fck",
+@@ -1127,6 +1128,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+
+ static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2chs2_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 1a52716..542a11b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1615,6 +1615,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
+@@ -1646,6 +1647,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
+@@ -1688,6 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+
+ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+ .name = "i2c3",
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_sdma_reqs,
+ .main_clk = "i2c3_fck",
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index b25ab83..2ebccb8 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -2201,7 +2201,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
+@@ -2254,7 +2254,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
+@@ -2307,7 +2307,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+ .main_clk = "i2c3_fck",
+@@ -2360,7 +2360,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+ .main_clk = "i2c4_fck",
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0069-I2C-OMAP2-increase-omap_i2c_dev_attr-flags-from-u8-t.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0069-I2C-OMAP2-increase-omap_i2c_dev_attr-flags-from-u8-t.patch
--- /dev/null
@@ -0,0 +1,46 @@
+From 6603b89339485a835a0597576e6dd56f1f58b651 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:14 -0600
+Subject: [PATCH 069/149] I2C: OMAP2+: increase omap_i2c_dev_attr flags from u8 to u32
+
+As part of removing cpu_...() from the OMAP I2C driver, we need to
+convert the CPU tests into functionality flags that are set by
+hwmod class in the same way the IP revision is.
+
+More flags are needed than will fit in the existing u8 flags
+member of omap_i2c_dev_attr.
+
+These flags can refer to options inside the IP block but they are
+most needed for information about cpu implementation specific
+options that are not part of the IP block itself. For example,
+how the CPU data bus is wired to the IP block databus differs
+between OMAP cpus and affects how you must shift the address in
+the IP block, but is not a feature of the IP block itself.
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/include/plat/i2c.h | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
+index 878d632..4c108f5 100644
+--- a/arch/arm/plat-omap/include/plat/i2c.h
++++ b/arch/arm/plat-omap/include/plat/i2c.h
+@@ -46,7 +46,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+ */
+ struct omap_i2c_dev_attr {
+ u8 fifo_depth;
+- u8 flags;
++ u32 flags;
+ };
+
+ void __init omap1_i2c_mux_pins(int bus_id);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0070-I2C-OMAP2-Introduce-I2C-IP-versioning-constants.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0070-I2C-OMAP2-Introduce-I2C-IP-versioning-constants.patch
--- /dev/null
@@ -0,0 +1,61 @@
+From 24c2c380b4b9c37d5f544374eb6b8695d3714ed6 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:14 -0600
+Subject: [PATCH 070/149] I2C: OMAP2+: Introduce I2C IP versioning constants
+
+These represent the two kinds of (incompatible) OMAP I2C
+peripheral unit in use so far.
+
+The constants are in linux/i2c-omap.h so the omap i2c driver can have
+them too.
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/include/plat/i2c.h | 1 +
+ include/linux/i2c-omap.h | 12 ++++++++++++
+ 2 files changed, 13 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
+index 4c108f5..fd75dad 100644
+--- a/arch/arm/plat-omap/include/plat/i2c.h
++++ b/arch/arm/plat-omap/include/plat/i2c.h
+@@ -22,6 +22,7 @@
+ #define __ASM__ARCH_OMAP_I2C_H
+
+ #include <linux/i2c.h>
++#include <linux/i2c-omap.h>
+
+ #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+ extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
+index 7472449..701886d 100644
+--- a/include/linux/i2c-omap.h
++++ b/include/linux/i2c-omap.h
+@@ -3,6 +3,18 @@
+
+ #include <linux/platform_device.h>
+
++/*
++ * Version 2 of the I2C peripheral unit has a different register
++ * layout and extra registers. The ID register in the V2 peripheral
++ * unit on the OMAP4430 reports the same ID as the V1 peripheral
++ * unit on the OMAP3530, so we must inform the driver which IP
++ * version we know it is running on from platform / cpu-specific
++ * code using these constants in the hwmod class definition.
++ */
++
++#define OMAP_I2C_IP_VERSION_1 1
++#define OMAP_I2C_IP_VERSION_2 2
++
+ struct omap_i2c_bus_platform_data {
+ u32 clkrate;
+ void (*set_mpu_wkup_lat)(struct device *dev, long set);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0071-I2C-OMAP1-OMAP2-create-omap-I2C-functionality-flags-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0071-I2C-OMAP1-OMAP2-create-omap-I2C-functionality-flags-.patch
--- /dev/null
@@ -0,0 +1,51 @@
+From 0793fbb7443250a496c72043667406b71aaabc71 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:15 -0600
+Subject: [PATCH 071/149] I2C: OMAP1/OMAP2+: create omap I2C functionality flags for each cpu_... test
+
+These represent the 8 kinds of implementation functionality
+that up until now were inferred by the 16 remaining cpu_...()
+tests in the omap i2c driver.
+
+Changed to use BIT() as suggested by Balaji T Krishnamoorthy.
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ include/linux/i2c-omap.h | 15 +++++++++++++++
+ 1 files changed, 15 insertions(+), 0 deletions(-)
+
+diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
+index 701886d..0aa0cbd 100644
+--- a/include/linux/i2c-omap.h
++++ b/include/linux/i2c-omap.h
+@@ -15,6 +15,21 @@
+ #define OMAP_I2C_IP_VERSION_1 1
+ #define OMAP_I2C_IP_VERSION_2 2
+
++/* struct omap_i2c_bus_platform_data .flags meanings */
++
++#define OMAP_I2C_FLAG_NO_FIFO BIT(0)
++#define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
++#define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
++#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
++#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
++#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
++#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
++/* how the CPU address bus must be translated for I2C unit access */
++#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
++#define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7)
++#define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8)
++#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
++
+ struct omap_i2c_bus_platform_data {
+ u32 clkrate;
+ void (*set_mpu_wkup_lat)(struct device *dev, long set);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0072-I2C-OMAP2-Tag-all-OMAP2-hwmod-defintions-with-I2C-IP.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0072-I2C-OMAP2-Tag-all-OMAP2-hwmod-defintions-with-I2C-IP.patch
--- /dev/null
@@ -0,0 +1,77 @@
+From 02a2751e0c1c30b6a5ebbb32a9e5d2c95e534d23 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:15 -0600
+Subject: [PATCH 072/149] I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision
+
+Since we cannot trust (or even reliably find) the OMAP I2C
+peripheral unit's own revision register, we must inform the
+OMAP i2c driver of which IP version it is running on. We
+do this by tagging the omap_hwmod_class for i2c on all the
+OMAP2+ platform / cpu specific hwmod init and passing it up
+to the driver (next patches).
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 +
+ 4 files changed, 4 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index f3901ab..95f547c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1029,6 +1029,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
++ .rev = OMAP_I2C_IP_VERSION_1,
+ };
+
+ static struct omap_i2c_dev_attr i2c_dev_attr;
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 19ddf08..d7ed51b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1078,6 +1078,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
++ .rev = OMAP_I2C_IP_VERSION_1,
+ };
+
+ static struct omap_i2c_dev_attr i2c_dev_attr = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 542a11b..58ec1e2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1308,6 +1308,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
++ .rev = OMAP_I2C_IP_VERSION_1,
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 2ebccb8..1bed3b8 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -2160,6 +2160,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
+ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &omap44xx_i2c_sysc,
++ .rev = OMAP_I2C_IP_VERSION_2,
+ };
+
+ /* i2c1 */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0073-I2C-OMAP2-add-correct-functionality-flags-to-all-oma.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0073-I2C-OMAP2-add-correct-functionality-flags-to-all-oma.patch
--- /dev/null
@@ -0,0 +1,146 @@
+From 3d1de2860ea9b5f0cd052c0b4b3a5bc0b3a71c40 Mon Sep 17 00:00:00 2001
+From: Andy Green <andy@warmcat.com>
+Date: Sun, 10 Jul 2011 05:27:16 -0600
+Subject: [PATCH 073/149] I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attr
+
+This adds the new functionality flags for omap i2c unit to all OMAP2
+hwmod definitions
+
+Cc: patches@linaro.org
+Cc: Ben Dooks <ben-linux@fluff.org>
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andy Green <andy.green@linaro.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 7 ++++++-
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +++++++++
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 9 +++++++++
+ 4 files changed, 27 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 95f547c..7af2514 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1032,7 +1032,12 @@ static struct omap_hwmod_class i2c_class = {
+ .rev = OMAP_I2C_IP_VERSION_1,
+ };
+
+-static struct omap_i2c_dev_attr i2c_dev_attr;
++static struct omap_i2c_dev_attr i2c_dev_attr = {
++ .flags = OMAP_I2C_FLAG_NO_FIFO |
++ OMAP_I2C_FLAG_SIMPLE_CLOCK |
++ OMAP_I2C_FLAG_16BIT_DATA_REG |
++ OMAP_I2C_FLAG_BUS_SHIFT_2,
++};
+
+ /* I2C1 */
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index d7ed51b..405688a 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1083,6 +1083,9 @@ static struct omap_hwmod_class i2c_class = {
+
+ static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .fifo_depth = 8, /* bytes */
++ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
++ OMAP_I2C_FLAG_BUS_SHIFT_2 |
++ OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
+ };
+
+ /* I2C1 */
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 58ec1e2..c704ac8 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1608,6 +1608,9 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
+
+ static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
++ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
++ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
++ OMAP_I2C_FLAG_BUS_SHIFT_2,
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+@@ -1640,6 +1643,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+
+ static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
++ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
++ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
++ OMAP_I2C_FLAG_BUS_SHIFT_2,
+ };
+
+ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+@@ -1672,6 +1678,9 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+
+ static struct omap_i2c_dev_attr i2c3_dev_attr = {
+ .fifo_depth = 64, /* bytes */
++ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
++ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
++ OMAP_I2C_FLAG_BUS_SHIFT_2,
+ };
+
+ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 1bed3b8..55331df 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -27,6 +27,7 @@
+ #include <plat/mcspi.h>
+ #include <plat/mcbsp.h>
+ #include <plat/mmc.h>
++#include <plat/i2c.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -2163,6 +2164,10 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+ .rev = OMAP_I2C_IP_VERSION_2,
+ };
+
++static struct omap_i2c_dev_attr i2c_dev_attr = {
++ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
++};
++
+ /* i2c1 */
+ static struct omap_hwmod omap44xx_i2c1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+@@ -2213,6 +2218,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ },
+ .slaves = omap44xx_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
++ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -2266,6 +2272,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ },
+ .slaves = omap44xx_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
++ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -2319,6 +2326,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ },
+ .slaves = omap44xx_i2c3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
++ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -2372,6 +2380,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ },
+ .slaves = omap44xx_i2c4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
++ .dev_attr = &i2c_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0074-OMAP-hwmod-fix-the-i2c-reset-timeout-during-bootup.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0074-OMAP-hwmod-fix-the-i2c-reset-timeout-during-bootup.patch
--- /dev/null
@@ -0,0 +1,286 @@
+From c53cc7d7eb7c4cc2d64f8f19dedb01639cb36b17 Mon Sep 17 00:00:00 2001
+From: Avinash.H.M <avinashhm@ti.com>
+Date: Sun, 10 Jul 2011 05:27:16 -0600
+Subject: [PATCH 074/149] OMAP: hwmod: fix the i2c-reset timeout during bootup
+
+The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
+special sequence to reset the module. The sequence is
+ - Disable the I2C.
+ - Write to SOFTRESET bit.
+ - Enable the I2C.
+ - Poll on the RESETDONE bit.
+The sequence is implemented as a function and the i2c_class is updated with
+the correct 'reset' pointer. omap_hwmod_softreset function is implemented
+which triggers the softreset by writing into sysconfig register. On following
+this sequence, i2c module resets properly and timeouts are not seen.
+
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Avinash.H.M <avinashhm@ti.com>
+[paul@pwsan.com: combined this patch with a patch to remove
+ HWMOD_INIT_NO_RESET from the 44xx hwmod flags; change register
+ offset conditional code to use the IP block revision; minor code
+ cleanup]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/i2c.c | 68 ++++++++++++++++++++++++++
+ arch/arm/mach-omap2/omap_hwmod.c | 27 ++++++++++
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 7 ++-
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 ++--
+ arch/arm/plat-omap/include/plat/i2c.h | 3 +
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 8 files changed, 111 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
+index 79c478c..ace9994 100644
+--- a/arch/arm/mach-omap2/i2c.c
++++ b/arch/arm/mach-omap2/i2c.c
+@@ -21,9 +21,19 @@
+
+ #include <plat/cpu.h>
+ #include <plat/i2c.h>
++#include <plat/common.h>
++#include <plat/omap_hwmod.h>
+
+ #include "mux.h"
+
++/* In register I2C_CON, Bit 15 is the I2C enable bit */
++#define I2C_EN BIT(15)
++#define OMAP2_I2C_CON_OFFSET 0x24
++#define OMAP4_I2C_CON_OFFSET 0xA4
++
++/* Maximum microseconds to wait for OMAP module to softreset */
++#define MAX_MODULE_SOFTRESET_WAIT 10000
++
+ void __init omap2_i2c_mux_pins(int bus_id)
+ {
+ char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
+ sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+ omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+ }
++
++/**
++ * omap_i2c_reset - reset the omap i2c module.
++ * @oh: struct omap_hwmod *
++ *
++ * The i2c moudle in omap2, omap3 had a special sequence to reset. The
++ * sequence is:
++ * - Disable the I2C.
++ * - Write to SOFTRESET bit.
++ * - Enable the I2C.
++ * - Poll on the RESETDONE bit.
++ * The sequence is implemented in below function. This is called for 2420,
++ * 2430 and omap3.
++ */
++int omap_i2c_reset(struct omap_hwmod *oh)
++{
++ u32 v;
++ u16 i2c_con;
++ int c = 0;
++
++ if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
++ i2c_con = OMAP4_I2C_CON_OFFSET;
++ } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
++ i2c_con = OMAP2_I2C_CON_OFFSET;
++ } else {
++ WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
++ oh->name);
++ return -EINVAL;
++ }
++
++ /* Disable I2C */
++ v = omap_hwmod_read(oh, i2c_con);
++ v &= ~I2C_EN;
++ omap_hwmod_write(v, oh, i2c_con);
++
++ /* Write to the SOFTRESET bit */
++ omap_hwmod_softreset(oh);
++
++ /* Enable I2C */
++ v = omap_hwmod_read(oh, i2c_con);
++ v |= I2C_EN;
++ omap_hwmod_write(v, oh, i2c_con);
++
++ /* Poll on RESETDONE bit */
++ omap_test_timeout((omap_hwmod_read(oh,
++ oh->class->sysc->syss_offs)
++ & SYSS_RESETDONE_MASK),
++ MAX_MODULE_SOFTRESET_WAIT, c);
++
++ if (c == MAX_MODULE_SOFTRESET_WAIT)
++ pr_warning("%s: %s: softreset failed (waited %d usec)\n",
++ __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
++ else
++ pr_debug("%s: %s: softreset in %d usec\n", __func__,
++ oh->name, c);
++
++ return 0;
++}
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 7d242c9..02b6016 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1656,6 +1656,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+ }
+
+ /**
++ * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
++ * @oh: struct omap_hwmod *
++ *
++ * This is a public function exposed to drivers. Some drivers may need to do
++ * some settings before and after resetting the device. Those drivers after
++ * doing the necessary settings could use this function to start a reset by
++ * setting the SYSCONFIG.SOFTRESET bit.
++ */
++int omap_hwmod_softreset(struct omap_hwmod *oh)
++{
++ u32 v;
++ int ret;
++
++ if (!oh || !(oh->_sysc_cache))
++ return -EINVAL;
++
++ v = oh->_sysc_cache;
++ ret = _set_softreset(oh, &v);
++ if (ret)
++ goto error;
++ _write_sysconfig(v, oh);
++
++error:
++ return ret;
++}
++
++/**
+ * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
+ * @oh: struct omap_hwmod *
+ * @idlemode: SIDLEMODE field bits (shifted to bit 0)
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 7af2514..a015c69 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1030,6 +1030,7 @@ static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
++ .reset = &omap_i2c_reset,
+ };
+
+ static struct omap_i2c_dev_attr i2c_dev_attr = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 405688a..16743c7 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1079,6 +1079,7 @@ static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
++ .reset = &omap_i2c_reset,
+ };
+
+ static struct omap_i2c_dev_attr i2c_dev_attr = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index c704ac8..25bf43b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1306,9 +1306,10 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ };
+
+ static struct omap_hwmod_class i2c_class = {
+- .name = "i2c",
+- .sysc = &i2c_sysc,
+- .rev = OMAP_I2C_IP_VERSION_1,
++ .name = "i2c",
++ .sysc = &i2c_sysc,
++ .rev = OMAP_I2C_IP_VERSION_1,
++ .reset = &omap_i2c_reset,
+ };
+
+ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 55331df..5d5df49 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -22,6 +22,7 @@
+
+ #include <plat/omap_hwmod.h>
+ #include <plat/cpu.h>
++#include <plat/i2c.h>
+ #include <plat/gpio.h>
+ #include <plat/dma.h>
+ #include <plat/mcspi.h>
+@@ -2162,6 +2163,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &omap44xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
++ .reset = &omap_i2c_reset,
+ };
+
+ static struct omap_i2c_dev_attr i2c_dev_attr = {
+@@ -2207,7 +2209,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
+@@ -2261,7 +2263,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
+@@ -2315,7 +2317,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+ .main_clk = "i2c3_fck",
+@@ -2369,7 +2371,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &omap44xx_i2c_hwmod_class,
+- .flags = HWMOD_16BIT_REG | HWMOD_INIT_NO_RESET,
++ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+ .main_clk = "i2c4_fck",
+diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
+index fd75dad..7c22b9e 100644
+--- a/arch/arm/plat-omap/include/plat/i2c.h
++++ b/arch/arm/plat-omap/include/plat/i2c.h
+@@ -53,4 +53,7 @@ struct omap_i2c_dev_attr {
+ void __init omap1_i2c_mux_pins(int bus_id);
+ void __init omap2_i2c_mux_pins(int bus_id);
+
++struct omap_hwmod;
++int omap_i2c_reset(struct omap_hwmod *oh);
++
+ #endif /* __ASM__ARCH_OMAP_I2C_H */
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index ce06ac6..fafdfe3 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -566,6 +566,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
+
+ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
+ u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
++int omap_hwmod_softreset(struct omap_hwmod *oh);
+
+ int omap_hwmod_count_resources(struct omap_hwmod *oh);
+ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0075-OMAP-omap_device-Create-clkdev-entry-for-hwmod-main_.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0075-OMAP-omap_device-Create-clkdev-entry-for-hwmod-main_.patch
--- /dev/null
@@ -0,0 +1,437 @@
+From f79980592a72321ba8a5b73e4c5907d369c70b4b Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:54:12 -0600
+Subject: [PATCH 075/149] OMAP: omap_device: Create clkdev entry for hwmod main_clk
+
+Extend the existing function to create clkdev for every optional
+clocks to add a well one "fck" alias for the main_clk of the
+omap_hwmod.
+It will allow to remove these static clkdev entries from the
+clockXXX_data.c file.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Todd Poynor <toddpoynor@google.com>
+[paul@pwsan.com: remove all of the "fck" role clkdev aliases from the
+ clock data files; fixed error message]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 22 ++++----
+ arch/arm/mach-omap2/clock2430_data.c | 32 ++++++------
+ arch/arm/mach-omap2/clock3xxx_data.c | 44 +++++++++---------
+ arch/arm/mach-omap2/clock44xx_data.c | 38 ++++++++--------
+ arch/arm/plat-omap/omap_device.c | 85 ++++++++++++++++++++--------------
+ 5 files changed, 118 insertions(+), 103 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 2926d02..debc040 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
+ /* DSS domain clocks */
+ CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
+- CLK("omapdss_dss", "fck", &dss1_fck, CK_242X),
+- CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X),
+- CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X),
++ CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
++ CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
++ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
+ /* L3 domain clocks */
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
+@@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
+- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
++ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
+- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
++ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
+- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
++ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
+- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
++ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
+@@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
+- CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
++ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
+@@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "eac_ick", &eac_ick, CK_242X),
+ CLK(NULL, "eac_fck", &eac_fck, CK_242X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
+- CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
++ CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
+- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X),
++ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
+- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X),
++ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 0c79d39..96a942e 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
+ /* DSS domain clocks */
+ CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
+- CLK("omapdss_dss", "fck", &dss1_fck, CK_243X),
+- CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X),
+- CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X),
++ CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
++ CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
++ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
+ /* L3 domain clocks */
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
+@@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
+- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
++ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
+- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
++ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
+ CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
+- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
++ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
+ CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
+- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
++ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
+ CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
+- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
++ CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
+- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
++ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
+- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
++ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
+ CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
+- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
++ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
+@@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
+- CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
++ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
+@@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = {
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
+ CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
+- CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X),
++ CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
+- CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X),
++ CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
+@@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "usb_fck", &usb_fck, CK_243X),
+ CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
+ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
+- CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
++ CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
+ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
+- CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
++ CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
+ CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
+ CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 75b119b..ffd55b1 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
+ CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
+ CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
+- CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+- CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
++ CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
++ CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
+- CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
+- CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
+- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
+- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
+- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
+- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
++ CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
++ CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
++ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
++ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
++ CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
++ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
+ CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
+- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
+- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
+- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
+- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
++ CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
++ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
++ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
++ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
+ CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+ CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
+- CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
++ CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
+ CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
+ CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
+ CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
+@@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
+- CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
+- CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+- CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX),
+- CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX),
+- CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX),
++ CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
++ CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
++ CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
++ CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
++ CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
+ CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
+ CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
+@@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
+ CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
+ CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
+- CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
++ CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
+ CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
+ CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
+@@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
+ CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
+ CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
+- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
+- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
+- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
++ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
++ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
++ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
+ CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
+ CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
+ CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 2578820..763507f 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3057,12 +3057,12 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
+ CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
+ CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
+- CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
++ CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
+ CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
+- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X),
+- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X),
+- CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X),
+- CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X),
++ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
++ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
++ CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
++ CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
+ CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
+ CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
+ CLK(NULL, "iss_fck", &iss_fck, CK_443X),
+@@ -3073,23 +3073,23 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
+ CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
+ CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
+- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
++ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
+ CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
+- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
++ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
+ CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
+- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
++ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
+ CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
+- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
++ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
+ CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
+- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
+- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
+- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
+- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
+- CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
+- CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
+- CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
+- CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
+- CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
++ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
++ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
++ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
++ CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
++ CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
++ CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
++ CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
++ CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
++ CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
+ CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
+ CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
+ CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
+@@ -3146,7 +3146,7 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "usim_ck", &usim_ck, CK_443X),
+ CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
+ CLK(NULL, "usim_fck", &usim_fck, CK_443X),
+- CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
++ CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
+ CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
+ CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
+ CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
+diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
+index c8b9cd1..be45147 100644
+--- a/arch/arm/plat-omap/omap_device.c
++++ b/arch/arm/plat-omap/omap_device.c
+@@ -236,56 +236,71 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
+ return 0;
+ }
+
++static void _add_clkdev(struct omap_device *od, const char *clk_alias,
++ const char *clk_name)
++{
++ struct clk *r;
++ struct clk_lookup *l;
++
++ if (!clk_alias || !clk_name)
++ return;
++
++ pr_debug("omap_device: %s: Creating %s -> %s\n",
++ dev_name(&od->pdev.dev), clk_alias, clk_name);
++
++ r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
++ if (!IS_ERR(r)) {
++ pr_warning("omap_device: %s: alias %s already exists\n",
++ dev_name(&od->pdev.dev), clk_alias);
++ clk_put(r);
++ return;
++ }
++
++ r = omap_clk_get_by_name(clk_name);
++ if (IS_ERR(r)) {
++ pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
++ dev_name(&od->pdev.dev), clk_name);
++ return;
++ }
++
++ l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
++ if (!l) {
++ pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
++ dev_name(&od->pdev.dev), clk_alias);
++ return;
++ }
++
++ clkdev_add(l);
++}
++
+ /**
+- * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
++ * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
++ * and main clock
+ * @od: struct omap_device *od
++ * @oh: struct omap_hwmod *oh
+ *
+- * For every optional clock present per hwmod per omap_device, this function
+- * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
+- * if it does not exist already.
++ * For the main clock and every optional clock present per hwmod per
++ * omap_device, this function adds an entry in the clkdev table of the
++ * form <dev-id=dev_name, con-id=role> if it does not exist already.
+ *
+ * The function is called from inside omap_device_build_ss(), after
+ * omap_device_register.
+ *
+ * This allows drivers to get a pointer to its optional clocks based on its role
+ * by calling clk_get(<dev*>, <role>).
++ * In the case of the main clock, a "fck" alias is used.
+ *
+ * No return value.
+ */
+-static void _add_optional_clock_clkdev(struct omap_device *od,
+- struct omap_hwmod *oh)
++static void _add_hwmod_clocks_clkdev(struct omap_device *od,
++ struct omap_hwmod *oh)
+ {
+ int i;
+
+- for (i = 0; i < oh->opt_clks_cnt; i++) {
+- struct omap_hwmod_opt_clk *oc;
+- struct clk *r;
+- struct clk_lookup *l;
+-
+- oc = &oh->opt_clks[i];
+-
+- if (!oc->_clk)
+- continue;
+-
+- r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
+- if (!IS_ERR(r))
+- continue; /* clkdev entry exists */
++ _add_clkdev(od, "fck", oh->main_clk);
+
+- r = omap_clk_get_by_name((char *)oc->clk);
+- if (IS_ERR(r)) {
+- pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+- dev_name(&od->pdev.dev), oc->clk);
+- continue;
+- }
+-
+- l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
+- if (!l) {
+- pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+- dev_name(&od->pdev.dev), oc->role);
+- return;
+- }
+- clkdev_add(l);
+- }
++ for (i = 0; i < oh->opt_clks_cnt; i++)
++ _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
+ }
+
+
+@@ -492,7 +507,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+
+ for (i = 0; i < oh_cnt; i++) {
+ hwmods[i]->od = od;
+- _add_optional_clock_clkdev(od, hwmods[i]);
++ _add_hwmod_clocks_clkdev(od, hwmods[i]);
+ }
+
+ if (ret)
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0076-OMAP4-clock-data-Add-missing-divider-selection-for-a.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0076-OMAP4-clock-data-Add-missing-divider-selection-for-a.patch
--- /dev/null
@@ -0,0 +1,292 @@
+From ce0ebe8b4f82a3205f9576400840d9fc0ae719d9 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Sun, 10 Jul 2011 05:56:14 -0600
+Subject: [PATCH 076/149] OMAP4: clock data: Add missing divider selection for auxclks
+
+On OMAP4 the auxclk nodes (part of SCRM) support both
+divider as well as parent selection.
+Supporting this requires splitting the existing nodes
+(which support only parent selection) into two nodes,
+one for parent and another for divider selection.
+The nodes for parent selection are named auxclk*_src_ck
+and the ones for divider selection as auxclk*_ck.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[b-cousson@ti.com: Rebase on top of clock cleanup
+and autogen alignement]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 176 +++++++++++++++++++++++++++++-----
+ 1 files changed, 152 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 763507f..07bf0de 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -2774,19 +2774,39 @@ static struct clk trace_clk_div_ck = {
+
+ /* SCRM aux clk nodes */
+
+-static const struct clksel auxclk_sel[] = {
++static const struct clksel auxclk_src_sel[] = {
+ { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+ { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+ { .parent = NULL },
+ };
+
+-static struct clk auxclk0_ck = {
+- .name = "auxclk0_ck",
++static const struct clksel_rate div16_1to16_rates[] = {
++ { .div = 1, .val = 0, .flags = RATE_IN_4430 },
++ { .div = 2, .val = 1, .flags = RATE_IN_4430 },
++ { .div = 3, .val = 2, .flags = RATE_IN_4430 },
++ { .div = 4, .val = 3, .flags = RATE_IN_4430 },
++ { .div = 5, .val = 4, .flags = RATE_IN_4430 },
++ { .div = 6, .val = 5, .flags = RATE_IN_4430 },
++ { .div = 7, .val = 6, .flags = RATE_IN_4430 },
++ { .div = 8, .val = 7, .flags = RATE_IN_4430 },
++ { .div = 9, .val = 8, .flags = RATE_IN_4430 },
++ { .div = 10, .val = 9, .flags = RATE_IN_4430 },
++ { .div = 11, .val = 10, .flags = RATE_IN_4430 },
++ { .div = 12, .val = 11, .flags = RATE_IN_4430 },
++ { .div = 13, .val = 12, .flags = RATE_IN_4430 },
++ { .div = 14, .val = 13, .flags = RATE_IN_4430 },
++ { .div = 15, .val = 14, .flags = RATE_IN_4430 },
++ { .div = 16, .val = 15, .flags = RATE_IN_4430 },
++ { .div = 0 },
++};
++
++static struct clk auxclk0_src_ck = {
++ .name = "auxclk0_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK0,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2794,12 +2814,29 @@ static struct clk auxclk0_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
+-static struct clk auxclk1_ck = {
+- .name = "auxclk1_ck",
++static const struct clksel auxclk0_sel[] = {
++ { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk0_ck = {
++ .name = "auxclk0_ck",
++ .parent = &auxclk0_src_ck,
++ .clksel = auxclk0_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK0,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
++static struct clk auxclk1_src_ck = {
++ .name = "auxclk1_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK1,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2807,12 +2844,29 @@ static struct clk auxclk1_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
+-static struct clk auxclk2_ck = {
+- .name = "auxclk2_ck",
++static const struct clksel auxclk1_sel[] = {
++ { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk1_ck = {
++ .name = "auxclk1_ck",
++ .parent = &auxclk1_src_ck,
++ .clksel = auxclk1_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK1,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
++static struct clk auxclk2_src_ck = {
++ .name = "auxclk2_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK2,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2820,12 +2874,29 @@ static struct clk auxclk2_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
+-static struct clk auxclk3_ck = {
+- .name = "auxclk3_ck",
++static const struct clksel auxclk2_sel[] = {
++ { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk2_ck = {
++ .name = "auxclk2_ck",
++ .parent = &auxclk2_src_ck,
++ .clksel = auxclk2_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK2,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
++static struct clk auxclk3_src_ck = {
++ .name = "auxclk3_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK3,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2833,12 +2904,29 @@ static struct clk auxclk3_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
+-static struct clk auxclk4_ck = {
+- .name = "auxclk4_ck",
++static const struct clksel auxclk3_sel[] = {
++ { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk3_ck = {
++ .name = "auxclk3_ck",
++ .parent = &auxclk3_src_ck,
++ .clksel = auxclk3_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK3,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
++static struct clk auxclk4_src_ck = {
++ .name = "auxclk4_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK4,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2846,12 +2934,29 @@ static struct clk auxclk4_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
+-static struct clk auxclk5_ck = {
+- .name = "auxclk5_ck",
++static const struct clksel auxclk4_sel[] = {
++ { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk4_ck = {
++ .name = "auxclk4_ck",
++ .parent = &auxclk4_src_ck,
++ .clksel = auxclk4_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK4,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
++static struct clk auxclk5_src_ck = {
++ .name = "auxclk5_src_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+- .clksel = auxclk_sel,
++ .clksel = auxclk_src_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK5,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+@@ -2859,6 +2964,23 @@ static struct clk auxclk5_ck = {
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+ };
+
++static const struct clksel auxclk5_sel[] = {
++ { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
++ { .parent = NULL },
++};
++
++static struct clk auxclk5_ck = {
++ .name = "auxclk5_ck",
++ .parent = &auxclk5_src_ck,
++ .clksel = auxclk5_sel,
++ .clksel_reg = OMAP4_SCRM_AUXCLK5,
++ .clksel_mask = OMAP4_CLKDIV_MASK,
++ .ops = &clkops_null,
++ .recalc = &omap2_clksel_recalc,
++ .round_rate = &omap2_clksel_round_rate,
++ .set_rate = &omap2_clksel_set_rate,
++};
++
+ static const struct clksel auxclkreq_sel[] = {
+ { .parent = &auxclk0_ck, .rates = div_1_0_rates },
+ { .parent = &auxclk1_ck, .rates = div_1_1_rates },
+@@ -3150,17 +3272,23 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
+ CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
+ CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
++ CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
+ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
+- CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
+- CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
+- CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
+- CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
+- CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
+ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
++ CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
++ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
+ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
++ CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
++ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
+ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
++ CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
++ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
+ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
++ CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
++ CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
+ CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
++ CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
++ CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
+ CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0077-OMAP4-hwmod-data-Add-clock-domain-attribute.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0077-OMAP4-hwmod-data-Add-clock-domain-attribute.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0077-OMAP4-hwmod-data-Add-clock-domain-attribute.patch
@@ -0,0 +1,724 @@
+From 73306ce1db51cc04a79cf002b9b5569d74b75f1c Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:29 -0600
+Subject: [PATCH 077/149] OMAP4: hwmod data: Add clock domain attribute
+
+In OMAP PRCM terminology, the clock domain is defined as a group of IPs
+that share some clocks and most of the time an interface clock.
+Every IP does belong to a clockdomain.
+For the moment the clock domain attribute is affected to a clock node.
+The issue with that approach, is that a clock might or not belong to a
+clock domain. Moreover during module transition, it is up to a module
+to handle properly the clock domain state and not to a clock node.
+
+Create a clkdm_name attribute to provide this information per hwmod.
+
+Populate this attribute for every OMAP4 hwmod entries.
+
+Future cleanup series with remove that information from the OMAP4 clock
+when it is relevant.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: fix the mpuss_clkdm name]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +-
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 85 +++++++++++++++++++++++++-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 3 files changed, 85 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index 66090f2..dccc651 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -565,7 +565,7 @@ static struct clockdomain ducati_44xx_clkdm = {
+ };
+
+ static struct clockdomain mpu_44xx_clkdm = {
+- .name = "mpu_clkdm",
++ .name = "mpuss_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = OMAP4430_CM1_PARTITION,
+ .cm_inst = OMAP4430_CM1_MPU_INST,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 5d5df49..becae45 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -123,9 +123,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+ static struct omap_hwmod omap44xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &omap44xx_dmm_hwmod_class,
+- .mpu_irqs = omap44xx_dmm_irqs,
++ .clkdm_name = "l3_emif_clkdm",
+ .slaves = omap44xx_dmm_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
++ .mpu_irqs = omap44xx_dmm_irqs,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+
+@@ -173,6 +174,7 @@ static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
+ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &omap44xx_emif_fw_hwmod_class,
++ .clkdm_name = "l3_emif_clkdm",
+ .slaves = omap44xx_emif_fw_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -212,6 +214,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &omap44xx_l3_hwmod_class,
++ .clkdm_name = "l3_instr_clkdm",
+ .slaves = omap44xx_l3_instr_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -304,6 +307,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap44xx_l3_hwmod_class,
++ .clkdm_name = "l3_1_clkdm",
+ .mpu_irqs = omap44xx_l3_main_1_irqs,
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+@@ -400,6 +404,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+ .name = "l3_main_2",
+ .class = &omap44xx_l3_hwmod_class,
++ .clkdm_name = "l3_2_clkdm",
+ .slaves = omap44xx_l3_main_2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -450,6 +455,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+ .name = "l3_main_3",
+ .class = &omap44xx_l3_hwmod_class,
++ .clkdm_name = "l3_instr_clkdm",
+ .slaves = omap44xx_l3_main_3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -507,6 +513,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+ .name = "l4_abe",
+ .class = &omap44xx_l4_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .slaves = omap44xx_l4_abe_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -529,6 +536,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
+ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+ .name = "l4_cfg",
+ .class = &omap44xx_l4_hwmod_class,
++ .clkdm_name = "l4_cfg_clkdm",
+ .slaves = omap44xx_l4_cfg_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -551,6 +559,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
+ static struct omap_hwmod omap44xx_l4_per_hwmod = {
+ .name = "l4_per",
+ .class = &omap44xx_l4_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .slaves = omap44xx_l4_per_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -573,6 +582,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
+ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &omap44xx_l4_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .slaves = omap44xx_l4_wkup_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -603,6 +613,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
+ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ .name = "mpu_private",
+ .class = &omap44xx_mpu_bus_hwmod_class,
++ .clkdm_name = "mpuss_clkdm",
+ .slaves = omap44xx_mpu_private_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -741,6 +752,7 @@ static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
+ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .name = "aess",
+ .class = &omap44xx_aess_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_aess_irqs,
+ .sdma_reqs = omap44xx_aess_sdma_reqs,
+ .main_clk = "aess_fck",
+@@ -773,6 +785,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
+ static struct omap_hwmod omap44xx_bandgap_hwmod = {
+ .name = "bandgap",
+ .class = &omap44xx_bandgap_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+@@ -830,6 +843,7 @@ static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
+ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .class = &omap44xx_counter_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+@@ -913,6 +927,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
+ static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &omap44xx_dma_hwmod_class,
++ .clkdm_name = "l3_dma_clkdm",
+ .mpu_irqs = omap44xx_dma_system_irqs,
+ .main_clk = "l3_div_ck",
+ .prcm = {
+@@ -1005,6 +1020,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
+ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .name = "dmic",
+ .class = &omap44xx_dmic_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_dmic_irqs,
+ .sdma_reqs = omap44xx_dmic_sdma_reqs,
+ .main_clk = "dmic_fck",
+@@ -1072,6 +1088,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
+ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
+ .name = "dsp_c0",
+ .class = &omap44xx_dsp_hwmod_class,
++ .clkdm_name = "tesla_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_dsp_c0_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
+@@ -1086,6 +1103,7 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
+ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .name = "dsp",
+ .class = &omap44xx_dsp_hwmod_class,
++ .clkdm_name = "tesla_clkdm",
+ .mpu_irqs = omap44xx_dsp_irqs,
+ .rst_lines = omap44xx_dsp_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
+@@ -1177,6 +1195,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_hwmod = {
+ .name = "dss_core",
+ .class = &omap44xx_dss_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+@@ -1278,7 +1297,7 @@ static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap44xx_dispc_hwmod_class,
+- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
++ .clkdm_name = "l3_dss_clkdm",
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+@@ -1376,6 +1395,7 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap44xx_dsi_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .mpu_irqs = omap44xx_dss_dsi1_irqs,
+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+@@ -1452,6 +1472,7 @@ static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .name = "dss_dsi2",
+ .class = &omap44xx_dsi_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+@@ -1548,6 +1569,7 @@ static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &omap44xx_hdmi_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .mpu_irqs = omap44xx_dss_hdmi_irqs,
+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+@@ -1639,6 +1661,7 @@ static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap44xx_rfbi_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+@@ -1709,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap44xx_venc_hwmod_class,
++ .clkdm_name = "l3_dss_clkdm",
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+@@ -1786,6 +1810,7 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = omap44xx_gpio1_irqs,
+ .main_clk = "gpio1_ick",
+ .prcm = {
+@@ -1838,6 +1863,7 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio2_irqs,
+ .main_clk = "gpio2_ick",
+@@ -1891,6 +1917,7 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio3_irqs,
+ .main_clk = "gpio3_ick",
+@@ -1944,6 +1971,7 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio4_irqs,
+ .main_clk = "gpio4_ick",
+@@ -1997,6 +2025,7 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .name = "gpio5",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio5_irqs,
+ .main_clk = "gpio5_ick",
+@@ -2050,6 +2079,7 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .name = "gpio6",
+ .class = &omap44xx_gpio_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap44xx_gpio6_irqs,
+ .main_clk = "gpio6_ick",
+@@ -2129,6 +2159,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
+ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .name = "hsi",
+ .class = &omap44xx_hsi_hwmod_class,
++ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap44xx_hsi_irqs,
+ .main_clk = "hsi_fck",
+ .prcm = {
+@@ -2209,6 +2240,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &omap44xx_i2c_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c1_irqs,
+ .sdma_reqs = omap44xx_i2c1_sdma_reqs,
+@@ -2263,6 +2295,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &omap44xx_i2c_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c2_irqs,
+ .sdma_reqs = omap44xx_i2c2_sdma_reqs,
+@@ -2317,6 +2350,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &omap44xx_i2c_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c3_irqs,
+ .sdma_reqs = omap44xx_i2c3_sdma_reqs,
+@@ -2371,6 +2405,7 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &omap44xx_i2c_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap44xx_i2c4_irqs,
+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
+@@ -2435,6 +2470,7 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
+ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+ .name = "ipu_c0",
+ .class = &omap44xx_ipu_hwmod_class,
++ .clkdm_name = "ducati_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_ipu_c0_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
+@@ -2450,6 +2486,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+ .name = "ipu_c1",
+ .class = &omap44xx_ipu_hwmod_class,
++ .clkdm_name = "ducati_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_ipu_c1_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
+@@ -2464,6 +2501,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .name = "ipu",
+ .class = &omap44xx_ipu_hwmod_class,
++ .clkdm_name = "ducati_clkdm",
+ .mpu_irqs = omap44xx_ipu_irqs,
+ .rst_lines = omap44xx_ipu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
+@@ -2551,6 +2589,7 @@ static struct omap_hwmod_opt_clk iss_opt_clks[] = {
+ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .name = "iss",
+ .class = &omap44xx_iss_hwmod_class,
++ .clkdm_name = "iss_clkdm",
+ .mpu_irqs = omap44xx_iss_irqs,
+ .sdma_reqs = omap44xx_iss_sdma_reqs,
+ .main_clk = "iss_fck",
+@@ -2631,6 +2670,7 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
+ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
+ .name = "iva_seq0",
+ .class = &omap44xx_iva_hwmod_class,
++ .clkdm_name = "ivahd_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_iva_seq0_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
+@@ -2646,6 +2686,7 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
+ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
+ .name = "iva_seq1",
+ .class = &omap44xx_iva_hwmod_class,
++ .clkdm_name = "ivahd_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .rst_lines = omap44xx_iva_seq1_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
+@@ -2660,6 +2701,7 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
+ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .name = "iva",
+ .class = &omap44xx_iva_hwmod_class,
++ .clkdm_name = "ivahd_clkdm",
+ .mpu_irqs = omap44xx_iva_irqs,
+ .rst_lines = omap44xx_iva_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
+@@ -2732,6 +2774,7 @@ static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
+ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .name = "kbd",
+ .class = &omap44xx_kbd_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = omap44xx_kbd_irqs,
+ .main_clk = "kbd_fck",
+ .prcm = {
+@@ -2797,6 +2840,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap44xx_mailbox_hwmod_class,
++ .clkdm_name = "l4_cfg_clkdm",
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .prcm = {
+ .omap4 = {
+@@ -2887,6 +2931,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
+ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap44xx_mcbsp_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcbsp1_irqs,
+ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+@@ -2960,6 +3005,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
+ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap44xx_mcbsp_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcbsp2_irqs,
+ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
+@@ -3033,6 +3079,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
+ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap44xx_mcbsp_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcbsp3_irqs,
+ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
+ .main_clk = "mcbsp3_fck",
+@@ -3085,6 +3132,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
+ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap44xx_mcbsp_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mcbsp4_irqs,
+ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
+ .main_clk = "mcbsp4_fck",
+@@ -3177,6 +3225,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
+ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .name = "mcpdm",
+ .class = &omap44xx_mcpdm_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcpdm_irqs,
+ .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
+ .main_clk = "mcpdm_fck",
+@@ -3262,6 +3311,7 @@ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &omap44xx_mcspi_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mcspi1_irqs,
+ .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+@@ -3322,6 +3372,7 @@ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &omap44xx_mcspi_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mcspi2_irqs,
+ .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
+@@ -3382,6 +3433,7 @@ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &omap44xx_mcspi_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mcspi3_irqs,
+ .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
+ .main_clk = "mcspi3_fck",
+@@ -3440,6 +3492,7 @@ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &omap44xx_mcspi_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mcspi4_irqs,
+ .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
+ .main_clk = "mcspi4_fck",
+@@ -3524,6 +3577,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &omap44xx_mmc_hwmod_class,
++ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap44xx_mmc1_irqs,
+ .sdma_reqs = omap44xx_mmc1_sdma_reqs,
+ .main_clk = "mmc1_fck",
+@@ -3583,6 +3637,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
+ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .name = "mmc2",
+ .class = &omap44xx_mmc_hwmod_class,
++ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap44xx_mmc2_irqs,
+ .sdma_reqs = omap44xx_mmc2_sdma_reqs,
+ .main_clk = "mmc2_fck",
+@@ -3637,6 +3692,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
+ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .name = "mmc3",
+ .class = &omap44xx_mmc_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mmc3_irqs,
+ .sdma_reqs = omap44xx_mmc3_sdma_reqs,
+ .main_clk = "mmc3_fck",
+@@ -3689,6 +3745,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
+ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .name = "mmc4",
+ .class = &omap44xx_mmc_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mmc4_irqs,
+
+ .sdma_reqs = omap44xx_mmc4_sdma_reqs,
+@@ -3742,6 +3799,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
+ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .name = "mmc5",
+ .class = &omap44xx_mmc_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_mmc5_irqs,
+ .sdma_reqs = omap44xx_mmc5_sdma_reqs,
+ .main_clk = "mmc5_fck",
+@@ -3782,6 +3840,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
+ static struct omap_hwmod omap44xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &omap44xx_mpu_hwmod_class,
++ .clkdm_name = "mpuss_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+@@ -3854,6 +3913,7 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .name = "smartreflex_core",
+ .class = &omap44xx_smartreflex_hwmod_class,
++ .clkdm_name = "l4_ao_clkdm",
+ .mpu_irqs = omap44xx_smartreflex_core_irqs,
+
+ .main_clk = "smartreflex_core_fck",
+@@ -3901,6 +3961,7 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .name = "smartreflex_iva",
+ .class = &omap44xx_smartreflex_hwmod_class,
++ .clkdm_name = "l4_ao_clkdm",
+ .mpu_irqs = omap44xx_smartreflex_iva_irqs,
+ .main_clk = "smartreflex_iva_fck",
+ .vdd_name = "iva",
+@@ -3947,6 +4008,7 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ .name = "smartreflex_mpu",
+ .class = &omap44xx_smartreflex_hwmod_class,
++ .clkdm_name = "l4_ao_clkdm",
+ .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
+ .main_clk = "smartreflex_mpu_fck",
+ .vdd_name = "mpu",
+@@ -4011,6 +4073,7 @@ static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
+ static struct omap_hwmod omap44xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &omap44xx_spinlock_hwmod_class,
++ .clkdm_name = "l4_cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+@@ -4092,6 +4155,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .prcm = {
+@@ -4137,6 +4201,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &omap44xx_timer_1ms_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+@@ -4182,6 +4247,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
+ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .prcm = {
+@@ -4227,6 +4293,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
+ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+@@ -4291,6 +4358,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
+ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+@@ -4355,6 +4423,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
+ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_timer6_irqs,
+
+ .main_clk = "timer6_fck",
+@@ -4420,6 +4489,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
+ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+@@ -4484,6 +4554,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
+ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_timer8_irqs,
+ .main_clk = "timer8_fck",
+ .prcm = {
+@@ -4529,6 +4600,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
+ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer9_irqs,
+ .main_clk = "timer9_fck",
+ .prcm = {
+@@ -4574,6 +4646,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
+ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &omap44xx_timer_1ms_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer10_irqs,
+ .main_clk = "timer10_fck",
+ .prcm = {
+@@ -4619,6 +4692,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
+ static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &omap44xx_timer_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer11_irqs,
+ .main_clk = "timer11_fck",
+ .prcm = {
+@@ -4692,6 +4766,7 @@ static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
+ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &omap44xx_uart_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_uart1_irqs,
+ .sdma_reqs = omap44xx_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+@@ -4744,6 +4819,7 @@ static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
+ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &omap44xx_uart_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_uart2_irqs,
+ .sdma_reqs = omap44xx_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
+@@ -4796,6 +4872,7 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &omap44xx_uart_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_uart3_irqs,
+ .sdma_reqs = omap44xx_uart3_sdma_reqs,
+@@ -4849,6 +4926,7 @@ static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
+ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &omap44xx_uart_hwmod_class,
++ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_uart4_irqs,
+ .sdma_reqs = omap44xx_uart4_sdma_reqs,
+ .main_clk = "uart4_fck",
+@@ -4927,6 +5005,7 @@ static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
+ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &omap44xx_usb_otg_hs_hwmod_class,
++ .clkdm_name = "l3_init_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
+ .main_clk = "usb_otg_hs_ick",
+@@ -5000,6 +5079,7 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
+ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &omap44xx_wd_timer_hwmod_class,
++ .clkdm_name = "l4_wkup_clkdm",
+ .mpu_irqs = omap44xx_wd_timer2_irqs,
+ .main_clk = "wd_timer2_fck",
+ .prcm = {
+@@ -5064,6 +5144,7 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+ .name = "wd_timer3",
+ .class = &omap44xx_wd_timer_hwmod_class,
++ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_wd_timer3_irqs,
+ .main_clk = "wd_timer3_fck",
+ .prcm = {
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index fafdfe3..21d3922 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -515,6 +515,7 @@ struct omap_hwmod {
+ const char *main_clk;
+ struct clk *_clk;
+ struct omap_hwmod_opt_clk *opt_clks;
++ char *clkdm_name;
+ char *vdd_name;
+ struct voltagedomain *voltdm;
+ struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0078-OMAP2-hwmod-Init-clkdm-field-at-boot-time.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0078-OMAP2-hwmod-Init-clkdm-field-at-boot-time.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0078-OMAP2-hwmod-Init-clkdm-field-at-boot-time.patch
@@ -0,0 +1,86 @@
+From 170e760ecb809025c72181910b911bb820f7a8fb Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:30 -0600
+Subject: [PATCH 078/149] OMAP2+: hwmod: Init clkdm field at boot time
+
+At boot time, lookup the clkdm_name to get the clkdm
+structure pointer for further usage.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 34 +++++++++++++++++++++++++-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 2 files changed, 34 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 02b6016..1f6f47f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -990,9 +990,40 @@ static struct omap_hwmod *_lookup(const char *name)
+
+ return oh;
+ }
++/**
++ * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
++ * @oh: struct omap_hwmod *
++ *
++ * Convert a clockdomain name stored in a struct omap_hwmod into a
++ * clockdomain pointer, and save it into the struct omap_hwmod.
++ * return -EINVAL if clkdm_name does not exist or if the lookup failed.
++ */
++static int _init_clkdm(struct omap_hwmod *oh)
++{
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ return 0;
++
++ if (!oh->clkdm_name) {
++ pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
++ return -EINVAL;
++ }
++
++ oh->clkdm = clkdm_lookup(oh->clkdm_name);
++ if (!oh->clkdm) {
++ pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
++ oh->name, oh->clkdm_name);
++ return -EINVAL;
++ }
++
++ pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
++ oh->name, oh->clkdm_name);
++
++ return 0;
++}
+
+ /**
+- * _init_clocks - clk_get() all clocks associated with this hwmod
++ * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
++ * well the clockdomain.
+ * @oh: struct omap_hwmod *
+ * @data: not used; pass NULL
+ *
+@@ -1012,6 +1043,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
+ ret |= _init_main_clk(oh);
+ ret |= _init_interface_clks(oh);
+ ret |= _init_opt_clks(oh);
++ ret |= _init_clkdm(oh);
+
+ if (!ret)
+ oh->_state = _HWMOD_STATE_CLKS_INITED;
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 21d3922..3306bdf 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -516,6 +516,7 @@ struct omap_hwmod {
+ struct clk *_clk;
+ struct omap_hwmod_opt_clk *opt_clks;
+ char *clkdm_name;
++ struct clockdomain *clkdm;
+ char *vdd_name;
+ struct voltagedomain *voltdm;
+ struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0079-OMAP4-hwmod-Replace-CLKCTRL-absolute-address-with-of.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0079-OMAP4-hwmod-Replace-CLKCTRL-absolute-address-with-of.patch
--- /dev/null
@@ -0,0 +1,976 @@
+From 5fb6c6eb4bfd89aabacd76d9ebe98127981646cb Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:30 -0600
+Subject: [PATCH 079/149] OMAP4: hwmod: Replace CLKCTRL absolute address with offset macros
+
+The CLKCTRL register was accessed using an absolute address.
+The usage of hardcoded macros to calculate virtual address from physical
+one should be avoided as much as possible.
+The usage of a offset will allow future improvement like migration from
+the current architecture code toward a module driver.
+
+Update cm_xxx accessor, move definition to the proper header file and
+update copyrights.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Todd Poynor <toddpoynor@google.com>
+[paul@pwsan.com: renamed 'omap4_cm_' fns to 'omap4_cminst_'; removed empty
+ fn prototype section from cm44xx.h; incorporated comments from Todd;
+ documented some functions]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cm44xx.h | 8 +-
+ arch/arm/mach-omap2/cminst44xx.c | 87 ++++++++++---
+ arch/arm/mach-omap2/cminst44xx.h | 4 +-
+ arch/arm/mach-omap2/omap_hwmod.c | 12 ++-
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 182 ++++++++++++++++---------
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 +-
+ 6 files changed, 198 insertions(+), 97 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
+index 0b87ec8..3380bee 100644
+--- a/arch/arm/mach-omap2/cm44xx.h
++++ b/arch/arm/mach-omap2/cm44xx.h
+@@ -1,7 +1,7 @@
+ /*
+ * OMAP4 Clock Management (CM) definitions
+ *
+- * Copyright (C) 2007-2009 Texas Instruments, Inc.
++ * Copyright (C) 2007-2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+@@ -23,10 +23,4 @@
+ #define OMAP4_CM_CLKSTCTRL 0x0000
+ #define OMAP4_CM_STATICDEP 0x0004
+
+-/* Function prototypes */
+-# ifndef __ASSEMBLER__
+-
+-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
+-
+-# endif
+ #endif
+diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
+index a482bfa..9033dd4 100644
+--- a/arch/arm/mach-omap2/cminst44xx.c
++++ b/arch/arm/mach-omap2/cminst44xx.c
+@@ -2,6 +2,7 @@
+ * OMAP4 CM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -32,6 +33,22 @@
+ #include "prm44xx.h"
+ #include "prcm_mpu44xx.h"
+
++/*
++ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
++ *
++ * 0x0 func: Module is fully functional, including OCP
++ * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
++ * abortion
++ * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
++ * using separate functional clock
++ * 0x3 disabled: Module is disabled and cannot be accessed
++ *
++ */
++#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
++#define CLKCTRL_IDLEST_INTRANSITION 0x1
++#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
++#define CLKCTRL_IDLEST_DISABLED 0x3
++
+ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+ [OMAP4430_INVALID_PRCM_PARTITION] = 0,
+ [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
+@@ -41,6 +58,48 @@ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+ [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
+ };
+
++/* Private functions */
++
++/**
++ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
++ *
++ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
++ * bit 0.
++ */
++static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
++{
++ u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
++ v &= OMAP4430_IDLEST_MASK;
++ v >>= OMAP4430_IDLEST_SHIFT;
++ return v;
++}
++
++/**
++ * _is_module_ready - can module registers be accessed without causing an abort?
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
++ *
++ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
++ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
++ */
++static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
++{
++ u32 v;
++
++ v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
++
++ return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
++ v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
++}
++
++/* Public functions */
++
+ /* Read a register in a CM instance */
+ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+ {
+@@ -200,35 +259,27 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+ */
+
+ /**
+- * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
+- * @clkctrl_reg: CLKCTRL module address
++ * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+- *
+- * Module idle state:
+- * 0x0 func: Module is fully functional, including OCP
+- * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
+- * abortion
+- * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
+- * using separate functional clock
+- * 0x3 disabled: Module is disabled and cannot be accessed
+- *
+ */
+-int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
++int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
++ u16 clkctrl_offs)
+ {
+ int i = 0;
+
+- if (!clkctrl_reg)
++ if (!clkctrl_offs)
+ return 0;
+
+- omap_test_timeout((
+- ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
+- (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
+- OMAP4430_IDLEST_SHIFT) == 0x2)),
+- MAX_MODULE_READY_TIME, i);
++ omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
++ MAX_MODULE_READY_TIME, i);
+
+ return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+ }
+diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
+index 2b32c18..8eba2ae 100644
+--- a/arch/arm/mach-omap2/cminst44xx.h
++++ b/arch/arm/mach-omap2/cminst44xx.h
+@@ -17,6 +17,8 @@ extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
+ extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
+ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+
++extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
++
+ /*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+@@ -32,6 +34,4 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
+ extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
+ u32 mask);
+
+-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
+-
+ #endif
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 1f6f47f..00241ea 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -146,7 +146,7 @@
+ #include <plat/prcm.h>
+
+ #include "cm2xxx_3xxx.h"
+-#include "cm44xx.h"
++#include "cminst44xx.h"
+ #include "prm2xxx_3xxx.h"
+ #include "prm44xx.h"
+ #include "mux.h"
+@@ -1060,7 +1060,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
+ * Wait for a module @oh to leave slave idle. Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+- * appropriate *_cm_wait_module_ready() function.
++ * appropriate *_cm*_wait_module_ready() function.
+ */
+ static int _wait_target_ready(struct omap_hwmod *oh)
+ {
+@@ -1087,7 +1087,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
+ oh->prcm.omap2.idlest_reg_id,
+ oh->prcm.omap2.idlest_idle_bit);
+ } else if (cpu_is_omap44xx()) {
+- ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
++ if (!oh->clkdm)
++ return -EINVAL;
++
++ ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
++ oh->clkdm->cm_inst,
++ oh->clkdm->clkdm_offs,
++ oh->prcm.omap4.clkctrl_offs);
+ } else {
+ BUG();
+ };
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index becae45..00d7130 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -124,6 +124,11 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &omap44xx_dmm_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_dmm_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
+ .mpu_irqs = omap44xx_dmm_irqs,
+@@ -175,6 +180,11 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &omap44xx_emif_fw_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_emif_fw_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -215,6 +225,11 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_instr_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l3_instr_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -309,6 +324,11 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_1_clkdm",
+ .mpu_irqs = omap44xx_l3_main_1_irqs,
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -405,6 +425,11 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+ .name = "l3_main_2",
+ .class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_2_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l3_main_2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -456,6 +481,11 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+ .name = "l3_main_3",
+ .class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_instr_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l3_main_3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -514,6 +544,11 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+ .name = "l4_abe",
+ .class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "abe_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l4_abe_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -537,6 +572,11 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+ .name = "l4_cfg",
+ .class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l4_cfg_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -560,6 +600,11 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
+ .name = "l4_per",
+ .class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l4_per_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -583,6 +628,11 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
++ },
++ },
+ .slaves = omap44xx_l4_wkup_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -758,7 +808,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .main_clk = "aess_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_aess_slaves,
+@@ -788,7 +838,7 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = bandgap_opt_clks,
+@@ -848,7 +898,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_counter_32k_slaves,
+@@ -932,7 +982,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ .main_clk = "l3_div_ck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
+@@ -1026,7 +1076,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .main_clk = "dmic_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dmic_slaves,
+@@ -1110,7 +1160,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .main_clk = "dsp_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+ .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+ },
+ },
+@@ -1199,7 +1249,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+@@ -1303,7 +1353,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_dispc_opt_clks,
+@@ -1401,7 +1451,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_dsi1_opt_clks,
+@@ -1478,7 +1528,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_dsi2_opt_clks,
+@@ -1575,7 +1625,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_hdmi_opt_clks,
+@@ -1666,7 +1716,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = dss_rfbi_opt_clks,
+@@ -1736,7 +1786,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dss_venc_slaves,
+@@ -1815,7 +1865,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .main_clk = "gpio1_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+@@ -1869,7 +1919,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .main_clk = "gpio2_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+@@ -1923,7 +1973,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .main_clk = "gpio3_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+@@ -1977,7 +2027,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .main_clk = "gpio4_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+@@ -2031,7 +2081,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .main_clk = "gpio5_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+@@ -2085,7 +2135,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .main_clk = "gpio6_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+@@ -2164,7 +2214,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .main_clk = "hsi_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_hsi_slaves,
+@@ -2247,7 +2297,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c1_slaves,
+@@ -2302,7 +2352,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c2_slaves,
+@@ -2357,7 +2407,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .main_clk = "i2c3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c3_slaves,
+@@ -2412,7 +2462,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .main_clk = "i2c4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c4_slaves,
+@@ -2508,7 +2558,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .main_clk = "ipu_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ },
+ },
+@@ -2595,7 +2645,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .main_clk = "iss_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = iss_opt_clks,
+@@ -2708,7 +2758,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .main_clk = "iva_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+ },
+ },
+@@ -2779,7 +2829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .main_clk = "kbd_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_kbd_slaves,
+@@ -2844,7 +2894,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+@@ -2937,7 +2987,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp1_slaves,
+@@ -3011,7 +3061,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp2_slaves,
+@@ -3085,7 +3135,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp3_slaves,
+@@ -3138,7 +3188,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .main_clk = "mcbsp4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp4_slaves,
+@@ -3231,7 +3281,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .main_clk = "mcpdm_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcpdm_slaves,
+@@ -3317,7 +3367,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+@@ -3378,7 +3428,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+@@ -3439,7 +3489,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+@@ -3498,7 +3548,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .main_clk = "mcspi4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+@@ -3583,7 +3633,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .main_clk = "mmc1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ },
+ },
+ .dev_attr = &mmc1_dev_attr,
+@@ -3643,7 +3693,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .main_clk = "mmc2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc2_slaves,
+@@ -3698,7 +3748,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .main_clk = "mmc3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc3_slaves,
+@@ -3752,7 +3802,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .main_clk = "mmc4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc4_slaves,
+@@ -3805,7 +3855,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .main_clk = "mmc5_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc5_slaves,
+@@ -3846,7 +3896,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
+ },
+ },
+ .masters = omap44xx_mpu_masters,
+@@ -3920,7 +3970,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .vdd_name = "core",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_core_slaves,
+@@ -3967,7 +4017,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .vdd_name = "iva",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_iva_slaves,
+@@ -4014,7 +4064,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ .vdd_name = "mpu",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_mpu_slaves,
+@@ -4076,7 +4126,7 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
+ .clkdm_name = "l4_cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_spinlock_slaves,
+@@ -4160,7 +4210,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+@@ -4206,7 +4256,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer2_slaves,
+@@ -4252,7 +4302,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer3_slaves,
+@@ -4298,7 +4348,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer4_slaves,
+@@ -4363,7 +4413,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer5_slaves,
+@@ -4429,7 +4479,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer6_slaves,
+@@ -4494,7 +4544,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer7_slaves,
+@@ -4559,7 +4609,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .main_clk = "timer8_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer8_slaves,
+@@ -4605,7 +4655,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .main_clk = "timer9_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer9_slaves,
+@@ -4651,7 +4701,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .main_clk = "timer10_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer10_slaves,
+@@ -4697,7 +4747,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .main_clk = "timer11_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer11_slaves,
+@@ -4772,7 +4822,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart1_slaves,
+@@ -4825,7 +4875,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart2_slaves,
+@@ -4879,7 +4929,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart3_slaves,
+@@ -4932,7 +4982,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .main_clk = "uart4_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart4_slaves,
+@@ -5011,7 +5061,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .main_clk = "usb_otg_hs_ick",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+@@ -5084,7 +5134,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ .main_clk = "wd_timer2_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_wd_timer2_slaves,
+@@ -5149,7 +5199,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+ .main_clk = "wd_timer3_fck",
+ .prcm = {
+ .omap4 = {
+- .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
++ .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_wd_timer3_slaves,
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 3306bdf..fc54355 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -360,7 +360,7 @@ struct omap_hwmod_omap2_prcm {
+ * @submodule_wkdep_bit: bit shift of the WKDEP range
+ */
+ struct omap_hwmod_omap4_prcm {
+- void __iomem *clkctrl_reg;
++ u16 clkctrl_offs;
+ void __iomem *rstctrl_reg;
+ u8 submodule_wkdep_bit;
+ };
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0080-OMAP-hwmod-Wait-the-idle-status-to-be-disabled.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0080-OMAP-hwmod-Wait-the-idle-status-to-be-disabled.patch
--- /dev/null
@@ -0,0 +1,153 @@
+From 32e2bca3815da5f1394f5e532acf3d9fd44362f6 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:30 -0600
+Subject: [PATCH 080/149] OMAP: hwmod: Wait the idle status to be disabled
+
+It is mandatory to wait for a module to be in disabled state before
+potentially disabling source clock or re-asserting a reset.
+
+omap_hwmod_idle and omap_hwmod_shutdown does not wait for
+the module to be fully idle.
+
+Add a cm_xxx accessor to wait the clkctrl idle status to be disabled.
+Fix hwmod_[idle|shutdown] to use this API.
+
+Based on Rajendra's initial patch.
+
+Please note that most interconnects hwmod will return one timeout because
+it is impossible for them to be in idle since the processor is accessing
+the registers though the interconnect.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Todd Poynor <toddpoynor@google.com>
+[paul@pwsan.com: move cpu_is_*() tests to the top of _wait_target_disable();
+ incorporate some feedback from Todd]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cminst44xx.c | 25 +++++++++++++++++++++++
+ arch/arm/mach-omap2/cminst44xx.h | 1 +
+ arch/arm/mach-omap2/omap_hwmod.c | 40 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 66 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
+index 9033dd4..0fe3f14 100644
+--- a/arch/arm/mach-omap2/cminst44xx.c
++++ b/arch/arm/mach-omap2/cminst44xx.c
+@@ -284,3 +284,28 @@ int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+ return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+ }
+
++/**
++ * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
++ * state
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
++ *
++ * Wait for the module IDLEST to be disabled. Some PRCM transition,
++ * like reset assertion or parent clock de-activation must wait the
++ * module to be fully disabled.
++ */
++int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
++{
++ int i = 0;
++
++ if (!clkctrl_offs)
++ return 0;
++
++ omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
++ CLKCTRL_IDLEST_DISABLED),
++ MAX_MODULE_READY_TIME, i);
++
++ return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
++}
+diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
+index 8eba2ae..a985400 100644
+--- a/arch/arm/mach-omap2/cminst44xx.h
++++ b/arch/arm/mach-omap2/cminst44xx.h
+@@ -18,6 +18,7 @@ extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
+ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+
+ extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
++extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
+ /*
+ * In an ideal world, we would not export these low-level functions,
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 00241ea..d21f49b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1102,6 +1102,36 @@ static int _wait_target_ready(struct omap_hwmod *oh)
+ }
+
+ /**
++ * _wait_target_disable - wait for a module to be disabled
++ * @oh: struct omap_hwmod *
++ *
++ * Wait for a module @oh to enter slave idle. Returns 0 if the module
++ * does not have an IDLEST bit or if the module successfully enters
++ * slave idle; otherwise, pass along the return value of the
++ * appropriate *_cm*_wait_module_idle() function.
++ */
++static int _wait_target_disable(struct omap_hwmod *oh)
++{
++ /* TODO: For now just handle OMAP4+ */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ return 0;
++
++ if (!oh)
++ return -EINVAL;
++
++ if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
++ return 0;
++
++ if (oh->flags & HWMOD_NO_IDLEST)
++ return 0;
++
++ return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
++ oh->clkdm->cm_inst,
++ oh->clkdm->clkdm_offs,
++ oh->prcm.omap4.clkctrl_offs);
++}
++
++/**
+ * _lookup_hardreset - fill register bit info for this hwmod/reset line
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line in the context of this hwmod
+@@ -1410,6 +1440,8 @@ static int _enable(struct omap_hwmod *oh)
+ */
+ static int _idle(struct omap_hwmod *oh)
+ {
++ int ret;
++
+ pr_debug("omap_hwmod: %s: idling\n", oh->name);
+
+ if (oh->_state != _HWMOD_STATE_ENABLED) {
+@@ -1422,6 +1454,10 @@ static int _idle(struct omap_hwmod *oh)
+ _idle_sysc(oh);
+ _del_initiator_dep(oh, mpu_oh);
+ _disable_clocks(oh);
++ ret = _wait_target_disable(oh);
++ if (ret)
++ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
++ oh->name);
+
+ /* Mux pins for device idle if populated */
+ if (oh->mux && oh->mux->pads_dynamic)
+@@ -1514,6 +1550,10 @@ static int _shutdown(struct omap_hwmod *oh)
+ _del_initiator_dep(oh, mpu_oh);
+ /* XXX what about the other system initiators here? dma, dsp */
+ _disable_clocks(oh);
++ ret = _wait_target_disable(oh);
++ if (ret)
++ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
++ oh->name);
+ }
+ /* XXX Should this code also force-disable the optional clocks? */
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0081-OMAP4-hwmod-Replace-RSTCTRL-absolute-address-with-of.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0081-OMAP4-hwmod-Replace-RSTCTRL-absolute-address-with-of.patch
--- /dev/null
@@ -0,0 +1,459 @@
+From c3b3634ca116bd50797a834a128bd70a79e83202 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:31 -0600
+Subject: [PATCH 081/149] OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros
+
+The RSTCTRL register was accessed using an absolute address.
+The usage of hardcoded macros to calculate virtual address from physical
+one should be avoided as much as possible.
+The usage of an offset will allow future improvement like migration from
+the current architecture code toward a module driver.
+
+Update prm_xxx accessors, move definition to the proper header file and
+update copyrights.
+Change the s16 register offset parameter to u16.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: use '_prminst_' in function names that are part of the
+ prminst44xx.c file]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 19 ++++--
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 16 ++--
+ arch/arm/mach-omap2/prm44xx.c | 93 +-------------------------
+ arch/arm/mach-omap2/prm44xx.h | 4 -
+ arch/arm/mach-omap2/prminst44xx.c | 93 +++++++++++++++++++++++++-
+ arch/arm/mach-omap2/prminst44xx.h | 10 +++-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 +-
+ 7 files changed, 125 insertions(+), 113 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index d21f49b..a0f7d31 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -149,6 +149,7 @@
+ #include "cminst44xx.h"
+ #include "prm2xxx_3xxx.h"
+ #include "prm44xx.h"
++#include "prminst44xx.h"
+ #include "mux.h"
+
+ /* Maximum microseconds to wait for OMAP module to softreset */
+@@ -1187,8 +1188,10 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+ return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+ ohri.rst_shift);
+ else if (cpu_is_omap44xx())
+- return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
+- ohri.rst_shift);
++ return omap4_prminst_assert_hardreset(ohri.rst_shift,
++ oh->clkdm->pwrdm.ptr->prcm_partition,
++ oh->clkdm->pwrdm.ptr->prcm_offs,
++ oh->prcm.omap4.rstctrl_offs);
+ else
+ return -EINVAL;
+ }
+@@ -1223,8 +1226,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+ if (ohri.st_shift)
+ pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+ oh->name, name);
+- ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
+- ohri.rst_shift);
++ ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
++ oh->clkdm->pwrdm.ptr->prcm_partition,
++ oh->clkdm->pwrdm.ptr->prcm_offs,
++ oh->prcm.omap4.rstctrl_offs);
+ } else {
+ return -EINVAL;
+ }
+@@ -1259,8 +1264,10 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+ return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+ ohri.st_shift);
+ } else if (cpu_is_omap44xx()) {
+- return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
+- ohri.rst_shift);
++ return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
++ oh->clkdm->pwrdm.ptr->prcm_partition,
++ oh->clkdm->pwrdm.ptr->prcm_offs,
++ oh->prcm.omap4.rstctrl_offs);
+ } else {
+ return -EINVAL;
+ }
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 00d7130..6a190f5 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -1144,7 +1144,7 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
+ .prcm = {
+ .omap4 = {
+- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+ },
+ },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -1161,7 +1161,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dsp_slaves,
+@@ -2526,7 +2526,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
+ .prcm = {
+ .omap4 = {
+- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ },
+ },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -2542,7 +2542,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
+ .prcm = {
+ .omap4 = {
+- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ },
+ },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -2559,7 +2559,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_ipu_slaves,
+@@ -2726,7 +2726,7 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
+ .prcm = {
+ .omap4 = {
+- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+ },
+ },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -2742,7 +2742,7 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
+ .prcm = {
+ .omap4 = {
+- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+ },
+ },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -2759,7 +2759,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
++ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+ },
+ },
+ .slaves = omap44xx_iva_slaves,
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index a2a04bf..faec860 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -1,7 +1,7 @@
+ /*
+ * OMAP4 PRM module functions
+ *
+- * Copyright (C) 2010 Texas Instruments, Inc.
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+@@ -24,12 +24,6 @@
+ #include "prm44xx.h"
+ #include "prm-regbits-44xx.h"
+
+-/*
+- * Address offset (in bytes) between the reset control and the reset
+- * status registers: 4 bytes on OMAP4
+- */
+-#define OMAP4_RST_CTRL_ST_OFFSET 4
+-
+ /* PRM low-level functions */
+
+ /* Read a register in a CM/PRM instance in the PRM module */
+@@ -94,91 +88,6 @@ u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+ return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
+ }
+
+-/**
+- * omap4_prm_is_hardreset_asserted - read the HW reset line state of
+- * submodules contained in the hwmod module
+- * @rstctrl_reg: RM_RSTCTRL register address for this module
+- * @shift: register bit shift corresponding to the reset line to check
+- *
+- * Returns 1 if the (sub)module hardreset line is currently asserted,
+- * 0 if the (sub)module hardreset line is not currently asserted, or
+- * -EINVAL upon parameter error.
+- */
+-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
+-{
+- if (!cpu_is_omap44xx() || !rstctrl_reg)
+- return -EINVAL;
+-
+- return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
+-}
+-
+-/**
+- * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
+- * @rstctrl_reg: RM_RSTCTRL register address for this module
+- * @shift: register bit shift corresponding to the reset line to assert
+- *
+- * Some IPs like dsp, ipu or iva contain processors that require an HW
+- * reset line to be asserted / deasserted in order to fully enable the
+- * IP. These modules may have multiple hard-reset lines that reset
+- * different 'submodules' inside the IP block. This function will
+- * place the submodule into reset. Returns 0 upon success or -EINVAL
+- * upon an argument error.
+- */
+-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+-{
+- u32 mask;
+-
+- if (!cpu_is_omap44xx() || !rstctrl_reg)
+- return -EINVAL;
+-
+- mask = 1 << shift;
+- omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
+-
+- return 0;
+-}
+-
+-/**
+- * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+- * @rstctrl_reg: RM_RSTCTRL register address for this module
+- * @shift: register bit shift corresponding to the reset line to deassert
+- *
+- * Some IPs like dsp, ipu or iva contain processors that require an HW
+- * reset line to be asserted / deasserted in order to fully enable the
+- * IP. These modules may have multiple hard-reset lines that reset
+- * different 'submodules' inside the IP block. This function will
+- * take the submodule out of reset and wait until the PRCM indicates
+- * that the reset has completed before returning. Returns 0 upon success or
+- * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+- * of reset, or -EBUSY if the submodule did not exit reset promptly.
+- */
+-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+-{
+- u32 mask;
+- void __iomem *rstst_reg;
+- int c;
+-
+- if (!cpu_is_omap44xx() || !rstctrl_reg)
+- return -EINVAL;
+-
+- rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
+-
+- mask = 1 << shift;
+-
+- /* Check the current status to avoid de-asserting the line twice */
+- if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
+- return -EEXIST;
+-
+- /* Clear the reset status by writing 1 to the status bit */
+- omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
+- /* de-assert the reset control line */
+- omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
+- /* wait the status to be set */
+- omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
+- MAX_MODULE_HARDRESET_WAIT, c);
+-
+- return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+-}
+-
+ void omap4_prm_global_warm_sw_reset(void)
+ {
+ u32 v;
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 6e53120..3732e02 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -755,10 +755,6 @@ extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+
+-extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
+-extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+-extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+-
+ extern void omap4_prm_global_warm_sw_reset(void);
+
+ # endif
+diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
+index a303242..35e02aa 100644
+--- a/arch/arm/mach-omap2/prminst44xx.c
++++ b/arch/arm/mach-omap2/prminst44xx.c
+@@ -2,6 +2,7 @@
+ * OMAP4 PRM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -53,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+
+ /* Read-modify-write a register in PRM. Caller must lock */
+ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+- s16 idx)
++ u16 idx)
+ {
+ u32 v;
+
+@@ -64,3 +65,93 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+
+ return v;
+ }
++
++/*
++ * Address offset (in bytes) between the reset control and the reset
++ * status registers: 4 bytes on OMAP4
++ */
++#define OMAP4_RST_CTRL_ST_OFFSET 4
++
++/**
++ * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
++ * submodules contained in the hwmod module
++ * @rstctrl_reg: RM_RSTCTRL register address for this module
++ * @shift: register bit shift corresponding to the reset line to check
++ *
++ * Returns 1 if the (sub)module hardreset line is currently asserted,
++ * 0 if the (sub)module hardreset line is not currently asserted, or
++ * -EINVAL upon parameter error.
++ */
++int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs)
++{
++ u32 v;
++
++ v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
++ v &= 1 << shift;
++ v >>= shift;
++
++ return v;
++}
++
++/**
++ * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
++ * @rstctrl_reg: RM_RSTCTRL register address for this module
++ * @shift: register bit shift corresponding to the reset line to assert
++ *
++ * Some IPs like dsp, ipu or iva contain processors that require an HW
++ * reset line to be asserted / deasserted in order to fully enable the
++ * IP. These modules may have multiple hard-reset lines that reset
++ * different 'submodules' inside the IP block. This function will
++ * place the submodule into reset. Returns 0 upon success or -EINVAL
++ * upon an argument error.
++ */
++int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs)
++{
++ u32 mask = 1 << shift;
++
++ omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
++
++ return 0;
++}
++
++/**
++ * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
++ * wait
++ * @rstctrl_reg: RM_RSTCTRL register address for this module
++ * @shift: register bit shift corresponding to the reset line to deassert
++ *
++ * Some IPs like dsp, ipu or iva contain processors that require an HW
++ * reset line to be asserted / deasserted in order to fully enable the
++ * IP. These modules may have multiple hard-reset lines that reset
++ * different 'submodules' inside the IP block. This function will
++ * take the submodule out of reset and wait until the PRCM indicates
++ * that the reset has completed before returning. Returns 0 upon success or
++ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
++ * of reset, or -EBUSY if the submodule did not exit reset promptly.
++ */
++int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs)
++{
++ int c;
++ u32 mask = 1 << shift;
++ u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
++
++ /* Check the current status to avoid de-asserting the line twice */
++ if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
++ rstctrl_offs) == 0)
++ return -EEXIST;
++
++ /* Clear the reset status by writing 1 to the status bit */
++ omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
++ rstst_offs);
++ /* de-assert the reset control line */
++ omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
++ /* wait the status to be set */
++ omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
++ rstst_offs),
++ MAX_MODULE_HARDRESET_WAIT, c);
++
++ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
++}
+diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
+index 02dd66d..c14ae29 100644
+--- a/arch/arm/mach-omap2/prminst44xx.h
++++ b/arch/arm/mach-omap2/prminst44xx.h
+@@ -2,6 +2,7 @@
+ * OMAP4 Power/Reset Management (PRM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -18,8 +19,15 @@
+ extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+ extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+ extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+- s16 inst, s16 idx);
++ s16 inst, u16 idx);
+
+ extern void omap4_prm_global_warm_sw_reset(void);
+
++extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs);
++extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs);
++extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
++ u16 rstctrl_offs);
++
+ #endif
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index fc54355..9ef4424 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -2,6 +2,7 @@
+ * omap_hwmod macros, structures
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
++ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * Created in collaboration with (alphabetical order): Benoît Cousson,
+@@ -361,7 +362,7 @@ struct omap_hwmod_omap2_prcm {
+ */
+ struct omap_hwmod_omap4_prcm {
+ u16 clkctrl_offs;
+- void __iomem *rstctrl_reg;
++ u16 rstctrl_offs;
+ u8 submodule_wkdep_bit;
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0082-OMAP4-prm-Replace-warm-reset-API-with-the-offset-bas.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0082-OMAP4-prm-Replace-warm-reset-API-with-the-offset-bas.patch
--- /dev/null
@@ -0,0 +1,125 @@
+From 44affcd067be1368401315e1eed6530cac5dd50a Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:31 -0600
+Subject: [PATCH 082/149] OMAP4: prm: Replace warm reset API with the offset based version
+
+The warm reset function was still using the obsolete API.
+Replace it by the new one and move the file to the proper c file.
+
+Change the function names to stick to the file convention as
+suggested by Paul Walmsley <paul@pwsan.com>:
+prm_xxx -> prminst_xxx
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/prcm.c | 2 +-
+ arch/arm/mach-omap2/prm44xx.c | 15 ---------------
+ arch/arm/mach-omap2/prm44xx.h | 2 --
+ arch/arm/mach-omap2/prminst44xx.c | 19 +++++++++++++++++++
+ arch/arm/mach-omap2/prminst44xx.h | 8 ++++----
+ 5 files changed, 24 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
+index 6be1438..2e40a5c 100644
+--- a/arch/arm/mach-omap2/prcm.c
++++ b/arch/arm/mach-omap2/prcm.c
+@@ -70,7 +70,7 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
+ prcm_offs = OMAP3430_GR_MOD;
+ omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
+ } else if (cpu_is_omap44xx()) {
+- omap4_prm_global_warm_sw_reset(); /* never returns */
++ omap4_prminst_global_warm_sw_reset(); /* never returns */
+ } else {
+ WARN_ON(1);
+ }
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index faec860..f815329 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -87,18 +87,3 @@ u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+ {
+ return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
+ }
+-
+-void omap4_prm_global_warm_sw_reset(void)
+-{
+- u32 v;
+-
+- v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+- OMAP4_RM_RSTCTRL);
+- v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
+- omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
+- OMAP4_RM_RSTCTRL);
+-
+- /* OCP barrier */
+- v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+- OMAP4_RM_RSTCTRL);
+-}
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 3732e02..725a6a8 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -755,8 +755,6 @@ extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+
+-extern void omap4_prm_global_warm_sw_reset(void);
+-
+ # endif
+
+ #endif
+diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
+index 35e02aa..3a7bab1 100644
+--- a/arch/arm/mach-omap2/prminst44xx.c
++++ b/arch/arm/mach-omap2/prminst44xx.c
+@@ -155,3 +155,22 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+
+ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+ }
++
++
++void omap4_prminst_global_warm_sw_reset(void)
++{
++ u32 v;
++
++ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST,
++ OMAP4_PRM_RSTCTRL_OFFSET);
++ v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
++ omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST,
++ OMAP4_PRM_RSTCTRL_OFFSET);
++
++ /* OCP barrier */
++ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST,
++ OMAP4_PRM_RSTCTRL_OFFSET);
++}
+diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
+index c14ae29..46f2efb 100644
+--- a/arch/arm/mach-omap2/prminst44xx.h
++++ b/arch/arm/mach-omap2/prminst44xx.h
+@@ -21,13 +21,13 @@ extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+ extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+ s16 inst, u16 idx);
+
+-extern void omap4_prm_global_warm_sw_reset(void);
++extern void omap4_prminst_global_warm_sw_reset(void);
+
+ extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+- u16 rstctrl_offs);
++ u16 rstctrl_offs);
+ extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+- u16 rstctrl_offs);
++ u16 rstctrl_offs);
+ extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+- u16 rstctrl_offs);
++ u16 rstctrl_offs);
+
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0083-OMAP4-prm-Remove-deprecated-functions.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0083-OMAP4-prm-Remove-deprecated-functions.patch
--- /dev/null
@@ -0,0 +1,81 @@
+From 50802cb78da0ca018fde257c7f09f1ca93feb2dd Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:31 -0600
+Subject: [PATCH 083/149] OMAP4: prm: Remove deprecated functions
+
+The new prminst_xxx accessors based on partition and offset
+is now used, so removed all the previous prcm_xxx accessors.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: remove fn prototypes also]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/prm44xx.c | 37 -------------------------------------
+ arch/arm/mach-omap2/prm44xx.h | 4 ----
+ 2 files changed, 0 insertions(+), 41 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index f815329..0016555 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -50,40 +50,3 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+
+ return v;
+ }
+-
+-/* Read a PRM register, AND it, and shift the result down to bit 0 */
+-/* XXX deprecated */
+-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
+-{
+- u32 v;
+-
+- v = __raw_readl(reg);
+- v &= mask;
+- v >>= __ffs(mask);
+-
+- return v;
+-}
+-
+-/* Read-modify-write a register in a PRM module. Caller must lock */
+-/* XXX deprecated */
+-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
+-{
+- u32 v;
+-
+- v = __raw_readl(reg);
+- v &= ~mask;
+- v |= bits;
+- __raw_writel(v, reg);
+-
+- return v;
+-}
+-
+-u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+-{
+- return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
+-}
+-
+-u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+-{
+- return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
+-}
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 725a6a8..7dfa379 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -750,10 +750,6 @@
+ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+ extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+-extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
+-extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+-extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+-extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+
+ # endif
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0084-OMAP4-hwmod-data-Add-PRM-context-register-offset.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0084-OMAP4-hwmod-data-Add-PRM-context-register-offset.patch
--- /dev/null
@@ -0,0 +1,630 @@
+From 4f1bf495d3eb576dd032b53cfc863017d6ea1fa2 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:32 -0600
+Subject: [PATCH 084/149] OMAP4: hwmod data: Add PRM context register offset
+
+Add a 'context_offs' entry in the prcm.omap4 structure to all
+IPs when applicable.
+The offset will be used to retrieve the per module context lost
+information now available on OMAP4.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 74 ++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 2 files changed, 75 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 6a190f5..d68ef2c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -127,6 +127,7 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dmm_slaves,
+@@ -183,6 +184,7 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_emif_fw_slaves,
+@@ -228,6 +230,7 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l3_instr_slaves,
+@@ -327,6 +330,7 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l3_main_1_slaves,
+@@ -428,6 +432,7 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l3_main_2_slaves,
+@@ -484,6 +489,7 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l3_main_3_slaves,
+@@ -575,6 +581,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l4_cfg_slaves,
+@@ -603,6 +610,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l4_per_slaves,
+@@ -631,6 +639,7 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_l4_wkup_slaves,
+@@ -809,6 +818,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_aess_slaves,
+@@ -899,6 +909,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_counter_32k_slaves,
+@@ -983,6 +994,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
+@@ -1077,6 +1089,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dmic_slaves,
+@@ -1162,6 +1175,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
++ .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dsp_slaves,
+@@ -1250,6 +1264,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+@@ -1354,6 +1369,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_dispc_opt_clks,
+@@ -1452,6 +1468,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_dsi1_opt_clks,
+@@ -1529,6 +1546,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_dsi2_opt_clks,
+@@ -1626,6 +1644,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_hdmi_opt_clks,
+@@ -1717,6 +1736,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = dss_rfbi_opt_clks,
+@@ -1787,6 +1807,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_dss_venc_slaves,
+@@ -1866,6 +1887,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+@@ -1920,6 +1942,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+@@ -1974,6 +1997,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+@@ -2028,6 +2052,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+@@ -2082,6 +2107,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+@@ -2136,6 +2162,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+@@ -2215,6 +2242,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_hsi_slaves,
+@@ -2298,6 +2326,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c1_slaves,
+@@ -2353,6 +2382,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c2_slaves,
+@@ -2408,6 +2438,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c3_slaves,
+@@ -2463,6 +2494,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_i2c4_slaves,
+@@ -2560,6 +2592,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
++ .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_ipu_slaves,
+@@ -2646,6 +2679,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = iss_opt_clks,
+@@ -2760,6 +2794,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
++ .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_iva_slaves,
+@@ -2830,6 +2865,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_kbd_slaves,
+@@ -2895,6 +2931,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+@@ -2988,6 +3025,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp1_slaves,
+@@ -3062,6 +3100,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp2_slaves,
+@@ -3136,6 +3175,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp3_slaves,
+@@ -3189,6 +3229,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcbsp4_slaves,
+@@ -3282,6 +3323,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mcpdm_slaves,
+@@ -3368,6 +3410,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+@@ -3429,6 +3472,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+@@ -3490,6 +3534,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+@@ -3549,6 +3594,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+@@ -3634,6 +3680,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &mmc1_dev_attr,
+@@ -3694,6 +3741,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc2_slaves,
+@@ -3749,6 +3797,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc3_slaves,
+@@ -3803,6 +3852,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc4_slaves,
+@@ -3856,6 +3906,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_mmc5_slaves,
+@@ -3897,6 +3948,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
+ },
+ },
+ .masters = omap44xx_mpu_masters,
+@@ -3971,6 +4023,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_core_slaves,
+@@ -4018,6 +4071,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_iva_slaves,
+@@ -4065,6 +4119,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_smartreflex_mpu_slaves,
+@@ -4127,6 +4182,7 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_spinlock_slaves,
+@@ -4211,6 +4267,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+@@ -4257,6 +4314,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer2_slaves,
+@@ -4303,6 +4361,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer3_slaves,
+@@ -4349,6 +4408,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer4_slaves,
+@@ -4414,6 +4474,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer5_slaves,
+@@ -4480,6 +4541,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer6_slaves,
+@@ -4545,6 +4607,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer7_slaves,
+@@ -4610,6 +4673,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer8_slaves,
+@@ -4656,6 +4720,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer9_slaves,
+@@ -4702,6 +4767,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer10_slaves,
+@@ -4748,6 +4814,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_timer11_slaves,
+@@ -4823,6 +4890,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart1_slaves,
+@@ -4876,6 +4944,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart2_slaves,
+@@ -4930,6 +4999,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart3_slaves,
+@@ -4983,6 +5053,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_uart4_slaves,
+@@ -5062,6 +5133,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+@@ -5135,6 +5207,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_wd_timer2_slaves,
+@@ -5200,6 +5273,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
++ .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
+ },
+ },
+ .slaves = omap44xx_wd_timer3_slaves,
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 9ef4424..16439fa 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -363,6 +363,7 @@ struct omap_hwmod_omap2_prcm {
+ struct omap_hwmod_omap4_prcm {
+ u16 clkctrl_offs;
+ u16 rstctrl_offs;
++ u16 context_offs;
+ u8 submodule_wkdep_bit;
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0085-OMAP4-hwmod-data-Add-modulemode-entry-in-omap_hwmod-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0085-OMAP4-hwmod-data-Add-modulemode-entry-in-omap_hwmod-.patch
--- /dev/null
@@ -0,0 +1,503 @@
+From fa4857f2e5301f905e097478542805af14dcf5fe Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:32 -0600
+Subject: [PATCH 085/149] OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure
+
+Add a new field to provide the mode supported by the module.
+The mode will control the way mandatory clocks are managed by the PRCM.
+
+ 0 : Module is temporarily disabled by SW. OCP access to module are stalled.
+ Can be used to change timing parameter of GPMC module.
+ 1 : Module is managed automatically by HW according to clock domain
+ transition. A clock domain sleep transition put module into idle.
+ A wakeup domain transition put it back into function.
+ If CLKTRCTRL=3, any OCP access to module is always granted.
+ Module clocks may be gated according to the clock domain state.
+ 2 : Module is explicitly enabled. Interface clock (if not used for
+ functions) may be gated according to the clock domain state.
+ Functional clocks are guarantied to stay present. As long as
+ in this configuration, power domain sleep transition cannot happen.
+
+Some modules will have a modulemode initialized at 1 (HWCTRL) by default.
+This is the case for interconnect and simple module like GPIO, WDT, MAILBOX.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 55 ++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 +++
+ 2 files changed, 61 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index d68ef2c..6201422 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -231,6 +231,7 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_l3_instr_slaves,
+@@ -490,6 +491,7 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_l3_main_3_slaves,
+@@ -819,6 +821,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_aess_slaves,
+@@ -1090,6 +1093,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_dmic_slaves,
+@@ -1176,6 +1180,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
+ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_dsp_slaves,
+@@ -1888,6 +1893,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+@@ -1943,6 +1949,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+@@ -1998,6 +2005,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+@@ -2053,6 +2061,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+@@ -2108,6 +2117,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+@@ -2163,6 +2173,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+@@ -2243,6 +2254,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_hsi_slaves,
+@@ -2327,6 +2339,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c1_slaves,
+@@ -2383,6 +2396,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c2_slaves,
+@@ -2439,6 +2453,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c3_slaves,
+@@ -2495,6 +2510,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_i2c4_slaves,
+@@ -2593,6 +2609,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_ipu_slaves,
+@@ -2680,6 +2697,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = iss_opt_clks,
+@@ -2795,6 +2813,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .slaves = omap44xx_iva_slaves,
+@@ -2866,6 +2885,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_kbd_slaves,
+@@ -3026,6 +3046,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mcbsp1_slaves,
+@@ -3101,6 +3122,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mcbsp2_slaves,
+@@ -3176,6 +3198,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mcbsp3_slaves,
+@@ -3230,6 +3253,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mcbsp4_slaves,
+@@ -3324,6 +3348,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mcpdm_slaves,
+@@ -3411,6 +3436,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+@@ -3473,6 +3499,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+@@ -3535,6 +3562,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+@@ -3595,6 +3623,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+@@ -3681,6 +3710,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mmc1_dev_attr,
+@@ -3742,6 +3772,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mmc2_slaves,
+@@ -3798,6 +3829,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mmc3_slaves,
+@@ -3853,6 +3885,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mmc4_slaves,
+@@ -3907,6 +3940,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_mmc5_slaves,
+@@ -4024,6 +4058,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_smartreflex_core_slaves,
+@@ -4072,6 +4107,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_smartreflex_iva_slaves,
+@@ -4120,6 +4156,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_smartreflex_mpu_slaves,
+@@ -4268,6 +4305,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+@@ -4315,6 +4353,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer2_slaves,
+@@ -4362,6 +4401,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer3_slaves,
+@@ -4409,6 +4449,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer4_slaves,
+@@ -4475,6 +4516,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer5_slaves,
+@@ -4542,6 +4584,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer6_slaves,
+@@ -4608,6 +4651,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer7_slaves,
+@@ -4674,6 +4718,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer8_slaves,
+@@ -4721,6 +4766,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer9_slaves,
+@@ -4768,6 +4814,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer10_slaves,
+@@ -4815,6 +4862,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_timer11_slaves,
+@@ -4891,6 +4939,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_uart1_slaves,
+@@ -4945,6 +4994,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_uart2_slaves,
+@@ -5000,6 +5050,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_uart3_slaves,
+@@ -5054,6 +5105,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_uart4_slaves,
+@@ -5134,6 +5186,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+@@ -5208,6 +5261,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_wd_timer2_slaves,
+@@ -5274,6 +5328,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = omap44xx_wd_timer3_slaves,
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 16439fa..0e329ca 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -80,6 +80,11 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+ #define HWMOD_IDLEMODE_SMART (1 << 2)
+ #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
+
++/* modulemode control type (SW or HW) */
++#define MODULEMODE_HWCTRL 1
++#define MODULEMODE_SWCTRL 2
++
++
+ /**
+ * struct omap_hwmod_mux_info - hwmod specific mux configuration
+ * @pads: array of omap_device_pad entries
+@@ -365,6 +370,7 @@ struct omap_hwmod_omap4_prcm {
+ u16 rstctrl_offs;
+ u16 context_offs;
+ u8 submodule_wkdep_bit;
++ u8 modulemode;
+ };
+
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0086-OMAP4-cm-Add-two-new-APIs-for-modulemode-control.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0086-OMAP4-cm-Add-two-new-APIs-for-modulemode-control.patch
--- /dev/null
@@ -0,0 +1,88 @@
+From 6f1abf1ed445fa081f832cc4e112888b86f69054 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:32 -0600
+Subject: [PATCH 086/149] OMAP4: cm: Add two new APIs for modulemode control
+
+In OMAP4, a new programming model based on module control instead
+of clock control was introduced.
+Expose two APIs to allow the upper layer (omap_hwmod) to control
+the module mode independently of the parent clocks management.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: renamed 'omap4_cm_' fns to 'omap4_cminst_'; cleaned up
+ kerneldoc]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cminst44xx.c | 40 ++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/cminst44xx.h | 5 ++++
+ 2 files changed, 45 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
+index 0fe3f14..eb2a472 100644
+--- a/arch/arm/mach-omap2/cminst44xx.c
++++ b/arch/arm/mach-omap2/cminst44xx.c
+@@ -309,3 +309,43 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
+
+ return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+ }
++
++/**
++ * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
++ * @mode: Module mode (SW or HW)
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
++ *
++ * No return value.
++ */
++void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
++ u16 clkctrl_offs)
++{
++ u32 v;
++
++ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
++ v &= ~OMAP4430_MODULEMODE_MASK;
++ v |= mode << OMAP4430_MODULEMODE_SHIFT;
++ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
++}
++
++/**
++ * omap4_cminst_module_disable - Disable the module inside CLKCTRL
++ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
++ * @inst: CM instance register offset (*_INST macro)
++ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
++ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
++ *
++ * No return value.
++ */
++void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
++ u16 clkctrl_offs)
++{
++ u32 v;
++
++ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
++ v &= ~OMAP4430_MODULEMODE_MASK;
++ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
++}
+diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
+index a985400..f2ea645 100644
+--- a/arch/arm/mach-omap2/cminst44xx.h
++++ b/arch/arm/mach-omap2/cminst44xx.h
+@@ -20,6 +20,11 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+ extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+ extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
++extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
++ u16 clkctrl_offs);
++extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
++ u16 clkctrl_offs);
++
+ /*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0087-OMAP4-hwmod-Introduce-the-module-control-in-hwmod-co.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0087-OMAP4-hwmod-Introduce-the-module-control-in-hwmod-co.patch
--- /dev/null
@@ -0,0 +1,129 @@
+From 08d7033937362297e45a4c5a691fc7e251fe9995 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:33 -0600
+Subject: [PATCH 087/149] OMAP4: hwmod: Introduce the module control in hwmod control
+
+Take advantage of the explicit modulemode control to fix
+the way parents clocks are managed.
+A module must be disabled before any parents are disabled.
+That programming model was not possible with the previous
+implementation that was considering a modulemode as a leaf
+clock node managed by the clock fmwk.
+This was leading to bad crash upon disable when the parent
+clock was gated before the module completed its transition
+to idle.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 63 ++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 61 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index a0f7d31..4424fee 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -680,6 +680,56 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
+ }
+
+ /**
++ * _enable_module - enable CLKCTRL modulemode on OMAP4
++ * @oh: struct omap_hwmod *
++ *
++ * Enables the PRCM module mode related to the hwmod @oh.
++ * No return value.
++ */
++static void _enable_module(struct omap_hwmod *oh)
++{
++ /* The module mode does not exist prior OMAP4 */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ return;
++
++ if (!oh->clkdm || !oh->prcm.omap4.modulemode)
++ return;
++
++ pr_debug("omap_hwmod: %s: _enable_module: %d\n",
++ oh->name, oh->prcm.omap4.modulemode);
++
++ omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
++ oh->clkdm->prcm_partition,
++ oh->clkdm->cm_inst,
++ oh->clkdm->clkdm_offs,
++ oh->prcm.omap4.clkctrl_offs);
++}
++
++/**
++ * _disable_module - enable CLKCTRL modulemode on OMAP4
++ * @oh: struct omap_hwmod *
++ *
++ * Disable the PRCM module mode related to the hwmod @oh.
++ * No return value.
++ */
++static void _disable_module(struct omap_hwmod *oh)
++{
++ /* The module mode does not exist prior OMAP4 */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ return;
++
++ if (!oh->clkdm || !oh->prcm.omap4.modulemode)
++ return;
++
++ pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
++
++ omap4_cminst_module_disable(oh->clkdm->prcm_partition,
++ oh->clkdm->cm_inst,
++ oh->clkdm->clkdm_offs,
++ oh->prcm.omap4.clkctrl_offs);
++}
++
++/**
+ * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
+ * @oh: struct omap_hwmod *oh
+ *
+@@ -1424,6 +1474,7 @@ static int _enable(struct omap_hwmod *oh)
+
+ return r;
+ }
++ _enable_module(oh);
+
+ oh->_state = _HWMOD_STATE_ENABLED;
+
+@@ -1460,11 +1511,18 @@ static int _idle(struct omap_hwmod *oh)
+ if (oh->class->sysc)
+ _idle_sysc(oh);
+ _del_initiator_dep(oh, mpu_oh);
+- _disable_clocks(oh);
++ _disable_module(oh);
+ ret = _wait_target_disable(oh);
+ if (ret)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
++ /*
++ * The module must be in idle mode before disabling any parents
++ * clocks. Otherwise, the parent clock might be disabled before
++ * the module transition is done, and thus will prevent the
++ * transition to complete properly.
++ */
++ _disable_clocks(oh);
+
+ /* Mux pins for device idle if populated */
+ if (oh->mux && oh->mux->pads_dynamic)
+@@ -1556,11 +1614,12 @@ static int _shutdown(struct omap_hwmod *oh)
+ if (oh->_state == _HWMOD_STATE_ENABLED) {
+ _del_initiator_dep(oh, mpu_oh);
+ /* XXX what about the other system initiators here? dma, dsp */
+- _disable_clocks(oh);
++ _disable_module(oh);
+ ret = _wait_target_disable(oh);
+ if (ret)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
++ _disable_clocks(oh);
+ }
+ /* XXX Should this code also force-disable the optional clocks? */
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0088-OMAP-clockdomain-Remove-redundant-call-to-pwrdm_wait.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0088-OMAP-clockdomain-Remove-redundant-call-to-pwrdm_wait.patch
--- /dev/null
@@ -0,0 +1,30 @@
+From e5d1984e1ae7e5171465645241697a2b950dcc95 Mon Sep 17 00:00:00 2001
+From: Vaibhav Bedia <vaibhav.bedia@ti.com>
+Date: Sun, 10 Jul 2011 05:56:53 -0600
+Subject: [PATCH 088/149] OMAP: clockdomain: Remove redundant call to pwrdm_wait_transition()
+
+The call to pwrdm_wait_transition() in clkdm_clk_enable()
+is redundant since the function pwrdm_clkdm_state_switch()
+which is called next also does the same thing.
+
+Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 6cb6c03..4fbbbfc 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -834,7 +834,6 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ clk->name);
+
+ arch_clkdm->clkdm_clk_enable(clkdm);
+- pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ pwrdm_clkdm_state_switch(clkdm);
+
+ return 0;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0089-OMAP2-clockdomain-Add-2-APIs-to-control-clockdomain-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0089-OMAP2-clockdomain-Add-2-APIs-to-control-clockdomain-.patch
--- /dev/null
@@ -0,0 +1,231 @@
+From a2518625f75160c7f7af57623178b38c3846c946 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Sun, 10 Jul 2011 05:56:54 -0600
+Subject: [PATCH 089/149] OMAP2+: clockdomain: Add 2 APIs to control clockdomain from hwmod framework
+
+Duplicate the existing API for clockdomain enable from clock to enable
+a clock domain from hwmod framework.
+This will be needed when the hwmod framework will move from the current
+clock centric approach to the module based approach.
+
+These APIs are returning 0 for the moment for OMAP2 and OMAP3 until
+their hwmods are updated with the clksm attribute.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 142 +++++++++++++++++++++++++++---------
+ arch/arm/mach-omap2/clockdomain.h | 3 +
+ 2 files changed, 109 insertions(+), 36 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 4fbbbfc..5a57de5 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -796,7 +796,50 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ }
+
+
+-/* Clockdomain-to-clock framework interface code */
++/* Clockdomain-to-clock/hwmod framework interface code */
++
++static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
++{
++ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
++ return -EINVAL;
++
++ /*
++ * For arch's with no autodeps, clkcm_clk_enable
++ * should be called for every clock instance or hwmod that is
++ * enabled, so the clkdm can be force woken up.
++ */
++ if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
++ return 0;
++
++ arch_clkdm->clkdm_clk_enable(clkdm);
++ pwrdm_wait_transition(clkdm->pwrdm.ptr);
++ pwrdm_clkdm_state_switch(clkdm);
++
++ pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
++
++ return 0;
++}
++
++static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
++{
++ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
++ return -EINVAL;
++
++ if (atomic_read(&clkdm->usecount) == 0) {
++ WARN_ON(1); /* underflow */
++ return -ERANGE;
++ }
++
++ if (atomic_dec_return(&clkdm->usecount) > 0)
++ return 0;
++
++ arch_clkdm->clkdm_clk_disable(clkdm);
++ pwrdm_clkdm_state_switch(clkdm);
++
++ pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
++
++ return 0;
++}
+
+ /**
+ * clkdm_clk_enable - add an enabled downstream clock to this clkdm
+@@ -819,24 +862,10 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ * downstream clocks for debugging purposes?
+ */
+
+- if (!clkdm || !clk)
++ if (!clk)
+ return -EINVAL;
+
+- if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+- return -EINVAL;
+-
+- if (atomic_inc_return(&clkdm->usecount) > 1)
+- return 0;
+-
+- /* Clockdomain now has one enabled downstream clock */
+-
+- pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
+- clk->name);
+-
+- arch_clkdm->clkdm_clk_enable(clkdm);
+- pwrdm_clkdm_state_switch(clkdm);
+-
+- return 0;
++ return _clkdm_clk_hwmod_enable(clkdm);
+ }
+
+ /**
+@@ -849,9 +878,8 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ * clockdomain usecount goes to 0, put the clockdomain to sleep
+ * (software-supervised mode) or remove the clkdm autodependencies
+ * (hardware-supervised mode). Returns -EINVAL if passed null
+- * pointers; -ERANGE if the @clkdm usecount underflows and debugging
+- * is enabled; or returns 0 upon success or if the clockdomain is in
+- * hwsup idle mode.
++ * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
++ * upon success or if the clockdomain is in hwsup idle mode.
+ */
+ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ {
+@@ -860,30 +888,72 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ * downstream clocks for debugging purposes?
+ */
+
+- if (!clkdm || !clk)
++ if (!clk)
+ return -EINVAL;
+
+- if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
++ return _clkdm_clk_hwmod_disable(clkdm);
++}
++
++/**
++ * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
++ * @clkdm: struct clockdomain *
++ * @oh: struct omap_hwmod * of the enabled downstream hwmod
++ *
++ * Increment the usecount of the clockdomain @clkdm and ensure that it
++ * is awake before @oh is enabled. Intended to be called by
++ * module_enable() code.
++ * If the clockdomain is in software-supervised idle mode, force the
++ * clockdomain to wake. If the clockdomain is in hardware-supervised idle
++ * mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
++ * clockdomain can be read from/written to by on-chip processors.
++ * Returns -EINVAL if passed null pointers;
++ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
++ */
++int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
++{
++ /* The clkdm attribute does not exist yet prior OMAP4 */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ return 0;
++
++ /*
++ * XXX Rewrite this code to maintain a list of enabled
++ * downstream hwmods for debugging purposes?
++ */
++
++ if (!oh)
+ return -EINVAL;
+
+-#ifdef DEBUG
+- if (atomic_read(&clkdm->usecount) == 0) {
+- WARN_ON(1); /* underflow */
+- return -ERANGE;
+- }
+-#endif
++ return _clkdm_clk_hwmod_enable(clkdm);
++}
+
+- if (atomic_dec_return(&clkdm->usecount) > 0)
++/**
++ * clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
++ * @clkdm: struct clockdomain *
++ * @oh: struct omap_hwmod * of the disabled downstream hwmod
++ *
++ * Decrement the usecount of this clockdomain @clkdm when @oh is
++ * disabled. Intended to be called by module_disable() code.
++ * If the clockdomain usecount goes to 0, put the clockdomain to sleep
++ * (software-supervised mode) or remove the clkdm autodependencies
++ * (hardware-supervised mode).
++ * Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
++ * underflows; or returns 0 upon success or if the clockdomain is in hwsup
++ * idle mode.
++ */
++int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
++{
++ /* The clkdm attribute does not exist yet prior OMAP4 */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return 0;
+
+- /* All downstream clocks of this clockdomain are now disabled */
+-
+- pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
+- clk->name);
++ /*
++ * XXX Rewrite this code to maintain a list of enabled
++ * downstream hwmods for debugging purposes?
++ */
+
+- arch_clkdm->clkdm_clk_disable(clkdm);
+- pwrdm_clkdm_state_switch(clkdm);
++ if (!oh)
++ return -EINVAL;
+
+- return 0;
++ return _clkdm_clk_hwmod_disable(clkdm);
+ }
+
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 5823584..8e0da64 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -20,6 +20,7 @@
+
+ #include "powerdomain.h"
+ #include <plat/clock.h>
++#include <plat/omap_hwmod.h>
+ #include <plat/cpu.h>
+
+ /*
+@@ -183,6 +184,8 @@ int clkdm_sleep(struct clockdomain *clkdm);
+
+ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
++int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
++int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
+
+ extern void __init omap2xxx_clockdomains_init(void);
+ extern void __init omap3xxx_clockdomains_init(void);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0090-OMAP2-clockdomain-add-clkdm_in_hwsup.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0090-OMAP2-clockdomain-add-clkdm_in_hwsup.patch
--- /dev/null
@@ -0,0 +1,141 @@
+From 184b3b5b0b4db984ed56ff182e36a5a409b114c1 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sun, 10 Jul 2011 05:56:54 -0600
+Subject: [PATCH 090/149] OMAP2+: clockdomain: add clkdm_in_hwsup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add a new function, clkdm_in_hwsup(), that returns true if a clockdomain
+is configured for hardware-supervised idle. It does not actually read the
+hardware; rather, it checks an internal flag in the struct clockdomain, which
+is changed when the clockdomain is switched in and out of hardware-supervised
+idle. This should be safe, since all changes to the idle mode should
+pass through the clockdomain code.
+
+Based on a set of patches by Rajendra Nayak <rnayak@ti.com> which do
+the same thing by checking the hardware bits. This approach should be
+faster and more compact.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Todd Poynor <toddpoynor@google.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 30 ++++++++++++++++++++++++++++--
+ arch/arm/mach-omap2/clockdomain.h | 6 ++++++
+ 2 files changed, 34 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 5a57de5..239b558 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -1,8 +1,8 @@
+ /*
+ * OMAP2/3/4 clockdomain framework functions
+ *
+- * Copyright (C) 2008-2010 Texas Instruments, Inc.
+- * Copyright (C) 2008-2010 Nokia Corporation
++ * Copyright (C) 2008-2011 Texas Instruments, Inc.
++ * Copyright (C) 2008-2011 Nokia Corporation
+ *
+ * Written by Paul Walmsley and Jouni Högander
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+@@ -704,6 +704,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
+
+ pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
+
++ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
++
+ return arch_clkdm->clkdm_sleep(clkdm);
+ }
+
+@@ -732,6 +734,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
+
+ pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
+
++ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
++
+ return arch_clkdm->clkdm_wakeup(clkdm);
+ }
+
+@@ -762,6 +766,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
+ pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
+ clkdm->name);
+
++ clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
++
+ arch_clkdm->clkdm_allow_idle(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+ }
+@@ -792,9 +798,29 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
+ clkdm->name);
+
++ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
++
+ arch_clkdm->clkdm_deny_idle(clkdm);
+ }
+
++/**
++ * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
++ * @clkdm: struct clockdomain *
++ *
++ * Returns true if clockdomain @clkdm currently has
++ * hardware-supervised idle enabled, or false if it does not or if
++ * @clkdm is NULL. It is only valid to call this function after
++ * clkdm_init() has been called. This function does not actually read
++ * bits from the hardware; it instead tests an in-memory flag that is
++ * changed whenever the clockdomain code changes the auto-idle mode.
++ */
++bool clkdm_in_hwsup(struct clockdomain *clkdm)
++{
++ if (!clkdm)
++ return false;
++
++ return (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
++}
+
+ /* Clockdomain-to-clock/hwmod framework interface code */
+
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 8e0da64..8782a5c 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -83,6 +83,9 @@ struct clkdm_dep {
+ const struct omap_chip_id omap_chip;
+ };
+
++/* Possible flags for struct clockdomain._flags */
++#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
++
+ /**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+@@ -90,6 +93,7 @@ struct clkdm_dep {
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
++ * @_flags: Flags for use only by internal clockdomain code
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
+ * @cm_inst: (OMAP4 only) CM instance register offset
+@@ -114,6 +118,7 @@ struct clockdomain {
+ } pwrdm;
+ const u16 clktrctrl_mask;
+ const u8 flags;
++ u8 _flags;
+ const u8 dep_bit;
+ const u8 prcm_partition;
+ const s16 cm_inst;
+@@ -178,6 +183,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
+ void clkdm_allow_idle(struct clockdomain *clkdm);
+ void clkdm_deny_idle(struct clockdomain *clkdm);
++bool clkdm_in_hwsup(struct clockdomain *clkdm);
+
+ int clkdm_wakeup(struct clockdomain *clkdm);
+ int clkdm_sleep(struct clockdomain *clkdm);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0091-OMAP2-PM-idle-clkdms-only-if-already-in-idle.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0091-OMAP2-PM-idle-clkdms-only-if-already-in-idle.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0091-OMAP2-PM-idle-clkdms-only-if-already-in-idle.patch
@@ -0,0 +1,53 @@
+From e9afc6eef2d05ec2e76a647bfd1e858e348fa13a Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Sun, 10 Jul 2011 05:56:54 -0600
+Subject: [PATCH 091/149] OMAP2+: PM: idle clkdms only if already in idle
+
+The omap_set_pwrdm_state function forces clockdomains
+to idle, without checking the existing idle state
+programmed, instead based solely on the HW capability
+of the clockdomain to support idle.
+This is wrong and the clockdomains should be idled
+post a state_switch *only* if idle transitions on the
+clockdomain were already enabled.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Acked-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/pm.c | 4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index d48813f..3feb359 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -108,6 +108,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ u32 cur_state;
+ int sleep_switch = -1;
+ int ret = 0;
++ int hwsup = 0;
+
+ if (pwrdm == NULL || IS_ERR(pwrdm))
+ return -EINVAL;
+@@ -127,6 +128,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+ sleep_switch = LOWPOWERSTATE_SWITCH;
+ } else {
++ hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
+ clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+ pwrdm_wait_transition(pwrdm);
+ sleep_switch = FORCEWAKEUP_SWITCH;
+@@ -142,7 +144,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+
+ switch (sleep_switch) {
+ case FORCEWAKEUP_SWITCH:
+- if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
++ if (hwsup)
+ clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+ else
+ clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0092-OMAP2-clockdomain-Add-per-clkdm-lock-to-prevent-conc.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0092-OMAP2-clockdomain-Add-per-clkdm-lock-to-prevent-conc.patch
--- /dev/null
@@ -0,0 +1,264 @@
+From d63deeadf77ca6351c3ffc6058bf55f22f670dbc Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Sun, 10 Jul 2011 05:56:55 -0600
+Subject: [PATCH 092/149] OMAP2+: clockdomain: Add per clkdm lock to prevent concurrent state programming
+
+Since the clkdm state programming is now done from within the hwmod
+framework (which uses a per-hwmod lock) instead of the being done
+from the clock framework (which used a global lock), there is now a
+need to have per-clkdm locking to prevent races between different
+hwmods/modules belonging to the same clock domain concurrently
+programming the clkdm state.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 47 +++++++++++++++++++++++----
+ arch/arm/mach-omap2/clockdomain.h | 2 +
+ arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 6 ++-
+ arch/arm/mach-omap2/clockdomain44xx.c | 13 ++-----
+ 4 files changed, 50 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 239b558..ab7db08 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -92,6 +92,8 @@ static int _clkdm_register(struct clockdomain *clkdm)
+
+ pwrdm_add_clkdm(pwrdm, clkdm);
+
++ spin_lock_init(&clkdm->lock);
++
+ pr_debug("clockdomain: registered %s\n", clkdm->name);
+
+ return 0;
+@@ -690,6 +692,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ */
+ int clkdm_sleep(struct clockdomain *clkdm)
+ {
++ int ret;
++ unsigned long flags;
++
+ if (!clkdm)
+ return -EINVAL;
+
+@@ -704,9 +709,11 @@ int clkdm_sleep(struct clockdomain *clkdm)
+
+ pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+-
+- return arch_clkdm->clkdm_sleep(clkdm);
++ ret = arch_clkdm->clkdm_sleep(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
++ return ret;
+ }
+
+ /**
+@@ -720,6 +727,9 @@ int clkdm_sleep(struct clockdomain *clkdm)
+ */
+ int clkdm_wakeup(struct clockdomain *clkdm)
+ {
++ int ret;
++ unsigned long flags;
++
+ if (!clkdm)
+ return -EINVAL;
+
+@@ -734,9 +744,11 @@ int clkdm_wakeup(struct clockdomain *clkdm)
+
+ pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+-
+- return arch_clkdm->clkdm_wakeup(clkdm);
++ ret = arch_clkdm->clkdm_wakeup(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
++ return ret;
+ }
+
+ /**
+@@ -751,6 +763,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
+ */
+ void clkdm_allow_idle(struct clockdomain *clkdm)
+ {
++ unsigned long flags;
++
+ if (!clkdm)
+ return;
+
+@@ -766,10 +780,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
+ pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
+ clkdm->name);
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
+-
+ arch_clkdm->clkdm_allow_idle(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
+ }
+
+ /**
+@@ -783,6 +798,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
+ */
+ void clkdm_deny_idle(struct clockdomain *clkdm)
+ {
++ unsigned long flags;
++
+ if (!clkdm)
+ return;
+
+@@ -798,9 +815,10 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
+ clkdm->name);
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+-
+ arch_clkdm->clkdm_deny_idle(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
+ }
+
+ /**
+@@ -816,16 +834,25 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ */
+ bool clkdm_in_hwsup(struct clockdomain *clkdm)
+ {
++ bool ret;
++ unsigned long flags;
++
+ if (!clkdm)
+ return false;
+
+- return (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
++ spin_lock_irqsave(&clkdm->lock, flags);
++ ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
++ spin_unlock_irqrestore(&clkdm->lock, flags);
++
++ return ret;
+ }
+
+ /* Clockdomain-to-clock/hwmod framework interface code */
+
+ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+ {
++ unsigned long flags;
++
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+ return -EINVAL;
+
+@@ -837,9 +864,11 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+ if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
+ return 0;
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ arch_clkdm->clkdm_clk_enable(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ pwrdm_clkdm_state_switch(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+
+@@ -848,6 +877,8 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+
+ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+ {
++ unsigned long flags;
++
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ return -EINVAL;
+
+@@ -859,8 +890,10 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+ if (atomic_dec_return(&clkdm->usecount) > 0)
+ return 0;
+
++ spin_lock_irqsave(&clkdm->lock, flags);
+ arch_clkdm->clkdm_clk_disable(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
++ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 8782a5c..1e50c88 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -17,6 +17,7 @@
+ #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+
+ #include <linux/init.h>
++#include <linux/spinlock.h>
+
+ #include "powerdomain.h"
+ #include <plat/clock.h>
+@@ -128,6 +129,7 @@ struct clockdomain {
+ const struct omap_chip_id omap_chip;
+ atomic_t usecount;
+ struct list_head node;
++ spinlock_t lock;
+ };
+
+ /**
+diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+index 48d0db7..f740edb 100644
+--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+@@ -183,7 +183,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
+ _clkdm_add_autodeps(clkdm);
+ _enable_hwsup(clkdm);
+ } else {
+- clkdm_wakeup(clkdm);
++ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
++ omap2_clkdm_wakeup(clkdm);
+ }
+
+ return 0;
+@@ -205,7 +206,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
+ _clkdm_del_autodeps(clkdm);
+ _enable_hwsup(clkdm);
+ } else {
+- clkdm_sleep(clkdm);
++ if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
++ omap2_clkdm_sleep(clkdm);
+ }
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
+index a1a4ecd..b43706a 100644
+--- a/arch/arm/mach-omap2/clockdomain44xx.c
++++ b/arch/arm/mach-omap2/clockdomain44xx.c
+@@ -95,13 +95,8 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+
+ static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+ {
+- bool hwsup = false;
+-
+- hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+- clkdm->cm_inst, clkdm->clkdm_offs);
+-
+- if (!hwsup)
+- clkdm_wakeup(clkdm);
++ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
++ return omap4_clkdm_wakeup(clkdm);
+
+ return 0;
+ }
+@@ -113,8 +108,8 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+ hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+ clkdm->cm_inst, clkdm->clkdm_offs);
+
+- if (!hwsup)
+- clkdm_sleep(clkdm);
++ if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
++ omap4_clkdm_sleep(clkdm);
+
+ return 0;
+ }
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0093-OMAP2-clock-allow-per-SoC-clock-init-code-to-prevent.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0093-OMAP2-clock-allow-per-SoC-clock-init-code-to-prevent.patch
--- /dev/null
@@ -0,0 +1,123 @@
+From 6479ce1adbb20504cba420d8f0f5af4c9ee91e73 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Sun, 10 Jul 2011 05:57:06 -0600
+Subject: [PATCH 093/149] OMAP2+: clock: allow per-SoC clock init code to prevent clockdomain calls from clock code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The OMAP2/3 clock code was written to notify the clockdomain code when
+the first clock in a clockdomain is enabled and when the last enabled
+clock in a clockdomain is disabled. OMAP4 requires a different
+approach: the hwmod code needs to signal the clockdomain code when to
+force-enable and auto-idle a clockdomain during the IP block enable
+process. The current conjecture is that once that hwmod sequence is
+implemented, it will no longer be necessary for the clock code to call
+into the clockdomain code for "optional clocks" on OMAP4.
+
+Add a static flag to the OMAP2+ clock code, clkdm_control, that by
+default preserves the OMAP2/3 behavior. Also add a function,
+omap2_clk_disable_clkdm_control(), intended to be called from OMAP4
+and beyond clock initcalls, that disables the old behavior.
+
+Part of this patch was originally based on a patch by Rajendra Nayak
+<rnayak@ti.com>.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+---
+ arch/arm/mach-omap2/clock.c | 27 ++++++++++++++++++++++++---
+ arch/arm/mach-omap2/clock.h | 3 +++
+ 2 files changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
+index 180299e..fc84576 100644
+--- a/arch/arm/mach-omap2/clock.c
++++ b/arch/arm/mach-omap2/clock.c
+@@ -38,6 +38,14 @@
+ u8 cpu_mask;
+
+ /*
++ * clkdm_control: if true, then when a clock is enabled in the
++ * hardware, its clockdomain will first be enabled; and when a clock
++ * is disabled in the hardware, its clockdomain will be disabled
++ * afterwards.
++ */
++static bool clkdm_control = true;
++
++/*
+ * OMAP2+ specific clock functions
+ */
+
+@@ -100,6 +108,19 @@ void omap2_init_clk_clkdm(struct clk *clk)
+ }
+
+ /**
++ * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
++ *
++ * Prevent the OMAP clock code from calling into the clockdomain code
++ * when a hardware clock in that clockdomain is enabled or disabled.
++ * Intended to be called at init time from omap*_clk_init(). No
++ * return value.
++ */
++void __init omap2_clk_disable_clkdm_control(void)
++{
++ clkdm_control = false;
++}
++
++/**
+ * omap2_clk_dflt_find_companion - find companion clock to @clk
+ * @clk: struct clk * to find the companion clock of
+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+@@ -268,7 +289,7 @@ void omap2_clk_disable(struct clk *clk)
+ clk->ops->disable(clk);
+ }
+
+- if (clk->clkdm)
++ if (clkdm_control && clk->clkdm)
+ clkdm_clk_disable(clk->clkdm, clk);
+
+ if (clk->parent)
+@@ -308,7 +329,7 @@ int omap2_clk_enable(struct clk *clk)
+ }
+ }
+
+- if (clk->clkdm) {
++ if (clkdm_control && clk->clkdm) {
+ ret = clkdm_clk_enable(clk->clkdm, clk);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable clockdomain %s: "
+@@ -330,7 +351,7 @@ int omap2_clk_enable(struct clk *clk)
+ return 0;
+
+ oce_err3:
+- if (clk->clkdm)
++ if (clkdm_control && clk->clkdm)
+ clkdm_clk_disable(clk->clkdm, clk);
+ oce_err2:
+ if (clk->parent)
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index e10ff2b..48ac568 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -16,6 +16,8 @@
+ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
+ #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
+
++#include <linux/kernel.h>
++
+ #include <plat/clock.h>
+
+ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+@@ -72,6 +74,7 @@ void omap2_clk_disable_unused(struct clk *clk);
+ #endif
+
+ void omap2_init_clk_clkdm(struct clk *clk);
++void __init omap2_clk_disable_clkdm_control(void);
+
+ /* clkt_clksel.c public functions */
+ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0094-OMAP2-hwmod-Follow-the-recommended-PRCM-module-enabl.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0094-OMAP2-hwmod-Follow-the-recommended-PRCM-module-enabl.patch
--- /dev/null
@@ -0,0 +1,173 @@
+From 8608f43bc499d2c92dd9e2ae15ae316b44229145 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Sun, 10 Jul 2011 05:57:07 -0600
+Subject: [PATCH 094/149] OMAP2+: hwmod: Follow the recommended PRCM module enable sequence
+
+On OMAP4, the PRCM recommended sequence for enabling
+a module after power-on-reset is:
+-1- Force clkdm to SW_WKUP
+-2- Enabling the clocks
+-3- Configure desired module mode to "enable" or "auto"
+-4- Wait for the desired module idle status to be FUNC
+-5- Program clkdm in HW_AUTO(if supported)
+
+This sequence applies to all older OMAPs' as well,
+however since they use autodeps, it makes sure that
+no clkdm is in IDLE, and hence not requiring a force
+SW_WKUP when a module is being enabled.
+
+OMAP4 does not need to support autodeps, because
+of the dyanamic dependency feature, wherein
+the HW takes care of waking up a clockdomain from
+idle and hence the module, whenever an interconnect
+access happens to the given module.
+
+Implementing the sequence for OMAP4 requires
+the clockdomain handling that is currently done in
+clock framework to be done as part of hwmod framework
+since the step -4- above to "Wait for the desired
+module idle status to be FUNC" is done as part of
+hwmod framework.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[b-cousson@ti.com: Adapt it to the new clkdm hwmod attribute and API]
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+[paul@pwsan.com: dropped mach-omap2/clock.c changes; modified to only
+ call the clockdomain code if oh->clkdm is set; disable clock->clockdomain
+ interaction on OMAP4]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock44xx_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod.c | 70 ++++++++++++++++++++++++----------
+ 2 files changed, 51 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 07bf0de..0d13def 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3340,6 +3340,7 @@ int __init omap4xxx_clk_init(void)
+ }
+
+ clk_init(&omap2_clk_functions);
++ omap2_clk_disable_clkdm_control();
+
+ for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+ c++)
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 4424fee..84cc0bd 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1437,6 +1437,7 @@ static int _reset(struct omap_hwmod *oh)
+ static int _enable(struct omap_hwmod *oh)
+ {
+ int r;
++ int hwsup = 0;
+
+ pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+
+@@ -1448,14 +1449,6 @@ static int _enable(struct omap_hwmod *oh)
+ return -EINVAL;
+ }
+
+- /* Mux pins for device runtime if populated */
+- if (oh->mux && (!oh->mux->enabled ||
+- ((oh->_state == _HWMOD_STATE_IDLE) &&
+- oh->mux->pads_dynamic)))
+- omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+-
+- _add_initiator_dep(oh, mpu_oh);
+- _enable_clocks(oh);
+
+ /*
+ * If an IP contains only one HW reset line, then de-assert it in order
+@@ -1466,23 +1459,56 @@ static int _enable(struct omap_hwmod *oh)
+ oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+ _deassert_hardreset(oh, oh->rst_lines[0].name);
+
+- r = _wait_target_ready(oh);
+- if (r) {
+- pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
+- oh->name, r);
+- _disable_clocks(oh);
++ /* Mux pins for device runtime if populated */
++ if (oh->mux && (!oh->mux->enabled ||
++ ((oh->_state == _HWMOD_STATE_IDLE) &&
++ oh->mux->pads_dynamic)))
++ omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
++
++ _add_initiator_dep(oh, mpu_oh);
+
+- return r;
++ if (oh->clkdm) {
++ /*
++ * A clockdomain must be in SW_SUP before enabling
++ * completely the module. The clockdomain can be set
++ * in HW_AUTO only when the module become ready.
++ */
++ hwsup = clkdm_in_hwsup(oh->clkdm);
++ r = clkdm_hwmod_enable(oh->clkdm, oh);
++ if (r) {
++ WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
++ oh->name, oh->clkdm->name, r);
++ return r;
++ }
+ }
++
++ _enable_clocks(oh);
+ _enable_module(oh);
+
+- oh->_state = _HWMOD_STATE_ENABLED;
++ r = _wait_target_ready(oh);
++ if (!r) {
++ /*
++ * Set the clockdomain to HW_AUTO only if the target is ready,
++ * assuming that the previous state was HW_AUTO
++ */
++ if (oh->clkdm && hwsup)
++ clkdm_allow_idle(oh->clkdm);
+
+- /* Access the sysconfig only if the target is ready */
+- if (oh->class->sysc) {
+- if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
+- _update_sysc_cache(oh);
+- _enable_sysc(oh);
++ oh->_state = _HWMOD_STATE_ENABLED;
++
++ /* Access the sysconfig only if the target is ready */
++ if (oh->class->sysc) {
++ if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
++ _update_sysc_cache(oh);
++ _enable_sysc(oh);
++ }
++ } else {
++ _disable_clocks(oh);
++ pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
++ oh->name, r);
++
++ if (oh->clkdm)
++ clkdm_hwmod_disable(oh->clkdm, oh);
+ }
+
+ return r;
+@@ -1523,6 +1549,8 @@ static int _idle(struct omap_hwmod *oh)
+ * transition to complete properly.
+ */
+ _disable_clocks(oh);
++ if (oh->clkdm)
++ clkdm_hwmod_disable(oh->clkdm, oh);
+
+ /* Mux pins for device idle if populated */
+ if (oh->mux && oh->mux->pads_dynamic)
+@@ -1620,6 +1648,8 @@ static int _shutdown(struct omap_hwmod *oh)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
+ _disable_clocks(oh);
++ if (oh->clkdm)
++ clkdm_hwmod_disable(oh->clkdm, oh);
+ }
+ /* XXX Should this code also force-disable the optional clocks? */
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0095-OMAP-Add-debugfs-node-to-show-the-summary-of-all-clo.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0095-OMAP-Add-debugfs-node-to-show-the-summary-of-all-clo.patch
--- /dev/null
@@ -0,0 +1,84 @@
+From 253facb782e79ae1367baf26058aa160bc479592 Mon Sep 17 00:00:00 2001
+From: Jon Hunter <jon-hunter@ti.com>
+Date: Sun, 10 Jul 2011 05:57:33 -0600
+Subject: [PATCH 095/149] OMAP: Add debugfs node to show the summary of all clocks
+
+Add a debugfs node called "summary" to /sys/kernel/debug/clock/
+that displays a quick summary of all clocks registered in the
+"clocks" structure. The format of the output from this node is:
+
+<clock-name> <parent-name> <rate> <usecount>
+
+This debugfs node was very helpful for taking a quick snapshot of
+the linux clock tree for OMAP and ensuring clock frequencies
+calculated by the kernel were indeed correct. This patch helped
+uncover some bugs in the linux clock tree for OMAP4.
+
+Signed-off-by: Jon Hunter <jon-hunter@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/clock.c | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 39 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
+index c9122dd..156b27d 100644
+--- a/arch/arm/plat-omap/clock.c
++++ b/arch/arm/plat-omap/clock.c
+@@ -475,8 +475,41 @@ int __init clk_init(struct clk_functions * custom_clocks)
+ /*
+ * debugfs support to trace clock tree hierarchy and attributes
+ */
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
+ static struct dentry *clk_debugfs_root;
+
++static int clk_dbg_show_summary(struct seq_file *s, void *unused)
++{
++ struct clk *c;
++ struct clk *pa;
++
++ seq_printf(s, "%-30s %-30s %-10s %s\n",
++ "clock-name", "parent-name", "rate", "use-count");
++
++ list_for_each_entry(c, &clocks, node) {
++ pa = c->parent;
++ seq_printf(s, "%-30s %-30s %-10lu %d\n",
++ c->name, pa ? pa->name : "none", c->rate, c->usecount);
++ }
++
++ return 0;
++}
++
++static int clk_dbg_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, clk_dbg_show_summary, inode->i_private);
++}
++
++static const struct file_operations debug_clock_fops = {
++ .open = clk_dbg_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
+ static int clk_debugfs_register_one(struct clk *c)
+ {
+ int err;
+@@ -551,6 +584,12 @@ static int __init clk_debugfs_init(void)
+ if (err)
+ goto err_out;
+ }
++
++ d = debugfs_create_file("summary", S_IRUGO,
++ d, NULL, &debug_clock_fops);
++ if (!d)
++ return -ENOMEM;
++
+ return 0;
+ err_out:
+ debugfs_remove_recursive(clk_debugfs_root);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0096-OMAP2-hwmod-remove-unused-voltagedomain-pointer.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0096-OMAP2-hwmod-remove-unused-voltagedomain-pointer.patch
--- /dev/null
@@ -0,0 +1,30 @@
+From 758d7d85d81593e529cdc1c93d9d5cd220007810 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 11:02:59 -0700
+Subject: [PATCH 096/149] OMAP2+: hwmod: remove unused voltagedomain pointer
+
+The voltage domain pointer currently in struct omap_hwmod is not used
+and does not belong here. Instead, voltage domains will be associated
+with powerdomains in forthcoming patches.
+
+Acked-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 0e329ca..38ac4af 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -526,7 +526,6 @@ struct omap_hwmod {
+ char *clkdm_name;
+ struct clockdomain *clkdm;
+ char *vdd_name;
+- struct voltagedomain *voltdm;
+ struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
+ struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
+ void *dev_attr;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0097-OMAP2-voltage-move-PRCM-mod-offets-into-VC-VP-struct.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0097-OMAP2-voltage-move-PRCM-mod-offets-into-VC-VP-struct.patch
--- /dev/null
@@ -0,0 +1,577 @@
+From ab3990ea80b797bb2e3b87afc968d8624aa8d25c Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 13:35:22 -0700
+Subject: [PATCH 097/149] OMAP2+: voltage: move PRCM mod offets into VC/VP structures
+
+Eliminate need for global variables for the various PRM module offsets by
+making them part of the VP/VC common structures
+
+Eventually, these will likely be moved again, or more likely removed
+when VP/VC code is isolated, but for now just getting rid of them as
+global variabes so that the voltage domain initialization can be
+cleaned up.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.h | 2 +
+ arch/arm/mach-omap2/vc3xxx_data.c | 1 +
+ arch/arm/mach-omap2/vc44xx_data.c | 1 +
+ arch/arm/mach-omap2/voltage.c | 109 ++++++++++++-------------
+ arch/arm/mach-omap2/voltage.h | 6 +-
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 8 +-
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 9 +-
+ arch/arm/mach-omap2/vp.h | 2 +
+ arch/arm/mach-omap2/vp3xxx_data.c | 1 +
+ arch/arm/mach-omap2/vp44xx_data.c | 1 +
+ 10 files changed, 70 insertions(+), 70 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index e776777..f7338af 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -23,6 +23,7 @@
+ * struct omap_vc_common_data - per-VC register/bitfield data
+ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+ * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
++ * @prm_mod: PRM module id used for PRM register access
+ * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
+ * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
+ * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
+@@ -40,6 +41,7 @@
+ struct omap_vc_common_data {
+ u32 cmd_on_mask;
+ u32 valid;
++ s16 prm_mod;
+ u8 smps_sa_reg;
+ u8 smps_volra_reg;
+ u8 bypass_val_reg;
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index f37dc4b..55caccb 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -30,6 +30,7 @@
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+ static struct omap_vc_common_data omap3_vc_common = {
++ .prm_mod = OMAP3430_GR_MOD,
+ .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+ .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index a98da8d..b62678e 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -31,6 +31,7 @@
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+ static const struct omap_vc_common_data omap4_vc_common = {
++ .prm_mod = OMAP4430_PRM_DEVICE_INST,
+ .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+ .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 9ef3789..3151d75 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -50,10 +50,6 @@ static struct omap_vdd_info **vdd_info;
+ */
+ static int nr_scalable_vdd;
+
+-/* XXX document */
+-static s16 prm_mod_offs;
+-static s16 prm_irqst_ocp_mod_offs;
+-
+ static struct dentry *voltage_dir;
+
+ /* Init function pointers */
+@@ -147,7 +143,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
+ return -EINVAL;
+ }
+
+- vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
++ vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+
+ if (!vdd->pmic_info->vsel_to_uv) {
+ pr_warning("PMIC function to convert vsel to voltage"
+@@ -197,19 +193,19 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
+
+ vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+
+- vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
+ vdd->vp_data->vp_common->vpconfig_initvdd);
+ vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
+
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+ vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
+- prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /* Clear initVDD copy trigger bit */
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ }
+
+ /* Generic voltage init functions */
+@@ -227,19 +223,19 @@ static void __init vp_init(struct omap_vdd_info *vdd)
+ (vdd->vp_rt_data.vpconfig_errorgain <<
+ vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
+ vdd->vp_data->vp_common->vpconfig_timeouten;
+- vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+ vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
+ (vdd->vp_rt_data.vstepmin_stepmin <<
+ vdd->vp_data->vp_common->vstepmin_stepmin_shift));
+- vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
++ vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstepmin);
+
+ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+ vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
+ (vdd->vp_rt_data.vstepmax_stepmax <<
+ vdd->vp_data->vp_common->vstepmax_stepmax_shift));
+- vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
++ vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstepmax);
+
+ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+ vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
+@@ -247,7 +243,7 @@ static void __init vp_init(struct omap_vdd_info *vdd)
+ vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
+ (vdd->vp_rt_data.vlimitto_timeout <<
+ vdd->vp_data->vp_common->vlimitto_timeout_shift));
+- vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
++ vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vlimitto);
+ }
+
+ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+@@ -336,23 +332,23 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+ volt_data = NULL;
+
+ *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+- *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
++ *current_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+
+ /* Setting the ON voltage to the new target voltage */
+- vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
++ vc_cmdval = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+ vc_cmdval &= ~vc_common->cmd_on_mask;
+ vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
+- vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
++ vdd->write_reg(vc_cmdval, vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+
+ /* Setting vp errorgain based on the voltage */
+ if (volt_data) {
+- vp_errgain_val = vdd->read_reg(prm_mod_offs,
++ vp_errgain_val = vdd->read_reg(vdd->vp_data->vp_common->prm_mod,
+ vdd->vp_data->vpconfig);
+ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+ vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
+ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+ vp_common->vpconfig_errorgain_shift;
+- vdd->write_reg(vp_errgain_val, prm_mod_offs,
++ vdd->write_reg(vp_errgain_val, vdd->vp_data->vp_common->prm_mod,
+ vdd->vp_data->vpconfig);
+ }
+
+@@ -394,11 +390,11 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ (vdd->pmic_info->i2c_slave_addr <<
+ vdd->vc_data->vc_common->slaveaddr_shift);
+
+- vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
+- vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
++ vdd->write_reg(vc_bypass_value, vdd->vc_data->vc_common->prm_mod, vc_bypass_val_reg);
++ vdd->write_reg(vc_bypass_value | vc_valid, vdd->vc_data->vc_common->prm_mod,
+ vc_bypass_val_reg);
+
+- vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
++ vc_bypass_value = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vc_bypass_val_reg);
+ /*
+ * Loop till the bypass command is acknowledged from the SMPS.
+ * NOTE: This is legacy code. The loop count and retry count needs
+@@ -417,7 +413,7 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ loop_cnt = 0;
+ udelay(10);
+ }
+- vc_bypass_value = vdd->read_reg(prm_mod_offs,
++ vc_bypass_value = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+ vc_bypass_val_reg);
+ }
+
+@@ -445,8 +441,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ */
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- prm_irqst_ocp_mod_offs, prm_irqst_reg);
+- if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ vdd->prm_irqst_mod, prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status))
+ break;
+ udelay(1);
+@@ -458,28 +454,28 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ }
+
+ /* Configure for VP-Force Update */
+- vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
+ vdd->vp_data->vp_common->vpconfig_forceupdate |
+ vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
+ vpconfig |= ((target_vsel <<
+ vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+ vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /* Force update of voltage */
+ vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /*
+ * Wait for TransactionDone. Typical latency is <200us.
+ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ */
+ timeout = 0;
+- omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status),
+ VP_TRANXDONE_TIMEOUT, timeout);
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+@@ -496,8 +492,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ timeout = 0;
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- prm_irqst_ocp_mod_offs, prm_irqst_reg);
+- if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ vdd->prm_irqst_mod, prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status))
+ break;
+ udelay(1);
+@@ -508,13 +504,13 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ "to clear the TRANXDONE status\n",
+ __func__, vdd->voltdm.name);
+
+- vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ /* Clear initVDD copy trigger bit */
+ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ /* Clear force bit */
+ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ return 0;
+ }
+@@ -525,10 +521,10 @@ static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
+ * Voltage Manager FSM parameters init
+ * XXX This data should be passed in from the board file
+ */
+- vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
+- vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
++ vdd->write_reg(OMAP3_CLKSETUP, vdd->vc_data->vc_common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
++ vdd->write_reg(OMAP3_VOLTOFFSET, vdd->vc_data->vc_common->prm_mod,
+ OMAP3_PRM_VOLTOFFSET_OFFSET);
+- vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
++ vdd->write_reg(OMAP3_VOLTSETUP2, vdd->vc_data->vc_common->prm_mod,
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
+ }
+
+@@ -550,15 +546,15 @@ static void __init omap3_vc_init(struct omap_vdd_info *vdd)
+ (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
+ (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
+ (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
+- vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+
+ /*
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+ */
+- vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
++ vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vdd->vc_data->vc_common->prm_mod,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+- vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
++ vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vdd->vc_data->vc_common->prm_mod,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ omap3_vfsm_init(vdd);
+@@ -585,11 +581,11 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+ vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+ OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+ OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+ /* XXX These are magic numbers and do not belong! */
+ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+- vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+ is_initialized = true;
+ }
+@@ -612,27 +608,27 @@ static void __init omap_vc_init(struct omap_vdd_info *vdd)
+ }
+
+ /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(prm_mod_offs,
++ vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+ vdd->vc_data->vc_common->smps_sa_reg);
+ vc_val &= ~vdd->vc_data->smps_sa_mask;
+ vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
+- vdd->write_reg(vc_val, prm_mod_offs,
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod,
+ vdd->vc_data->vc_common->smps_sa_reg);
+
+ /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(prm_mod_offs,
++ vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+ vdd->vc_data->vc_common->smps_volra_reg);
+ vc_val &= ~vdd->vc_data->smps_volra_mask;
+ vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
+- vdd->write_reg(vc_val, prm_mod_offs,
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod,
+ vdd->vc_data->vc_common->smps_volra_reg);
+
+ /* Configure the setup times */
+- vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
++ vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
+ vc_val &= ~vdd->vfsm->voltsetup_mask;
+ vc_val |= vdd->pmic_info->volt_setup_time <<
+ vdd->vfsm->voltsetup_shift;
+- vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
++ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
+
+ if (cpu_is_omap34xx())
+ omap3_vc_init(vdd);
+@@ -713,7 +709,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
++ curr_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+
+ if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+ pr_warning("%s: PMIC function to convert vsel to voltage"
+@@ -755,9 +751,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ vp_latch_vsel(vdd);
+
+ /* Enable VP */
+- vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ vdd->vp_enabled = true;
+ }
+
+@@ -794,14 +790,14 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ }
+
+ /* Disable VP */
+- vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
++ vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+
+ /*
+ * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+ */
+- omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
++ omap_test_timeout((vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstatus)),
+ VP_IDLE_TIMEOUT, timeout);
+
+ if (timeout >= VP_IDLE_TIMEOUT)
+@@ -1094,12 +1090,9 @@ int __init omap_voltage_late_init(void)
+ }
+
+ /* XXX document */
+-int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
+- struct omap_vdd_info *omap_vdd_array[],
++int __init omap_voltage_early_init(struct omap_vdd_info *omap_vdd_array[],
+ u8 omap_vdd_count)
+ {
+- prm_mod_offs = prm_mod;
+- prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
+ vdd_info = omap_vdd_array;
+ nr_scalable_vdd = omap_vdd_count;
+ return 0;
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index e9f5408..ffdc55e 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -119,6 +119,7 @@ struct omap_volt_pmic_info {
+ * @voltdm : pointer to the voltage domain structure
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
++ * @prm_irqst_mod : PRM module id used for PRM IRQ status register access
+ * @vp_enabled : flag to keep track of whether vp is enabled or not
+ * @volt_scale : API to scale the voltage of the vdd.
+ */
+@@ -133,6 +134,8 @@ struct omap_vdd_info {
+ struct dentry *debug_dir;
+ u32 curr_volt;
+ bool vp_enabled;
++
++ s16 prm_irqst_mod;
+ u32 (*read_reg) (u16 mod, u8 offset);
+ void (*write_reg) (u32 val, u16 mod, u8 offset);
+ int (*volt_scale) (struct omap_vdd_info *vdd,
+@@ -151,8 +154,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ unsigned long volt);
+ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+-int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod,
+- struct omap_vdd_info *omap_vdd_array[],
++int __init omap_voltage_early_init(struct omap_vdd_info *omap_vdd_array[],
+ u8 omap_vdd_count);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index def230f..0d30b7f 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -38,6 +38,7 @@ static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap3_vdd1_info = {
++ .prm_irqst_mod = OCP_MOD,
+ .vp_data = &omap3_vp1_data,
+ .vc_data = &omap3_vc1_data,
+ .vfsm = &omap3_vdd1_vfsm_data,
+@@ -53,6 +54,7 @@ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap3_vdd2_info = {
++ .prm_irqst_mod = OCP_MOD,
+ .vp_data = &omap3_vp2_data,
+ .vc_data = &omap3_vc2_data,
+ .vfsm = &omap3_vdd2_vfsm_data,
+@@ -70,9 +72,6 @@ static struct omap_vdd_info *omap3_vdd_info[] = {
+ /* OMAP3 specific voltage init functions */
+ static int __init omap3xxx_voltage_early_init(void)
+ {
+- s16 prm_mod = OMAP3430_GR_MOD;
+- s16 prm_irqst_ocp_mod = OCP_MOD;
+-
+ if (!cpu_is_omap34xx())
+ return 0;
+
+@@ -88,8 +87,7 @@ static int __init omap3xxx_voltage_early_init(void)
+ omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
+ }
+
+- return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+- omap3_vdd_info,
++ return omap_voltage_early_init(omap3_vdd_info,
+ ARRAY_SIZE(omap3_vdd_info));
+ };
+ core_initcall(omap3xxx_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index cb64996..1c2d7d7 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -37,6 +37,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_mpu_info = {
++ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .vp_data = &omap4_vp_mpu_data,
+ .vc_data = &omap4_vc_mpu_data,
+ .vfsm = &omap4_vdd_mpu_vfsm_data,
+@@ -50,6 +51,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_iva_info = {
++ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .vp_data = &omap4_vp_iva_data,
+ .vc_data = &omap4_vc_iva_data,
+ .vfsm = &omap4_vdd_iva_vfsm_data,
+@@ -63,6 +65,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_core_info = {
++ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .vp_data = &omap4_vp_core_data,
+ .vc_data = &omap4_vc_core_data,
+ .vfsm = &omap4_vdd_core_vfsm_data,
+@@ -81,9 +84,6 @@ static struct omap_vdd_info *omap4_vdd_info[] = {
+ /* OMAP4 specific voltage init functions */
+ static int __init omap44xx_voltage_early_init(void)
+ {
+- s16 prm_mod = OMAP4430_PRM_DEVICE_INST;
+- s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+-
+ if (!cpu_is_omap44xx())
+ return 0;
+
+@@ -95,8 +95,7 @@ static int __init omap44xx_voltage_early_init(void)
+ omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+ omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
+
+- return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+- omap4_vdd_info,
++ return omap_voltage_early_init(omap4_vdd_info,
+ ARRAY_SIZE(omap4_vdd_info));
+ };
+ core_initcall(omap44xx_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 7ce134f..d277da6 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -42,6 +42,7 @@
+ * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
++ * @prm_mod: PRM module id used for PRM register access
+ *
+ * XXX It it not necessary to have both a mask and a shift for the same
+ * bitfield - remove one
+@@ -54,6 +55,7 @@ struct omap_vp_common_data {
+ u32 vpconfig_initvdd;
+ u32 vpconfig_forceupdate;
+ u32 vpconfig_vpenable;
++ s16 prm_mod;
+ u8 vpconfig_erroroffset_shift;
+ u8 vpconfig_errorgain_shift;
+ u8 vpconfig_initvoltage_shift;
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index 6452170..c9b3e64 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -31,6 +31,7 @@
+ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ */
+ static const struct omap_vp_common_data omap3_vp_common = {
++ .prm_mod = OMAP3430_GR_MOD,
+ .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 65d1ad6..1a0842e 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -32,6 +32,7 @@
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+ */
+ static const struct omap_vp_common_data omap4_vp_common = {
++ .prm_mod = OMAP4430_PRM_DEVICE_INST,
+ .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0098-OMAP2-voltage-move-prm_irqst_reg-from-VP-into-voltag.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0098-OMAP2-voltage-move-prm_irqst_reg-from-VP-into-voltag.patch
--- /dev/null
@@ -0,0 +1,203 @@
+From ecd88e1c3fcc8cfbba32267252497e9bd1213844 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 17:20:35 -0700
+Subject: [PATCH 098/149] OMAP2+: voltage: move prm_irqst_reg from VP into voltage domain
+
+The prm_irqst_reg is not part of the VP. Move it up into the common
+voltage domain struct.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 15 +++++++--------
+ arch/arm/mach-omap2/voltage.h | 1 +
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 2 ++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 3 +++
+ arch/arm/mach-omap2/vp.h | 3 ---
+ arch/arm/mach-omap2/vp3xxx_data.c | 2 --
+ arch/arm/mach-omap2/vp44xx_data.c | 3 ---
+ 7 files changed, 13 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 3151d75..a366a6b 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -426,23 +426,21 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ unsigned long target_volt)
+ {
+ u32 vpconfig;
+- u8 target_vsel, current_vsel, prm_irqst_reg;
++ u8 target_vsel, current_vsel;
+ int ret, timeout = 0;
+
+ ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+ return ret;
+
+- prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
+-
+ /*
+ * Clear all pending TransactionDone interrupt/status. Typical latency
+ * is <3us
+ */
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
++ vdd->prm_irqst_mod, vdd->prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status))
+ break;
+ udelay(1);
+@@ -475,7 +473,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ */
+ timeout = 0;
+- omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
++ omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod,
++ vdd->prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status),
+ VP_TRANXDONE_TIMEOUT, timeout);
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+@@ -492,8 +491,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ timeout = 0;
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
++ vdd->prm_irqst_mod, vdd->prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+ vdd->vp_data->prm_irqst_data->tranxdone_status))
+ break;
+ udelay(1);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index ffdc55e..db23d49 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -136,6 +136,7 @@ struct omap_vdd_info {
+ bool vp_enabled;
+
+ s16 prm_irqst_mod;
++ u8 prm_irqst_reg;
+ u32 (*read_reg) (u16 mod, u8 offset);
+ void (*write_reg) (u32 val, u16 mod, u8 offset);
+ int (*volt_scale) (struct omap_vdd_info *vdd,
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 0d30b7f..f831f9a 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -39,6 +39,7 @@ static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+
+ static struct omap_vdd_info omap3_vdd1_info = {
+ .prm_irqst_mod = OCP_MOD,
++ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp1_data,
+ .vc_data = &omap3_vc1_data,
+ .vfsm = &omap3_vdd1_vfsm_data,
+@@ -55,6 +56,7 @@ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+
+ static struct omap_vdd_info omap3_vdd2_info = {
+ .prm_irqst_mod = OCP_MOD,
++ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp2_data,
+ .vc_data = &omap3_vc2_data,
+ .vfsm = &omap3_vdd2_vfsm_data,
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 1c2d7d7..64dc265 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -38,6 +38,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
+
+ static struct omap_vdd_info omap4_vdd_mpu_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+ .vp_data = &omap4_vp_mpu_data,
+ .vc_data = &omap4_vc_mpu_data,
+ .vfsm = &omap4_vdd_mpu_vfsm_data,
+@@ -52,6 +53,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+
+ static struct omap_vdd_info omap4_vdd_iva_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_iva_data,
+ .vc_data = &omap4_vc_iva_data,
+ .vfsm = &omap4_vdd_iva_vfsm_data,
+@@ -66,6 +68,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+
+ static struct omap_vdd_info omap4_vdd_core_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_core_data,
+ .vc_data = &omap4_vc_core_data,
+ .vfsm = &omap4_vdd_core_vfsm_data,
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index d277da6..5406b08 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -70,16 +70,13 @@ struct omap_vp_common_data {
+
+ /**
+ * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
+- * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ *
+- * XXX prm_irqst_reg does not belong here
+ * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
+ * hardware bug
+ * XXX This structure is probably not needed
+ */
+ struct omap_vp_prm_irqst_data {
+- u8 prm_irqst_reg;
+ u32 tranxdone_status;
+ };
+
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index c9b3e64..a8ea045 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -51,7 +51,6 @@ static const struct omap_vp_common_data omap3_vp_common = {
+ };
+
+ static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
+- .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+ };
+
+@@ -67,7 +66,6 @@ struct omap_vp_instance_data omap3_vp1_data = {
+ };
+
+ static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
+- .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+ };
+
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 1a0842e..0957c24 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -52,7 +52,6 @@ static const struct omap_vp_common_data omap4_vp_common = {
+ };
+
+ static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+ .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+ };
+
+@@ -68,7 +67,6 @@ struct omap_vp_instance_data omap4_vp_mpu_data = {
+ };
+
+ static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+ };
+
+@@ -84,7 +82,6 @@ struct omap_vp_instance_data omap4_vp_iva_data = {
+ };
+
+ static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0099-OMAP2-voltage-start-towards-a-new-voltagedomain-laye.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0099-OMAP2-voltage-start-towards-a-new-voltagedomain-laye.patch
--- /dev/null
@@ -0,0 +1,986 @@
+From 1de34a7da5240cb0ab762a7fbb9d9f0f6ab35253 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 14:25:45 -0700
+Subject: [PATCH 099/149] OMAP2+: voltage: start towards a new voltagedomain layer
+
+Start cleaning up the voltage layer to have a voltage domain layer
+that resembles the structure of the existing clock and power domain
+layers. To that end:
+
+- move the 'struct voltagedomain' out of 'struct omap_vdd_info' to
+ become the primary data structure.
+
+- convert any functions taking a pointer to struct omap_vdd_info into
+ functions taking a struct voltagedomain pointer.
+
+- convert the register & initialize of voltage domains to look like
+ that of powerdomains
+
+- convert omap_voltage_domain_lookup() to voltdm_lookup(), modeled
+ after the current powerdomain and clockdomain lookup functions.
+
+- omap_voltage_late_init(): only configure VDD info when
+ the vdd_info struct is non-NULL
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/io.c | 3 +
+ arch/arm/mach-omap2/omap_twl.c | 10 +-
+ arch/arm/mach-omap2/pm.c | 2 +-
+ arch/arm/mach-omap2/sr_device.c | 2 +-
+ arch/arm/mach-omap2/voltage.c | 257 ++++++++++++++-----------
+ arch/arm/mach-omap2/voltage.h | 27 ++--
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 34 ++--
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 44 ++--
+ 8 files changed, 207 insertions(+), 172 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 2ce1ce6..9f5a846 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -38,6 +38,7 @@
+ #include "io.h"
+
+ #include <plat/omap-pm.h>
++#include "voltage.h"
+ #include "powerdomain.h"
+
+ #include "clockdomain.h"
+@@ -349,10 +350,12 @@ void __init omap2_init_common_infrastructure(void)
+ omap2xxx_clockdomains_init();
+ omap2430_hwmod_init();
+ } else if (cpu_is_omap34xx()) {
++ omap3xxx_voltagedomains_init();
+ omap3xxx_powerdomains_init();
+ omap3xxx_clockdomains_init();
+ omap3xxx_hwmod_init();
+ } else if (cpu_is_omap44xx()) {
++ omap44xx_voltagedomains_init();
+ omap44xx_powerdomains_init();
+ omap44xx_clockdomains_init();
+ omap44xx_hwmod_init();
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 07d6140..fcd2f62 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -250,13 +250,13 @@ int __init omap4_twl_init(void)
+ if (!cpu_is_omap44xx())
+ return -ENODEV;
+
+- voltdm = omap_voltage_domain_lookup("mpu");
++ voltdm = voltdm_lookup("mpu");
+ omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
+
+- voltdm = omap_voltage_domain_lookup("iva");
++ voltdm = voltdm_lookup("iva");
+ omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
+
+- voltdm = omap_voltage_domain_lookup("core");
++ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
+
+ return 0;
+@@ -288,10 +288,10 @@ int __init omap3_twl_init(void)
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
+- voltdm = omap_voltage_domain_lookup("mpu");
++ voltdm = voltdm_lookup("mpu");
+ omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
+
+- voltdm = omap_voltage_domain_lookup("core");
++ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 3feb359..3bce29b 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -183,7 +183,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+ goto exit;
+ }
+
+- voltdm = omap_voltage_domain_lookup(vdd_name);
++ voltdm = voltdm_lookup(vdd_name);
+ if (IS_ERR(voltdm)) {
+ printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+ __func__, vdd_name);
+diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
+index 10d3c5e..2782d3f 100644
+--- a/arch/arm/mach-omap2/sr_device.c
++++ b/arch/arm/mach-omap2/sr_device.c
+@@ -102,7 +102,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
+ sr_data->senn_mod = 0x1;
+ sr_data->senp_mod = 0x1;
+
+- sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name);
++ sr_data->voltdm = voltdm_lookup(oh->vdd_name);
+ if (IS_ERR(sr_data->voltdm)) {
+ pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
+ __func__, oh->vdd_name);
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index a366a6b..4f0361a 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -40,20 +40,13 @@
+ #include "vc.h"
+ #include "vp.h"
+
+-#define VOLTAGE_DIR_SIZE 16
+-
+-
+-static struct omap_vdd_info **vdd_info;
+-
+-/*
+- * Number of scalable voltage domains.
+- */
+-static int nr_scalable_vdd;
++static LIST_HEAD(voltdm_list);
+
++#define VOLTAGE_DIR_SIZE 16
+ static struct dentry *voltage_dir;
+
+ /* Init function pointers */
+-static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
++static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ unsigned long target_volt);
+
+ static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+@@ -77,11 +70,12 @@ static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+ omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+ }
+
+-static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
++static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+ char *sys_ck_name;
+ struct clk *sys_ck;
+ u32 sys_clk_speed, timeout_val, waittime;
++ struct omap_vdd_info *vdd = voltdm->vdd;
+
+ /*
+ * XXX Clockfw should handle this, or this should be in a
+@@ -101,7 +95,7 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
+ sys_ck = clk_get(NULL, sys_ck_name);
+ if (IS_ERR(sys_ck)) {
+ pr_warning("%s: Could not get the sys clk to calculate"
+- "various vdd_%s params\n", __func__, vdd->voltdm.name);
++ "various vdd_%s params\n", __func__, voltdm->name);
+ return -EINVAL;
+ }
+ sys_clk_speed = clk_get_rate(sys_ck);
+@@ -135,7 +129,8 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
+ /* Voltage debugfs support */
+ static int vp_volt_debug_get(void *data, u64 *val)
+ {
+- struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
++ struct voltagedomain *voltdm = (struct voltagedomain *)data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u8 vsel;
+
+ if (!vdd) {
+@@ -157,14 +152,14 @@ static int vp_volt_debug_get(void *data, u64 *val)
+
+ static int nom_volt_debug_get(void *data, u64 *val)
+ {
+- struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
++ struct voltagedomain *voltdm = (struct voltagedomain *)data;
+
+- if (!vdd) {
++ if (!voltdm) {
+ pr_warning("Wrong paramater passed\n");
+ return -EINVAL;
+ }
+
+- *val = omap_voltage_get_nom_volt(&vdd->voltdm);
++ *val = omap_voltage_get_nom_volt(voltdm);
+
+ return 0;
+ }
+@@ -172,16 +167,17 @@ static int nom_volt_debug_get(void *data, u64 *val)
+ DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
+ DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+ "%llu\n");
+-static void vp_latch_vsel(struct omap_vdd_info *vdd)
++static void vp_latch_vsel(struct voltagedomain *voltdm)
+ {
+ u32 vpconfig;
+ unsigned long uvdc;
+ char vsel;
++ struct omap_vdd_info *vdd = voltdm->vdd;
+
+- uvdc = omap_voltage_get_nom_volt(&vdd->voltdm);
++ uvdc = omap_voltage_get_nom_volt(voltdm);
+ if (!uvdc) {
+ pr_warning("%s: unable to find current voltage for vdd_%s\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return;
+ }
+
+@@ -209,13 +205,14 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
+ }
+
+ /* Generic voltage init functions */
+-static void __init vp_init(struct omap_vdd_info *vdd)
++static void __init vp_init(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vp_val;
+
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return;
+ }
+
+@@ -246,25 +243,26 @@ static void __init vp_init(struct omap_vdd_info *vdd)
+ vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vlimitto);
+ }
+
+-static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
++static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+ {
+ char *name;
++ struct omap_vdd_info *vdd = voltdm->vdd;
+
+ name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL);
+ if (!name) {
+ pr_warning("%s: Unable to allocate memory for debugfs"
+ " directory name for vdd_%s",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return;
+ }
+ strcpy(name, "vdd_");
+- strcat(name, vdd->voltdm.name);
++ strcat(name, voltdm->name);
+
+ vdd->debug_dir = debugfs_create_dir(name, voltage_dir);
+ kfree(name);
+ if (IS_ERR(vdd->debug_dir)) {
+ pr_warning("%s: Unable to create debugfs directory for"
+- " vdd_%s\n", __func__, vdd->voltdm.name);
++ " vdd_%s\n", __func__, voltdm->name);
+ vdd->debug_dir = NULL;
+ return;
+ }
+@@ -288,16 +286,17 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+ (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
+ &(vdd->vp_rt_data.vlimitto_timeout));
+ (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
+- (void *) vdd, &vp_volt_debug_fops);
++ (void *) voltdm, &vp_volt_debug_fops);
+ (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+- vdd->debug_dir, (void *) vdd,
++ vdd->debug_dir, (void *) voltdm,
+ &nom_volt_debug_fops);
+ }
+
+ /* Voltage scale and accessory APIs */
+-static int _pre_volt_scale(struct omap_vdd_info *vdd,
++static int _pre_volt_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ struct omap_volt_data *volt_data;
+ const struct omap_vc_common_data *vc_common;
+ const struct omap_vp_common_data *vp_common;
+@@ -309,25 +308,25 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+ /* Check if suffiecient pmic info is available for this vdd */
+ if (!vdd->pmic_info) {
+ pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return -EINVAL;
+ }
+
+ if (!vdd->pmic_info->uv_to_vsel) {
+ pr_err("%s: PMIC function to convert voltage in uV to"
+ "vsel not registered. Hence unable to scale voltage"
+- "for vdd_%s\n", __func__, vdd->voltdm.name);
++ "for vdd_%s\n", __func__, voltdm->name);
+ return -ENODATA;
+ }
+
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return -EINVAL;
+ }
+
+ /* Get volt_data corresponding to target_volt */
+- volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
++ volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+ if (IS_ERR(volt_data))
+ volt_data = NULL;
+
+@@ -355,9 +354,10 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+ return 0;
+ }
+
+-static void _post_volt_scale(struct omap_vdd_info *vdd,
++static void _post_volt_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt, u8 target_vsel, u8 current_vsel)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 smps_steps = 0, smps_delay = 0;
+
+ smps_steps = abs(target_vsel - current_vsel);
+@@ -370,15 +370,16 @@ static void _post_volt_scale(struct omap_vdd_info *vdd,
+ }
+
+ /* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
+-static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
++static int vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+ u8 target_vsel, current_vsel;
+ int ret;
+
+- ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel);
++ ret = _pre_volt_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+ return ret;
+
+@@ -417,19 +418,20 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ vc_bypass_val_reg);
+ }
+
+- _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
++ _post_volt_scale(voltdm, target_volt, target_vsel, current_vsel);
+ return 0;
+ }
+
+ /* VP force update method of voltage scaling */
+-static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
++static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vpconfig;
+ u8 target_vsel, current_vsel;
+ int ret, timeout = 0;
+
+- ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel);
++ ret = _pre_volt_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+ return ret;
+
+@@ -447,7 +449,7 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ }
+ if (timeout >= VP_TRANXDONE_TIMEOUT) {
+ pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+- "Voltage change aborted", __func__, vdd->voltdm.name);
++ "Voltage change aborted", __func__, voltdm->name);
+ return -ETIMEDOUT;
+ }
+
+@@ -480,9 +482,9 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+ "TRANXDONE never got set after the voltage update\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+
+- _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
++ _post_volt_scale(voltdm, target_volt, target_vsel, current_vsel);
+
+ /*
+ * Disable TransactionDone interrupt , clear all status, clear
+@@ -501,7 +503,7 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+ pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+ "to clear the TRANXDONE status\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+
+ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+ /* Clear initVDD copy trigger bit */
+@@ -514,8 +516,10 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ return 0;
+ }
+
+-static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
++static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
++
+ /*
+ * Voltage Manager FSM parameters init
+ * XXX This data should be passed in from the board file
+@@ -527,8 +531,9 @@ static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
+ }
+
+-static void __init omap3_vc_init(struct omap_vdd_info *vdd)
++static void __init omap3_vc_init(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+ u32 vc_val;
+@@ -556,15 +561,16 @@ static void __init omap3_vc_init(struct omap_vdd_info *vdd)
+ vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vdd->vc_data->vc_common->prm_mod,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+- omap3_vfsm_init(vdd);
++ omap3_vfsm_init(voltdm);
+
+ is_initialized = true;
+ }
+
+
+ /* OMAP4 specific voltage init functions */
+-static void __init omap4_vc_init(struct omap_vdd_info *vdd)
++static void __init omap4_vc_init(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+ u32 vc_val;
+
+@@ -589,20 +595,21 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+ is_initialized = true;
+ }
+
+-static void __init omap_vc_init(struct omap_vdd_info *vdd)
++static void __init omap_vc_init(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vc_val;
+
+ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+ pr_err("%s: PMIC info requried to configure vc for"
+ "vdd_%s not populated.Hence cannot initialize vc\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return;
+ }
+
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, vdd->voltdm.name);
++ __func__, voltdm->name);
+ return;
+ }
+
+@@ -630,23 +637,24 @@ static void __init omap_vc_init(struct omap_vdd_info *vdd)
+ vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
+
+ if (cpu_is_omap34xx())
+- omap3_vc_init(vdd);
++ omap3_vc_init(voltdm);
+ else if (cpu_is_omap44xx())
+- omap4_vc_init(vdd);
++ omap4_vc_init(voltdm);
+ }
+
+-static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
++static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ {
++ struct omap_vdd_info *vdd = voltdm->vdd;
+ int ret = -EINVAL;
+
+ if (!vdd->pmic_info) {
+ pr_err("%s: PMIC info requried to configure vdd_%s not"
+ "populated.Hence cannot initialize vdd_%s\n",
+- __func__, vdd->voltdm.name, vdd->voltdm.name);
++ __func__, voltdm->name, voltdm->name);
+ goto ovdc_out;
+ }
+
+- if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
++ if (IS_ERR_VALUE(_config_common_vdd_data(voltdm)))
+ goto ovdc_out;
+
+ if (cpu_is_omap34xx()) {
+@@ -680,7 +688,7 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ return vdd->curr_volt;
+ }
+@@ -701,7 +709,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+ if (!vdd->read_reg) {
+ pr_err("%s: No read API for reading vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -736,7 +744,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -747,7 +755,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ if (vdd->vp_enabled)
+ return;
+
+- vp_latch_vsel(vdd);
++ vp_latch_vsel(voltdm);
+
+ /* Enable VP */
+ vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+@@ -774,7 +782,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -827,7 +835,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+ return -EINVAL;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ if (!vdd->volt_scale) {
+ pr_err("%s: No voltage scale API registered for vdd_%s\n",
+@@ -835,7 +843,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+ return -ENODATA;
+ }
+
+- return vdd->volt_scale(vdd, target_volt);
++ return vdd->volt_scale(voltdm, target_volt);
+ }
+
+ /**
+@@ -888,7 +896,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ return;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ *volt_data = vdd->volt_data;
+ }
+@@ -919,7 +927,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ return ERR_PTR(-EINVAL);
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ if (!vdd->volt_data) {
+ pr_warning("%s: voltage table does not exist for vdd_%s\n",
+@@ -957,7 +965,7 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ return -EINVAL;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ vdd->pmic_info = pmic_info;
+
+@@ -984,7 +992,7 @@ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
+ return NULL;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ return vdd->debug_dir;
+ }
+@@ -1009,7 +1017,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ return;
+ }
+
+- vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
++ vdd = voltdm->vdd;
+
+ switch (voltscale_method) {
+ case VOLTSCALE_VPFORCEUPDATE:
+@@ -1025,38 +1033,6 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ }
+
+ /**
+- * omap_voltage_domain_lookup() - API to get the voltage domain pointer
+- * @name: Name of the voltage domain
+- *
+- * This API looks up in the global vdd_info struct for the
+- * existence of voltage domain <name>. If it exists, the API returns
+- * a pointer to the voltage domain structure corresponding to the
+- * VDD<name>. Else retuns error pointer.
+- */
+-struct voltagedomain *omap_voltage_domain_lookup(char *name)
+-{
+- int i;
+-
+- if (!vdd_info) {
+- pr_err("%s: Voltage driver init not yet happened.Faulting!\n",
+- __func__);
+- return ERR_PTR(-EINVAL);
+- }
+-
+- if (!name) {
+- pr_err("%s: No name to get the votage domain!\n", __func__);
+- return ERR_PTR(-EINVAL);
+- }
+-
+- for (i = 0; i < nr_scalable_vdd; i++) {
+- if (!(strcmp(name, vdd_info[i]->voltdm.name)))
+- return &vdd_info[i]->voltdm;
+- }
+-
+- return ERR_PTR(-EINVAL);
+-}
+-
+-/**
+ * omap_voltage_late_init() - Init the various voltage parameters
+ *
+ * This API is to be called in the later stages of the
+@@ -1065,9 +1041,9 @@ struct voltagedomain *omap_voltage_domain_lookup(char *name)
+ */
+ int __init omap_voltage_late_init(void)
+ {
+- int i;
++ struct voltagedomain *voltdm;
+
+- if (!vdd_info) {
++ if (list_empty(&voltdm_list)) {
+ pr_err("%s: Voltage driver support not added\n",
+ __func__);
+ return -EINVAL;
+@@ -1077,22 +1053,81 @@ int __init omap_voltage_late_init(void)
+ if (IS_ERR(voltage_dir))
+ pr_err("%s: Unable to create voltage debugfs main dir\n",
+ __func__);
+- for (i = 0; i < nr_scalable_vdd; i++) {
+- if (omap_vdd_data_configure(vdd_info[i]))
+- continue;
+- omap_vc_init(vdd_info[i]);
+- vp_init(vdd_info[i]);
+- vdd_debugfs_init(vdd_info[i]);
++ list_for_each_entry(voltdm, &voltdm_list, node) {
++ if (voltdm->vdd) {
++ if (omap_vdd_data_configure(voltdm))
++ continue;
++ omap_vc_init(voltdm);
++ vp_init(voltdm);
++ vdd_debugfs_init(voltdm);
++ }
+ }
+
+ return 0;
+ }
+
+-/* XXX document */
+-int __init omap_voltage_early_init(struct omap_vdd_info *omap_vdd_array[],
+- u8 omap_vdd_count)
++static struct voltagedomain *_voltdm_lookup(const char *name)
+ {
+- vdd_info = omap_vdd_array;
+- nr_scalable_vdd = omap_vdd_count;
++ struct voltagedomain *voltdm, *temp_voltdm;
++
++ voltdm = NULL;
++
++ list_for_each_entry(temp_voltdm, &voltdm_list, node) {
++ if (!strcmp(name, temp_voltdm->name)) {
++ voltdm = temp_voltdm;
++ break;
++ }
++ }
++
++ return voltdm;
++}
++
++static int _voltdm_register(struct voltagedomain *voltdm)
++{
++ if (!voltdm || !voltdm->name)
++ return -EINVAL;
++
++ list_add(&voltdm->node, &voltdm_list);
++
++ pr_debug("voltagedomain: registered %s\n", voltdm->name);
++
+ return 0;
+ }
++
++/**
++ * voltdm_lookup - look up a voltagedomain by name, return a pointer
++ * @name: name of voltagedomain
++ *
++ * Find a registered voltagedomain by its name @name. Returns a pointer
++ * to the struct voltagedomain if found, or NULL otherwise.
++ */
++struct voltagedomain *voltdm_lookup(const char *name)
++{
++ struct voltagedomain *voltdm ;
++
++ if (!name)
++ return NULL;
++
++ voltdm = _voltdm_lookup(name);
++
++ return voltdm;
++}
++
++/**
++ * voltdm_init - set up the voltagedomain layer
++ * @voltdm_list: array of struct voltagedomain pointers to register
++ *
++ * Loop through the array of voltagedomains @voltdm_list, registering all
++ * that are available on the current CPU. If voltdm_list is supplied
++ * and not null, all of the referenced voltagedomains will be
++ * registered. No return value.
++ */
++void voltdm_init(struct voltagedomain **voltdms)
++{
++ struct voltagedomain **v;
++
++ if (voltdms) {
++ for (v = voltdms; *v; v++)
++ _voltdm_register(*v);
++ }
++}
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index db23d49..5440298 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -31,6 +31,8 @@
+ #define OMAP3_VOLTOFFSET 0xff
+ #define OMAP3_VOLTSETUP2 0xff
+
++struct omap_vdd_info;
++
+ /**
+ * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
+ * data
+@@ -50,11 +52,14 @@ struct omap_vfsm_instance_data {
+
+ /**
+ * struct voltagedomain - omap voltage domain global structure.
+- * @name: Name of the voltage domain which can be used as a unique
+- * identifier.
++ * @name: Name of the voltage domain which can be used as a unique identifier.
++ * @node: list_head linking all voltage domains
++ * @vdd: to be removed
+ */
+ struct voltagedomain {
+ char *name;
++ struct list_head node;
++ struct omap_vdd_info *vdd;
+ };
+
+ /**
+@@ -116,7 +121,6 @@ struct omap_volt_pmic_info {
+ * @vc_data : structure containing various various vc registers,
+ * shifts, masks etc.
+ * @vfsm : voltage manager FSM data
+- * @voltdm : pointer to the voltage domain structure
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+ * @prm_irqst_mod : PRM module id used for PRM IRQ status register access
+@@ -130,7 +134,6 @@ struct omap_vdd_info {
+ struct omap_vp_runtime_data vp_rt_data;
+ struct omap_vc_instance_data *vc_data;
+ const struct omap_vfsm_instance_data *vfsm;
+- struct voltagedomain voltdm;
+ struct dentry *debug_dir;
+ u32 curr_volt;
+ bool vp_enabled;
+@@ -139,7 +142,7 @@ struct omap_vdd_info {
+ u8 prm_irqst_reg;
+ u32 (*read_reg) (u16 mod, u8 offset);
+ void (*write_reg) (u32 val, u16 mod, u8 offset);
+- int (*volt_scale) (struct omap_vdd_info *vdd,
++ int (*volt_scale) (struct voltagedomain *voltdm,
+ unsigned long target_volt);
+ };
+
+@@ -155,16 +158,11 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ unsigned long volt);
+ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+-int __init omap_voltage_early_init(struct omap_vdd_info *omap_vdd_array[],
+- u8 omap_vdd_count);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ struct omap_volt_pmic_info *pmic_info);
+ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ int voltscale_method);
+-/* API to get the voltagedomain pointer */
+-struct voltagedomain *omap_voltage_domain_lookup(char *name);
+-
+ int omap_voltage_late_init(void);
+ #else
+ static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+@@ -178,10 +176,11 @@ static inline int omap_voltage_late_init(void)
+ {
+ return -EINVAL;
+ }
+-static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
+-{
+- return ERR_PTR(-EINVAL);
+-}
+ #endif
+
++extern void omap3xxx_voltagedomains_init(void);
++extern void omap44xx_voltagedomains_init(void);
++
++struct voltagedomain *voltdm_lookup(const char *name);
++void voltdm_init(struct voltagedomain **voltdm_list);
+ #endif
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index f831f9a..4bee412 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -43,9 +43,6 @@ static struct omap_vdd_info omap3_vdd1_info = {
+ .vp_data = &omap3_vp1_data,
+ .vc_data = &omap3_vc1_data,
+ .vfsm = &omap3_vdd1_vfsm_data,
+- .voltdm = {
+- .name = "mpu",
+- },
+ };
+
+ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+@@ -60,23 +57,26 @@ static struct omap_vdd_info omap3_vdd2_info = {
+ .vp_data = &omap3_vp2_data,
+ .vc_data = &omap3_vc2_data,
+ .vfsm = &omap3_vdd2_vfsm_data,
+- .voltdm = {
+- .name = "core",
+- },
+ };
+
+-/* OMAP3 VDD structures */
+-static struct omap_vdd_info *omap3_vdd_info[] = {
+- &omap3_vdd1_info,
+- &omap3_vdd2_info,
++static struct voltagedomain omap3_voltdm_mpu = {
++ .name = "mpu",
++ .vdd = &omap3_vdd1_info,
+ };
+
+-/* OMAP3 specific voltage init functions */
+-static int __init omap3xxx_voltage_early_init(void)
+-{
+- if (!cpu_is_omap34xx())
+- return 0;
++static struct voltagedomain omap3_voltdm_core = {
++ .name = "core",
++ .vdd = &omap3_vdd2_info,
++};
+
++static struct voltagedomain *voltagedomains_omap3[] __initdata = {
++ &omap3_voltdm_mpu,
++ &omap3_voltdm_core,
++ NULL,
++};
++
++void __init omap3xxx_voltagedomains_init(void)
++{
+ /*
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC
+@@ -89,7 +89,5 @@ static int __init omap3xxx_voltage_early_init(void)
+ omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
+ }
+
+- return omap_voltage_early_init(omap3_vdd_info,
+- ARRAY_SIZE(omap3_vdd_info));
++ voltdm_init(voltagedomains_omap3);
+ };
+-core_initcall(omap3xxx_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 64dc265..245fdf9 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -42,9 +42,6 @@ static struct omap_vdd_info omap4_vdd_mpu_info = {
+ .vp_data = &omap4_vp_mpu_data,
+ .vc_data = &omap4_vc_mpu_data,
+ .vfsm = &omap4_vdd_mpu_vfsm_data,
+- .voltdm = {
+- .name = "mpu",
+- },
+ };
+
+ static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+@@ -57,9 +54,6 @@ static struct omap_vdd_info omap4_vdd_iva_info = {
+ .vp_data = &omap4_vp_iva_data,
+ .vc_data = &omap4_vc_iva_data,
+ .vfsm = &omap4_vdd_iva_vfsm_data,
+- .voltdm = {
+- .name = "iva",
+- },
+ };
+
+ static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+@@ -72,24 +66,32 @@ static struct omap_vdd_info omap4_vdd_core_info = {
+ .vp_data = &omap4_vp_core_data,
+ .vc_data = &omap4_vc_core_data,
+ .vfsm = &omap4_vdd_core_vfsm_data,
+- .voltdm = {
+- .name = "core",
+- },
+ };
+
+-/* OMAP4 VDD structures */
+-static struct omap_vdd_info *omap4_vdd_info[] = {
+- &omap4_vdd_mpu_info,
+- &omap4_vdd_iva_info,
+- &omap4_vdd_core_info,
++static struct voltagedomain omap4_voltdm_mpu = {
++ .name = "mpu",
++ .vdd = &omap4_vdd_mpu_info,
+ };
+
+-/* OMAP4 specific voltage init functions */
+-static int __init omap44xx_voltage_early_init(void)
+-{
+- if (!cpu_is_omap44xx())
+- return 0;
++static struct voltagedomain omap4_voltdm_iva = {
++ .name = "iva",
++ .vdd = &omap4_vdd_iva_info,
++};
++
++static struct voltagedomain omap4_voltdm_core = {
++ .name = "core",
++ .vdd = &omap4_vdd_core_info,
++};
+
++static struct voltagedomain *voltagedomains_omap4[] __initdata = {
++ &omap4_voltdm_mpu,
++ &omap4_voltdm_iva,
++ &omap4_voltdm_core,
++ NULL,
++};
++
++void __init omap44xx_voltagedomains_init(void)
++{
+ /*
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC
+@@ -98,7 +100,5 @@ static int __init omap44xx_voltage_early_init(void)
+ omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+ omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
+
+- return omap_voltage_early_init(omap4_vdd_info,
+- ARRAY_SIZE(omap4_vdd_info));
++ voltdm_init(voltagedomains_omap4);
+ };
+-core_initcall(omap44xx_voltage_early_init);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0100-OMAP3-voltage-rename-mpu-voltagedomain-to-mpu_iva.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0100-OMAP3-voltage-rename-mpu-voltagedomain-to-mpu_iva.patch
--- /dev/null
@@ -0,0 +1,82 @@
+From 3773058cdb4d2045c86f828353dfe31ddfaa4c83 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 23 Mar 2011 11:18:08 -0700
+Subject: [PATCH 100/149] OMAP3: voltage: rename "mpu" voltagedomain to "mpu_iva"
+
+This voltage domain (a.k.a. VDD1) contains both the MPU and the IVA, so
+rename appropriately.
+
+Also fixup any users of the "mpu" name to use "mpu_iva"
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4 ++--
+ arch/arm/mach-omap2/omap_twl.c | 2 +-
+ arch/arm/mach-omap2/pm.c | 2 +-
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 2 +-
+ 4 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 25bf43b..59fdb9f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -2597,7 +2597,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
+ .name = "sr1_hwmod",
+ .class = &omap34xx_smartreflex_hwmod_class,
+ .main_clk = "sr1_fck",
+- .vdd_name = "mpu",
++ .vdd_name = "mpu_iva",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+@@ -2619,7 +2619,7 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
+ .name = "sr1_hwmod",
+ .class = &omap36xx_smartreflex_hwmod_class,
+ .main_clk = "sr1_fck",
+- .vdd_name = "mpu",
++ .vdd_name = "mpu_iva",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index fcd2f62..760487b 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -288,7 +288,7 @@ int __init omap3_twl_init(void)
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
+- voltdm = voltdm_lookup("mpu");
++ voltdm = voltdm_lookup("mpu_iva");
+ omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
+
+ voltdm = voltdm_lookup("core");
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 3bce29b..f81340e 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -228,7 +228,7 @@ static void __init omap3_init_voltages(void)
+ if (!cpu_is_omap34xx())
+ return;
+
+- omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
++ omap2_set_init_voltage("mpu_iva", "dpll1_ck", mpu_dev);
+ omap2_set_init_voltage("core", "l3_ick", l3_dev);
+ }
+
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 4bee412..2167ef4 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -60,7 +60,7 @@ static struct omap_vdd_info omap3_vdd2_info = {
+ };
+
+ static struct voltagedomain omap3_voltdm_mpu = {
+- .name = "mpu",
++ .name = "mpu_iva",
+ .vdd = &omap3_vdd1_info,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0101-OMAP3-voltagedomain-data-add-wakeup-domain.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0101-OMAP3-voltagedomain-data-add-wakeup-domain.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0101-OMAP3-voltagedomain-data-add-wakeup-domain.patch
@@ -0,0 +1,37 @@
+From 41bc3f2ed28c59135def4c8c2807f136ced889bd Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 23 Mar 2011 13:30:33 -0700
+Subject: [PATCH 101/149] OMAP3: voltagedomain data: add wakeup domain
+
+Add wakeup voltage domain so that the wakeup powerdomain can have an
+associated powerdomain. Note that the scalable flat is not set for
+the this voltagedomain, so it will not be fully initialized like
+scalable voltage domains.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 2167ef4..42d0b11 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -69,9 +69,14 @@ static struct voltagedomain omap3_voltdm_core = {
+ .vdd = &omap3_vdd2_info,
+ };
+
++static struct voltagedomain omap3_voltdm_wkup = {
++ .name = "wakeup",
++};
++
+ static struct voltagedomain *voltagedomains_omap3[] __initdata = {
+ &omap3_voltdm_mpu,
+ &omap3_voltdm_core,
++ &omap3_voltdm_wkup,
+ NULL,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0102-OMAP3-voltage-add-scalable-flag-to-voltagedomain.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0102-OMAP3-voltage-add-scalable-flag-to-voltagedomain.patch
--- /dev/null
@@ -0,0 +1,93 @@
+From 93ea3f18fadde0402331871869793f8721b605ee Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 23 Mar 2011 17:00:21 -0700
+Subject: [PATCH 102/149] OMAP3+: voltage: add scalable flag to voltagedomain
+
+Add a 'bool scalable' flag to the struct powerdomain and set it for
+the scalable domains on OMAP3 and OMAP4.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 3 +++
+ arch/arm/mach-omap2/voltage.h | 2 ++
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 2 ++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 3 +++
+ 4 files changed, 10 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 4f0361a..48a2593 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -1054,6 +1054,9 @@ int __init omap_voltage_late_init(void)
+ pr_err("%s: Unable to create voltage debugfs main dir\n",
+ __func__);
+ list_for_each_entry(voltdm, &voltdm_list, node) {
++ if (!voltdm->scalable)
++ continue;
++
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+ continue;
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 5440298..25cfb5c 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -53,11 +53,13 @@ struct omap_vfsm_instance_data {
+ /**
+ * struct voltagedomain - omap voltage domain global structure.
+ * @name: Name of the voltage domain which can be used as a unique identifier.
++ * @scalable: Whether or not this voltage domain is scalable
+ * @node: list_head linking all voltage domains
+ * @vdd: to be removed
+ */
+ struct voltagedomain {
+ char *name;
++ bool scalable;
+ struct list_head node;
+ struct omap_vdd_info *vdd;
+ };
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 42d0b11..d7e1052 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -61,11 +61,13 @@ static struct omap_vdd_info omap3_vdd2_info = {
+
+ static struct voltagedomain omap3_voltdm_mpu = {
+ .name = "mpu_iva",
++ .scalable = true,
+ .vdd = &omap3_vdd1_info,
+ };
+
+ static struct voltagedomain omap3_voltdm_core = {
+ .name = "core",
++ .scalable = true,
+ .vdd = &omap3_vdd2_info,
+ };
+
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 245fdf9..95e1ce5 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -70,16 +70,19 @@ static struct omap_vdd_info omap4_vdd_core_info = {
+
+ static struct voltagedomain omap4_voltdm_mpu = {
+ .name = "mpu",
++ .scalable = true,
+ .vdd = &omap4_vdd_mpu_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_iva = {
+ .name = "iva",
++ .scalable = true,
+ .vdd = &omap4_vdd_iva_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_core = {
+ .name = "core",
++ .scalable = true,
+ .vdd = &omap4_vdd_core_info,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0103-OMAP2-powerdomain-add-voltagedomain-to-struct-powerd.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0103-OMAP2-powerdomain-add-voltagedomain-to-struct-powerd.patch
--- /dev/null
@@ -0,0 +1,51 @@
+From f8ad469a2588e82d357fccb2c75462ee42e98e22 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 23 Mar 2011 07:22:23 -0700
+Subject: [PATCH 103/149] OMAP2+: powerdomain: add voltagedomain to struct powerdomain
+
+Each powerdomain is associated with a voltage domain. Add an entry to
+struct powerdomain where the enclosing voltagedomain can be
+referenced.
+
+Modeled after similar relationship between clockdomains and powerdomains.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/powerdomain.h | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
+index d23d979..9ce920d 100644
+--- a/arch/arm/mach-omap2/powerdomain.h
++++ b/arch/arm/mach-omap2/powerdomain.h
+@@ -24,6 +24,8 @@
+
+ #include <plat/cpu.h>
+
++#include "voltage.h"
++
+ /* Powerdomain basic power states */
+ #define PWRDM_POWER_OFF 0x0
+ #define PWRDM_POWER_RET 0x1
+@@ -78,6 +80,7 @@ struct powerdomain;
+ /**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
++ * @voltdm: voltagedomain containing this powerdomain
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
+@@ -98,6 +101,10 @@ struct powerdomain;
+ */
+ struct powerdomain {
+ const char *name;
++ union {
++ const char *name;
++ struct voltagedomain *ptr;
++ } voltdm;
+ const struct omap_chip_id omap_chip;
+ const s16 prcm_offs;
+ const u8 pwrsts;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0104-OMAP2-add-voltage-domains-and-connect-to-powerdomain.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0104-OMAP2-add-voltage-domains-and-connect-to-powerdomain.patch
--- /dev/null
@@ -0,0 +1,138 @@
+From c878d9950cd3d7524a9fe90ab69826f42d07843b Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 23 Mar 2011 16:09:41 -0700
+Subject: [PATCH 104/149] OMAP2: add voltage domains and connect to powerdomains
+
+Create basic voltagedomains for OMAP2 and associate OMAP2 powerdomains
+with the newly created voltage domains.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 3 +-
+ arch/arm/mach-omap2/io.c | 2 +
+ arch/arm/mach-omap2/powerdomains2xxx_data.c | 4 +++
+ arch/arm/mach-omap2/voltage.h | 1 +
+ arch/arm/mach-omap2/voltagedomains2xxx_data.c | 32 +++++++++++++++++++++++++
+ 5 files changed, 41 insertions(+), 1 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/voltagedomains2xxx_data.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index f343365..1b6cecd 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -91,7 +91,8 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+ # OMAP voltage domains
+ ifeq ($(CONFIG_PM),y)
+ voltagedomain-common := voltage.o
+-obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
++obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
++ voltagedomains2xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
+ voltagedomains3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 9f5a846..4c8a5de 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -342,10 +342,12 @@ void __init omap2_init_common_infrastructure(void)
+ u8 postsetup_state;
+
+ if (cpu_is_omap242x()) {
++ omap2xxx_voltagedomains_init();
+ omap2xxx_powerdomains_init();
+ omap2xxx_clockdomains_init();
+ omap2420_hwmod_init();
+ } else if (cpu_is_omap243x()) {
++ omap2xxx_voltagedomains_init();
+ omap2xxx_powerdomains_init();
+ omap2xxx_clockdomains_init();
+ omap2430_hwmod_init();
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+index cc389fb..274f64c 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+@@ -38,6 +38,7 @@ static struct powerdomain dsp_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON,
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain mpu_24xx_pwrdm = {
+@@ -53,6 +54,7 @@ static struct powerdomain mpu_24xx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON,
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain core_24xx_pwrdm = {
+@@ -71,6 +73,7 @@ static struct powerdomain core_24xx_pwrdm = {
+ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+
+@@ -95,6 +98,7 @@ static struct powerdomain mdm_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ #endif /* CONFIG_SOC_OMAP2430 */
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 25cfb5c..cacd76e 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -180,6 +180,7 @@ static inline int omap_voltage_late_init(void)
+ }
+ #endif
+
++extern void omap2xxx_voltagedomains_init(void);
+ extern void omap3xxx_voltagedomains_init(void);
+ extern void omap44xx_voltagedomains_init(void);
+
+diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
+new file mode 100644
+index 0000000..69ff261
+--- /dev/null
++++ b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
+@@ -0,0 +1,32 @@
++/*
++ * OMAP3 voltage domain data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++
++#include "voltage.h"
++
++static struct voltagedomain omap2_voltdm_core = {
++ .name = "core",
++};
++
++static struct voltagedomain omap2_voltdm_wkup = {
++ .name = "wakeup",
++};
++
++static struct voltagedomain *voltagedomains_omap2[] __initdata = {
++ &omap2_voltdm_core,
++ &omap2_voltdm_wkup,
++ NULL,
++};
++
++void __init omap2xxx_voltagedomains_init(void)
++{
++ voltdm_init(voltagedomains_omap2);
++}
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0105-OMAP3-powerdomain-data-add-voltage-domains.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0105-OMAP3-powerdomain-data-add-voltage-domains.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0105-OMAP3-powerdomain-data-add-voltage-domains.patch
@@ -0,0 +1,161 @@
+From 595cfecd088ff8aaf211b8f20a946a7688bb4edb Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Fri, 18 Mar 2011 14:12:18 -0700
+Subject: [PATCH 105/149] OMAP3: powerdomain data: add voltage domains
+
+Add voltage domain name to indicate which voltagedomain each
+powerdomain is in.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 2 ++
+ arch/arm/mach-omap2/powerdomains3xxx_data.c | 16 ++++++++++++++++
+ 2 files changed, 18 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+index 4210c33..2242c8e 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+@@ -70,6 +70,7 @@ struct powerdomain gfx_omap2_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ struct powerdomain wkup_omap2_pwrdm = {
+@@ -77,4 +78,5 @@ struct powerdomain wkup_omap2_pwrdm = {
+ .prcm_offs = WKUP_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+ .pwrsts = PWRSTS_ON,
++ .voltdm = { .name = "wakeup" },
+ };
+diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
+index 469a920..1f37c0c 100644
+--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
+@@ -52,6 +52,7 @@ static struct powerdomain iva2_pwrdm = {
+ [2] = PWRSTS_OFF_ON,
+ [3] = PWRSTS_ON,
+ },
++ .voltdm = { .name = "mpu_iva" },
+ };
+
+ static struct powerdomain mpu_3xxx_pwrdm = {
+@@ -68,6 +69,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_ON,
+ },
++ .voltdm = { .name = "mpu_iva" },
+ };
+
+ /*
+@@ -98,6 +100,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
+ [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain core_3xxx_es3_1_pwrdm = {
+@@ -121,6 +124,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
+ [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain dss_pwrdm = {
+@@ -136,6 +140,7 @@ static struct powerdomain dss_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ /*
+@@ -157,6 +162,7 @@ static struct powerdomain sgx_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain cam_pwrdm = {
+@@ -172,6 +178,7 @@ static struct powerdomain cam_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain per_pwrdm = {
+@@ -187,12 +194,14 @@ static struct powerdomain per_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain emu_pwrdm = {
+ .name = "emu_pwrdm",
+ .prcm_offs = OMAP3430_EMU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain neon_pwrdm = {
+@@ -201,6 +210,7 @@ static struct powerdomain neon_pwrdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
++ .voltdm = { .name = "mpu_iva" },
+ };
+
+ static struct powerdomain usbhost_pwrdm = {
+@@ -223,36 +233,42 @@ static struct powerdomain usbhost_pwrdm = {
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain dpll1_pwrdm = {
+ .name = "dpll1_pwrdm",
+ .prcm_offs = MPU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ .voltdm = { .name = "mpu_iva" },
+ };
+
+ static struct powerdomain dpll2_pwrdm = {
+ .name = "dpll2_pwrdm",
+ .prcm_offs = OMAP3430_IVA2_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ .voltdm = { .name = "mpu_iva" },
+ };
+
+ static struct powerdomain dpll3_pwrdm = {
+ .name = "dpll3_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain dpll4_pwrdm = {
+ .name = "dpll4_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ .voltdm = { .name = "core" },
+ };
+
+ static struct powerdomain dpll5_pwrdm = {
+ .name = "dpll5_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
++ .voltdm = { .name = "core" },
+ };
+
+ /* As powerdomains are added or removed above, this list must also be changed */
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0106-OMAP4-powerdomain-data-add-voltage-domains.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0106-OMAP4-powerdomain-data-add-voltage-domains.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0106-OMAP4-powerdomain-data-add-voltage-domains.patch
@@ -0,0 +1,177 @@
+From c4ce93f86e7242b3f167601be92e8dbd3bcd72e2 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Mon, 21 Mar 2011 12:11:54 +0100
+Subject: [PATCH 106/149] OMAP4: powerdomain data: add voltage domains
+
+Add voltage domain name to indicate which voltagedomain each
+powerdomain is in.
+
+The fixed voltage domain like ldo_wakeup for emu and wkup power
+domain is added too.
+
+Update the TI copyright date to 2011.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+[khilman@ti.com]: renamed wakeup domain: s/ldo_wakeup/wakeup/
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 16 ++++++++++++++++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 5 +++++
+ 2 files changed, 21 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index 247e794..45c7f29 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -33,6 +33,7 @@
+ /* core_44xx_pwrdm: CORE power domain */
+ static struct powerdomain core_44xx_pwrdm = {
+ .name = "core_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_CORE_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -59,6 +60,7 @@ static struct powerdomain core_44xx_pwrdm = {
+ /* gfx_44xx_pwrdm: 3D accelerator power domain */
+ static struct powerdomain gfx_44xx_pwrdm = {
+ .name = "gfx_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_GFX_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -76,6 +78,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
+ /* abe_44xx_pwrdm: Audio back end power domain */
+ static struct powerdomain abe_44xx_pwrdm = {
+ .name = "abe_pwrdm",
++ .voltdm = { .name = "iva" },
+ .prcm_offs = OMAP4430_PRM_ABE_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -96,6 +99,7 @@ static struct powerdomain abe_44xx_pwrdm = {
+ /* dss_44xx_pwrdm: Display subsystem power domain */
+ static struct powerdomain dss_44xx_pwrdm = {
+ .name = "dss_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_DSS_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -114,6 +118,7 @@ static struct powerdomain dss_44xx_pwrdm = {
+ /* tesla_44xx_pwrdm: Tesla processor power domain */
+ static struct powerdomain tesla_44xx_pwrdm = {
+ .name = "tesla_pwrdm",
++ .voltdm = { .name = "iva" },
+ .prcm_offs = OMAP4430_PRM_TESLA_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -136,6 +141,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
+ /* wkup_44xx_pwrdm: Wake-up power domain */
+ static struct powerdomain wkup_44xx_pwrdm = {
+ .name = "wkup_pwrdm",
++ .voltdm = { .name = "wakeup" },
+ .prcm_offs = OMAP4430_PRM_WKUP_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -152,6 +158,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
+ /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+ static struct powerdomain cpu0_44xx_pwrdm = {
+ .name = "cpu0_pwrdm",
++ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
+ .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -169,6 +176,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
+ /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+ static struct powerdomain cpu1_44xx_pwrdm = {
+ .name = "cpu1_pwrdm",
++ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
+ .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -186,6 +194,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
+ /* emu_44xx_pwrdm: Emulation power domain */
+ static struct powerdomain emu_44xx_pwrdm = {
+ .name = "emu_pwrdm",
++ .voltdm = { .name = "wakeup" },
+ .prcm_offs = OMAP4430_PRM_EMU_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -202,6 +211,7 @@ static struct powerdomain emu_44xx_pwrdm = {
+ /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+ static struct powerdomain mpu_44xx_pwrdm = {
+ .name = "mpu_pwrdm",
++ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP4430_PRM_MPU_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -223,6 +233,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
+ /* ivahd_44xx_pwrdm: IVA-HD power domain */
+ static struct powerdomain ivahd_44xx_pwrdm = {
+ .name = "ivahd_pwrdm",
++ .voltdm = { .name = "iva" },
+ .prcm_offs = OMAP4430_PRM_IVAHD_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -247,6 +258,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
+ /* cam_44xx_pwrdm: Camera subsystem power domain */
+ static struct powerdomain cam_44xx_pwrdm = {
+ .name = "cam_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_CAM_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -264,6 +276,7 @@ static struct powerdomain cam_44xx_pwrdm = {
+ /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
+ static struct powerdomain l3init_44xx_pwrdm = {
+ .name = "l3init_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_L3INIT_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -282,6 +295,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
+ /* l4per_44xx_pwrdm: Target peripherals power domain */
+ static struct powerdomain l4per_44xx_pwrdm = {
+ .name = "l4per_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_L4PER_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -305,6 +319,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
+ */
+ static struct powerdomain always_on_core_44xx_pwrdm = {
+ .name = "always_on_core_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -314,6 +329,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
+ /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
+ static struct powerdomain cefuse_44xx_pwrdm = {
+ .name = "cefuse_pwrdm",
++ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP4430_PRM_CEFUSE_INST,
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 95e1ce5..9a17b5e 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -86,10 +86,15 @@ static struct voltagedomain omap4_voltdm_core = {
+ .vdd = &omap4_vdd_core_info,
+ };
+
++static struct voltagedomain omap4_voltdm_wkup = {
++ .name = "wakeup",
++};
++
+ static struct voltagedomain *voltagedomains_omap4[] __initdata = {
+ &omap4_voltdm_mpu,
+ &omap4_voltdm_iva,
+ &omap4_voltdm_core,
++ &omap4_voltdm_wkup,
+ NULL,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0107-OMAP2-powerdomain-add-voltage-domain-lookup-during-r.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0107-OMAP2-powerdomain-add-voltage-domain-lookup-during-r.patch
--- /dev/null
@@ -0,0 +1,89 @@
+From 73e5197e2861d26462a67d9796bedd7d84c81687 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 15:52:47 -0700
+Subject: [PATCH 107/149] OMAP2+: powerdomain: add voltage domain lookup during register
+
+When a powerdomain is registered, lookup the voltage domain by name
+and keep a pointer to the containing voltagedomain in the powerdomain
+structure.
+
+Modeled after similar method between powerdomain and clockdomain layers.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/powerdomain.c | 21 +++++++++++++++++++++
+ arch/arm/mach-omap2/powerdomain.h | 1 +
+ arch/arm/mach-omap2/voltage.h | 1 +
+ 3 files changed, 23 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
+index 9af0847..1d3013d 100644
+--- a/arch/arm/mach-omap2/powerdomain.c
++++ b/arch/arm/mach-omap2/powerdomain.c
+@@ -77,6 +77,7 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
+ static int _pwrdm_register(struct powerdomain *pwrdm)
+ {
+ int i;
++ struct voltagedomain *voltdm;
+
+ if (!pwrdm || !pwrdm->name)
+ return -EINVAL;
+@@ -94,6 +95,14 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
+ if (_pwrdm_lookup(pwrdm->name))
+ return -EEXIST;
+
++ voltdm = voltdm_lookup(pwrdm->voltdm.name);
++ if (!voltdm) {
++ pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
++ pwrdm->name, pwrdm->voltdm.name);
++ return -EINVAL;
++ }
++ pwrdm->voltdm.ptr = voltdm;
++
+ list_add(&pwrdm->node, &pwrdm_list);
+
+ /* Initialize the powerdomain's state counter */
+@@ -383,6 +392,18 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+ }
+
+ /**
++ * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
++ * @pwrdm: struct powerdomain *
++ *
++ * Return a pointer to the struct voltageomain that the specified powerdomain
++ * @pwrdm exists in.
++ */
++struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
++{
++ return pwrdm->voltdm.ptr;
++}
++
++/**
+ * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
+ * @pwrdm: struct powerdomain *
+ *
+diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
+index 9ce920d..25bef48 100644
+--- a/arch/arm/mach-omap2/powerdomain.h
++++ b/arch/arm/mach-omap2/powerdomain.h
+@@ -183,6 +183,7 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+ int (*fn)(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm));
++struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
+
+ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index cacd76e..966aa88 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -186,4 +186,5 @@ extern void omap44xx_voltagedomains_init(void);
+
+ struct voltagedomain *voltdm_lookup(const char *name);
+ void voltdm_init(struct voltagedomain **voltdm_list);
++int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0108-OMAP2-voltage-keep-track-of-powerdomains-in-each-vol.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0108-OMAP2-voltage-keep-track-of-powerdomains-in-each-vol.patch
--- /dev/null
@@ -0,0 +1,200 @@
+From 6575b52f36e82696802c1eee40bbad5bebedeab7 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 16 Mar 2011 16:13:15 -0700
+Subject: [PATCH 108/149] OMAP2+: voltage: keep track of powerdomains in each voltagedomain
+
+When a powerdomain is registered and it has an associated voltage domain,
+add the powerdomain to the voltagedomain using voltdm_add_pwrdm().
+
+Also add voltagedomain iterator helper functions to iterate over all
+registered voltagedomains and all powerdomains associated with a
+voltagedomain.
+
+Modeled after a similar relationship between clockdomains and powerdomains.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/powerdomain.c | 2 +
+ arch/arm/mach-omap2/powerdomain.h | 2 +
+ arch/arm/mach-omap2/voltage.c | 80 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/voltage.h | 10 +++++
+ 4 files changed, 94 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
+index 1d3013d..12135e2 100644
+--- a/arch/arm/mach-omap2/powerdomain.c
++++ b/arch/arm/mach-omap2/powerdomain.c
+@@ -102,6 +102,8 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
+ return -EINVAL;
+ }
+ pwrdm->voltdm.ptr = voltdm;
++ INIT_LIST_HEAD(&pwrdm->voltdm_node);
++ voltdm_add_pwrdm(voltdm, pwrdm);
+
+ list_add(&pwrdm->node, &pwrdm_list);
+
+diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
+index 25bef48..2c685a5 100644
+--- a/arch/arm/mach-omap2/powerdomain.h
++++ b/arch/arm/mach-omap2/powerdomain.h
+@@ -92,6 +92,7 @@ struct powerdomain;
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
++ * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @state:
+ * @state_counter:
+ * @timer:
+@@ -116,6 +117,7 @@ struct powerdomain {
+ const u8 prcm_partition;
+ struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
+ struct list_head node;
++ struct list_head voltdm_node;
+ int state;
+ unsigned state_counter[PWRDM_MAX_PWRSTS];
+ unsigned ret_logic_off_counter;
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 48a2593..1e5c122 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -36,6 +36,7 @@
+ #include "control.h"
+
+ #include "voltage.h"
++#include "powerdomain.h"
+
+ #include "vc.h"
+ #include "vp.h"
+@@ -1085,11 +1086,90 @@ static struct voltagedomain *_voltdm_lookup(const char *name)
+ return voltdm;
+ }
+
++/**
++ * voltdm_add_pwrdm - add a powerdomain to a voltagedomain
++ * @voltdm: struct voltagedomain * to add the powerdomain to
++ * @pwrdm: struct powerdomain * to associate with a voltagedomain
++ *
++ * Associate the powerdomain @pwrdm with a voltagedomain @voltdm. This
++ * enables the use of voltdm_for_each_pwrdm(). Returns -EINVAL if
++ * presented with invalid pointers; -ENOMEM if memory could not be allocated;
++ * or 0 upon success.
++ */
++int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
++{
++ if (!voltdm || !pwrdm)
++ return -EINVAL;
++
++ pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
++ "%s\n", pwrdm->name, voltdm->name);
++
++ list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
++
++ return 0;
++}
++
++/**
++ * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
++ * @voltdm: struct voltagedomain * to iterate over
++ * @fn: callback function *
++ *
++ * Call the supplied function @fn for each powerdomain in the
++ * voltagedomain @voltdm. Returns -EINVAL if presented with invalid
++ * pointers; or passes along the last return value of the callback
++ * function, which should be 0 for success or anything else to
++ * indicate failure.
++ */
++int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
++ int (*fn)(struct voltagedomain *voltdm,
++ struct powerdomain *pwrdm))
++{
++ struct powerdomain *pwrdm;
++ int ret = 0;
++
++ if (!fn)
++ return -EINVAL;
++
++ list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
++ ret = (*fn)(voltdm, pwrdm);
++
++ return ret;
++}
++
++/**
++ * voltdm_for_each - call function on each registered voltagedomain
++ * @fn: callback function *
++ *
++ * Call the supplied function @fn for each registered voltagedomain.
++ * The callback function @fn can return anything but 0 to bail out
++ * early from the iterator. Returns the last return value of the
++ * callback function, which should be 0 for success or anything else
++ * to indicate failure; or -EINVAL if the function pointer is null.
++ */
++int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
++ void *user)
++{
++ struct voltagedomain *temp_voltdm;
++ int ret = 0;
++
++ if (!fn)
++ return -EINVAL;
++
++ list_for_each_entry(temp_voltdm, &voltdm_list, node) {
++ ret = (*fn)(temp_voltdm, user);
++ if (ret)
++ break;
++ }
++
++ return ret;
++}
++
+ static int _voltdm_register(struct voltagedomain *voltdm)
+ {
+ if (!voltdm || !voltdm->name)
+ return -EINVAL;
+
++ INIT_LIST_HEAD(&voltdm->pwrdm_list);
+ list_add(&voltdm->node, &voltdm_list);
+
+ pr_debug("voltagedomain: registered %s\n", voltdm->name);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 966aa88..b41d9f1 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -19,6 +19,8 @@
+ #include "vc.h"
+ #include "vp.h"
+
++struct powerdomain;
++
+ /* XXX document */
+ #define VOLTSCALE_VPFORCEUPDATE 1
+ #define VOLTSCALE_VCBYPASS 2
+@@ -55,12 +57,15 @@ struct omap_vfsm_instance_data {
+ * @name: Name of the voltage domain which can be used as a unique identifier.
+ * @scalable: Whether or not this voltage domain is scalable
+ * @node: list_head linking all voltage domains
++ * @pwrdm_node: list_head linking all powerdomains in this voltagedomain
+ * @vdd: to be removed
++ * @pwrdms: powerdomains in this voltagedomain
+ */
+ struct voltagedomain {
+ char *name;
+ bool scalable;
+ struct list_head node;
++ struct list_head pwrdm_list;
+ struct omap_vdd_info *vdd;
+ };
+
+@@ -187,4 +192,9 @@ extern void omap44xx_voltagedomains_init(void);
+ struct voltagedomain *voltdm_lookup(const char *name);
+ void voltdm_init(struct voltagedomain **voltdm_list);
+ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
++int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
++ void *user);
++int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
++ int (*fn)(struct voltagedomain *voltdm,
++ struct powerdomain *pwrdm));
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0109-OMAP2-voltage-split-voltage-controller-VC-code-into-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0109-OMAP2-voltage-split-voltage-controller-VC-code-into-.patch
--- /dev/null
@@ -0,0 +1,666 @@
+From 39ad303f0ef9e85f85f4e06a356d878d965d1b82 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 21 Mar 2011 14:08:55 -0700
+Subject: [PATCH 109/149] OMAP2+: voltage: split voltage controller (VC) code into dedicated layer
+
+As part of the voltage layer cleanup, split out VC specific code into
+a dedicated VC layer. This patch primarily just moves VC code from
+voltage.c into vc.c, and adds prototypes to vc.h.
+
+No functional changes.
+
+For readability, each function was given a local 'vc' pointer:
+
+ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
+
+and a global replace of s/vdd->vc_data/vc/ was done.
+
+Also vc_init was renamed to vc_init_channel to reflect that this is
+per-VC channel initializtion.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/vc.c | 276 +++++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/vc.h | 12 ++
+ arch/arm/mach-omap2/voltage.c | 264 +--------------------------------------
+ 4 files changed, 293 insertions(+), 261 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/vc.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 1b6cecd..ecbf361 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -90,7 +90,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+
+ # OMAP voltage domains
+ ifeq ($(CONFIG_PM),y)
+-voltagedomain-common := voltage.o
++voltagedomain-common := voltage.o vc.o
+ obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
+ voltagedomains2xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+new file mode 100644
+index 0000000..98f5a4b
+--- /dev/null
++++ b/arch/arm/mach-omap2/vc.c
+@@ -0,0 +1,276 @@
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++
++#include <plat/cpu.h>
++
++#include "voltage.h"
++#include "vc.h"
++#include "prm-regbits-34xx.h"
++#include "prm-regbits-44xx.h"
++#include "prm44xx.h"
++
++/* Voltage scale and accessory APIs */
++int omap_vc_pre_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt,
++ u8 *target_vsel, u8 *current_vsel)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ struct omap_volt_data *volt_data;
++ const struct omap_vc_common_data *vc_common;
++ const struct omap_vp_common_data *vp_common;
++ u32 vc_cmdval, vp_errgain_val;
++
++ vc_common = vc->vc_common;
++ vp_common = vdd->vp_data->vp_common;
++
++ /* Check if sufficient pmic info is available for this vdd */
++ if (!vdd->pmic_info) {
++ pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
++ __func__, voltdm->name);
++ return -EINVAL;
++ }
++
++ if (!vdd->pmic_info->uv_to_vsel) {
++ pr_err("%s: PMIC function to convert voltage in uV to"
++ "vsel not registered. Hence unable to scale voltage"
++ "for vdd_%s\n", __func__, voltdm->name);
++ return -ENODATA;
++ }
++
++ if (!vdd->read_reg || !vdd->write_reg) {
++ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
++ __func__, voltdm->name);
++ return -EINVAL;
++ }
++
++ /* Get volt_data corresponding to target_volt */
++ volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
++ if (IS_ERR(volt_data))
++ volt_data = NULL;
++
++ *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
++ *current_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
++
++ /* Setting the ON voltage to the new target voltage */
++ vc_cmdval = vdd->read_reg(vc->vc_common->prm_mod, vc->cmdval_reg);
++ vc_cmdval &= ~vc_common->cmd_on_mask;
++ vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
++ vdd->write_reg(vc_cmdval, vc->vc_common->prm_mod, vc->cmdval_reg);
++
++ /* Setting vp errorgain based on the voltage */
++ if (volt_data) {
++ vp_errgain_val = vdd->read_reg(vdd->vp_data->vp_common->prm_mod,
++ vdd->vp_data->vpconfig);
++ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
++ vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
++ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
++ vp_common->vpconfig_errorgain_shift;
++ vdd->write_reg(vp_errgain_val, vdd->vp_data->vp_common->prm_mod,
++ vdd->vp_data->vpconfig);
++ }
++
++ return 0;
++}
++
++void omap_vc_post_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt,
++ u8 target_vsel, u8 current_vsel)
++{
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 smps_steps = 0, smps_delay = 0;
++
++ smps_steps = abs(target_vsel - current_vsel);
++ /* SMPS slew rate / step size. 2us added as buffer. */
++ smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
++ vdd->pmic_info->slew_rate) + 2;
++ udelay(smps_delay);
++
++ vdd->curr_volt = target_volt;
++}
++
++/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
++int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
++ unsigned long target_volt)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 loop_cnt = 0, retries_cnt = 0;
++ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
++ u8 target_vsel, current_vsel;
++ int ret;
++
++ ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
++ if (ret)
++ return ret;
++
++ vc_valid = vc->vc_common->valid;
++ vc_bypass_val_reg = vc->vc_common->bypass_val_reg;
++ vc_bypass_value = (target_vsel << vc->vc_common->data_shift) |
++ (vdd->pmic_info->pmic_reg <<
++ vc->vc_common->regaddr_shift) |
++ (vdd->pmic_info->i2c_slave_addr <<
++ vc->vc_common->slaveaddr_shift);
++
++ vdd->write_reg(vc_bypass_value, vc->vc_common->prm_mod, vc_bypass_val_reg);
++ vdd->write_reg(vc_bypass_value | vc_valid, vc->vc_common->prm_mod,
++ vc_bypass_val_reg);
++
++ vc_bypass_value = vdd->read_reg(vc->vc_common->prm_mod, vc_bypass_val_reg);
++ /*
++ * Loop till the bypass command is acknowledged from the SMPS.
++ * NOTE: This is legacy code. The loop count and retry count needs
++ * to be revisited.
++ */
++ while (!(vc_bypass_value & vc_valid)) {
++ loop_cnt++;
++
++ if (retries_cnt > 10) {
++ pr_warning("%s: Retry count exceeded\n", __func__);
++ return -ETIMEDOUT;
++ }
++
++ if (loop_cnt > 50) {
++ retries_cnt++;
++ loop_cnt = 0;
++ udelay(10);
++ }
++ vc_bypass_value = vdd->read_reg(vc->vc_common->prm_mod,
++ vc_bypass_val_reg);
++ }
++
++ omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
++ return 0;
++}
++
++static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++
++ /*
++ * Voltage Manager FSM parameters init
++ * XXX This data should be passed in from the board file
++ */
++ vdd->write_reg(OMAP3_CLKSETUP, vc->vc_common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
++ vdd->write_reg(OMAP3_VOLTOFFSET, vc->vc_common->prm_mod,
++ OMAP3_PRM_VOLTOFFSET_OFFSET);
++ vdd->write_reg(OMAP3_VOLTSETUP2, vc->vc_common->prm_mod,
++ OMAP3_PRM_VOLTSETUP2_OFFSET);
++}
++
++static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ static bool is_initialized;
++ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
++ u32 vc_val;
++
++ if (is_initialized)
++ return;
++
++ /* Set up the on, inactive, retention and off voltage */
++ on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
++ onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
++ ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
++ off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
++ vc_val = ((on_vsel << vc->vc_common->cmd_on_shift) |
++ (onlp_vsel << vc->vc_common->cmd_onlp_shift) |
++ (ret_vsel << vc->vc_common->cmd_ret_shift) |
++ (off_vsel << vc->vc_common->cmd_off_shift));
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod, vc->cmdval_reg);
++
++ /*
++ * Generic VC parameters init
++ * XXX This data should be abstracted out
++ */
++ vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vc->vc_common->prm_mod,
++ OMAP3_PRM_VC_CH_CONF_OFFSET);
++ vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vc->vc_common->prm_mod,
++ OMAP3_PRM_VC_I2C_CFG_OFFSET);
++
++ omap3_vfsm_init(voltdm);
++
++ is_initialized = true;
++}
++
++
++/* OMAP4 specific voltage init functions */
++static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ static bool is_initialized;
++ u32 vc_val;
++
++ if (is_initialized)
++ return;
++
++ /* TODO: Configure setup times and CMD_VAL values*/
++
++ /*
++ * Generic VC parameters init
++ * XXX This data should be abstracted out
++ */
++ vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
++ OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
++ OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
++
++ /* XXX These are magic numbers and do not belong! */
++ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
++
++ is_initialized = true;
++}
++
++void __init omap_vc_init_channel(struct voltagedomain *voltdm)
++{
++ struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 vc_val;
++
++ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
++ pr_err("%s: PMIC info requried to configure vc for"
++ "vdd_%s not populated.Hence cannot initialize vc\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ if (!vdd->read_reg || !vdd->write_reg) {
++ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ /* Set up the SMPS_SA(i2c slave address in VC */
++ vc_val = vdd->read_reg(vc->vc_common->prm_mod,
++ vc->vc_common->smps_sa_reg);
++ vc_val &= ~vc->smps_sa_mask;
++ vc_val |= vdd->pmic_info->i2c_slave_addr << vc->smps_sa_shift;
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod,
++ vc->vc_common->smps_sa_reg);
++
++ /* Setup the VOLRA(pmic reg addr) in VC */
++ vc_val = vdd->read_reg(vc->vc_common->prm_mod,
++ vc->vc_common->smps_volra_reg);
++ vc_val &= ~vc->smps_volra_mask;
++ vc_val |= vdd->pmic_info->pmic_reg << vc->smps_volra_shift;
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod,
++ vc->vc_common->smps_volra_reg);
++
++ /* Configure the setup times */
++ vc_val = vdd->read_reg(vc->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
++ vc_val &= ~vdd->vfsm->voltsetup_mask;
++ vc_val |= vdd->pmic_info->volt_setup_time <<
++ vdd->vfsm->voltsetup_shift;
++ vdd->write_reg(vc_val, vc->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
++
++ if (cpu_is_omap34xx())
++ omap3_vc_init_channel(voltdm);
++ else if (cpu_is_omap44xx())
++ omap4_vc_init_channel(voltdm);
++}
++
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index f7338af..d0bf348 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -19,6 +19,8 @@
+
+ #include <linux/kernel.h>
+
++struct voltagedomain;
++
+ /**
+ * struct omap_vc_common_data - per-VC register/bitfield data
+ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+@@ -81,5 +83,15 @@ extern struct omap_vc_instance_data omap4_vc_mpu_data;
+ extern struct omap_vc_instance_data omap4_vc_iva_data;
+ extern struct omap_vc_instance_data omap4_vc_core_data;
+
++void omap_vc_init_channel(struct voltagedomain *voltdm);
++int omap_vc_pre_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt,
++ u8 *target_vsel, u8 *current_vsel);
++void omap_vc_post_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt,
++ u8 target_vsel, u8 current_vsel);
++int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
++ unsigned long target_volt);
++
+ #endif
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 1e5c122..6ba6e49 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -293,136 +293,6 @@ static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+ &nom_volt_debug_fops);
+ }
+
+-/* Voltage scale and accessory APIs */
+-static int _pre_volt_scale(struct voltagedomain *voltdm,
+- unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- struct omap_volt_data *volt_data;
+- const struct omap_vc_common_data *vc_common;
+- const struct omap_vp_common_data *vp_common;
+- u32 vc_cmdval, vp_errgain_val;
+-
+- vc_common = vdd->vc_data->vc_common;
+- vp_common = vdd->vp_data->vp_common;
+-
+- /* Check if suffiecient pmic info is available for this vdd */
+- if (!vdd->pmic_info) {
+- pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+- __func__, voltdm->name);
+- return -EINVAL;
+- }
+-
+- if (!vdd->pmic_info->uv_to_vsel) {
+- pr_err("%s: PMIC function to convert voltage in uV to"
+- "vsel not registered. Hence unable to scale voltage"
+- "for vdd_%s\n", __func__, voltdm->name);
+- return -ENODATA;
+- }
+-
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, voltdm->name);
+- return -EINVAL;
+- }
+-
+- /* Get volt_data corresponding to target_volt */
+- volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+- if (IS_ERR(volt_data))
+- volt_data = NULL;
+-
+- *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+- *current_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+-
+- /* Setting the ON voltage to the new target voltage */
+- vc_cmdval = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+- vc_cmdval &= ~vc_common->cmd_on_mask;
+- vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
+- vdd->write_reg(vc_cmdval, vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+-
+- /* Setting vp errorgain based on the voltage */
+- if (volt_data) {
+- vp_errgain_val = vdd->read_reg(vdd->vp_data->vp_common->prm_mod,
+- vdd->vp_data->vpconfig);
+- vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+- vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
+- vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+- vp_common->vpconfig_errorgain_shift;
+- vdd->write_reg(vp_errgain_val, vdd->vp_data->vp_common->prm_mod,
+- vdd->vp_data->vpconfig);
+- }
+-
+- return 0;
+-}
+-
+-static void _post_volt_scale(struct voltagedomain *voltdm,
+- unsigned long target_volt, u8 target_vsel, u8 current_vsel)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 smps_steps = 0, smps_delay = 0;
+-
+- smps_steps = abs(target_vsel - current_vsel);
+- /* SMPS slew rate / step size. 2us added as buffer. */
+- smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
+- vdd->pmic_info->slew_rate) + 2;
+- udelay(smps_delay);
+-
+- vdd->curr_volt = target_volt;
+-}
+-
+-/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
+-static int vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+- unsigned long target_volt)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 loop_cnt = 0, retries_cnt = 0;
+- u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+- u8 target_vsel, current_vsel;
+- int ret;
+-
+- ret = _pre_volt_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+- if (ret)
+- return ret;
+-
+- vc_valid = vdd->vc_data->vc_common->valid;
+- vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
+- vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
+- (vdd->pmic_info->pmic_reg <<
+- vdd->vc_data->vc_common->regaddr_shift) |
+- (vdd->pmic_info->i2c_slave_addr <<
+- vdd->vc_data->vc_common->slaveaddr_shift);
+-
+- vdd->write_reg(vc_bypass_value, vdd->vc_data->vc_common->prm_mod, vc_bypass_val_reg);
+- vdd->write_reg(vc_bypass_value | vc_valid, vdd->vc_data->vc_common->prm_mod,
+- vc_bypass_val_reg);
+-
+- vc_bypass_value = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vc_bypass_val_reg);
+- /*
+- * Loop till the bypass command is acknowledged from the SMPS.
+- * NOTE: This is legacy code. The loop count and retry count needs
+- * to be revisited.
+- */
+- while (!(vc_bypass_value & vc_valid)) {
+- loop_cnt++;
+-
+- if (retries_cnt > 10) {
+- pr_warning("%s: Retry count exceeded\n", __func__);
+- return -ETIMEDOUT;
+- }
+-
+- if (loop_cnt > 50) {
+- retries_cnt++;
+- loop_cnt = 0;
+- udelay(10);
+- }
+- vc_bypass_value = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+- vc_bypass_val_reg);
+- }
+-
+- _post_volt_scale(voltdm, target_volt, target_vsel, current_vsel);
+- return 0;
+-}
+-
+ /* VP force update method of voltage scaling */
+ static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+@@ -432,7 +302,7 @@ static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ u8 target_vsel, current_vsel;
+ int ret, timeout = 0;
+
+- ret = _pre_volt_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
++ ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+ if (ret)
+ return ret;
+
+@@ -485,7 +355,7 @@ static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ "TRANXDONE never got set after the voltage update\n",
+ __func__, voltdm->name);
+
+- _post_volt_scale(voltdm, target_volt, target_vsel, current_vsel);
++ omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+
+ /*
+ * Disable TransactionDone interrupt , clear all status, clear
+@@ -517,132 +387,6 @@ static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+ return 0;
+ }
+
+-static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+-
+- /*
+- * Voltage Manager FSM parameters init
+- * XXX This data should be passed in from the board file
+- */
+- vdd->write_reg(OMAP3_CLKSETUP, vdd->vc_data->vc_common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
+- vdd->write_reg(OMAP3_VOLTOFFSET, vdd->vc_data->vc_common->prm_mod,
+- OMAP3_PRM_VOLTOFFSET_OFFSET);
+- vdd->write_reg(OMAP3_VOLTSETUP2, vdd->vc_data->vc_common->prm_mod,
+- OMAP3_PRM_VOLTSETUP2_OFFSET);
+-}
+-
+-static void __init omap3_vc_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- static bool is_initialized;
+- u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+- u32 vc_val;
+-
+- if (is_initialized)
+- return;
+-
+- /* Set up the on, inactive, retention and off voltage */
+- on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+- onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+- ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+- off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+- vc_val = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
+- (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
+- (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
+- (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, vdd->vc_data->cmdval_reg);
+-
+- /*
+- * Generic VC parameters init
+- * XXX This data should be abstracted out
+- */
+- vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vdd->vc_data->vc_common->prm_mod,
+- OMAP3_PRM_VC_CH_CONF_OFFSET);
+- vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vdd->vc_data->vc_common->prm_mod,
+- OMAP3_PRM_VC_I2C_CFG_OFFSET);
+-
+- omap3_vfsm_init(voltdm);
+-
+- is_initialized = true;
+-}
+-
+-
+-/* OMAP4 specific voltage init functions */
+-static void __init omap4_vc_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- static bool is_initialized;
+- u32 vc_val;
+-
+- if (is_initialized)
+- return;
+-
+- /* TODO: Configure setup times and CMD_VAL values*/
+-
+- /*
+- * Generic VC parameters init
+- * XXX This data should be abstracted out
+- */
+- vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+- OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+- OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+-
+- /* XXX These are magic numbers and do not belong! */
+- vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+-
+- is_initialized = true;
+-}
+-
+-static void __init omap_vc_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vc_val;
+-
+- if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+- pr_err("%s: PMIC info requried to configure vc for"
+- "vdd_%s not populated.Hence cannot initialize vc\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+- vdd->vc_data->vc_common->smps_sa_reg);
+- vc_val &= ~vdd->vc_data->smps_sa_mask;
+- vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod,
+- vdd->vc_data->vc_common->smps_sa_reg);
+-
+- /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod,
+- vdd->vc_data->vc_common->smps_volra_reg);
+- vc_val &= ~vdd->vc_data->smps_volra_mask;
+- vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod,
+- vdd->vc_data->vc_common->smps_volra_reg);
+-
+- /* Configure the setup times */
+- vc_val = vdd->read_reg(vdd->vc_data->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
+- vc_val &= ~vdd->vfsm->voltsetup_mask;
+- vc_val |= vdd->pmic_info->volt_setup_time <<
+- vdd->vfsm->voltsetup_shift;
+- vdd->write_reg(vc_val, vdd->vc_data->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
+-
+- if (cpu_is_omap34xx())
+- omap3_vc_init(voltdm);
+- else if (cpu_is_omap44xx())
+- omap4_vc_init(voltdm);
+-}
+-
+ static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ {
+ struct omap_vdd_info *vdd = voltdm->vdd;
+@@ -1025,7 +769,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ vdd->volt_scale = vp_forceupdate_scale_voltage;
+ return;
+ case VOLTSCALE_VCBYPASS:
+- vdd->volt_scale = vc_bypass_scale_voltage;
++ vdd->volt_scale = omap_vc_bypass_scale_voltage;
+ return;
+ default:
+ pr_warning("%s: Trying to change the method of voltage scaling"
+@@ -1061,7 +805,7 @@ int __init omap_voltage_late_init(void)
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+ continue;
+- omap_vc_init(voltdm);
++ omap_vc_init_channel(voltdm);
+ vp_init(voltdm);
+ vdd_debugfs_init(voltdm);
+ }
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0110-OMAP2-voltage-move-VC-into-struct-voltagedomain-misc.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0110-OMAP2-voltage-move-VC-into-struct-voltagedomain-misc.patch
--- /dev/null
@@ -0,0 +1,544 @@
+From f3ab67725a755e84f957e131386461ea3bb5bbea Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 22 Mar 2011 16:14:57 -0700
+Subject: [PATCH 110/149] OMAP2+: voltage: move VC into struct voltagedomain, misc. renames
+
+Move the VC instance struct from omap_vdd_info into struct voltagedomain.
+While moving, perform some misc. renames for readability.
+
+No functional changes.
+
+Summary of renames:
+- rename omap_vc_instance to omap_vc_channel, since there is only
+ one instance of the VC IP and this actually represents channels
+ using TRM terminology.
+- rename 'vc_common' field of VC channel which led to:
+ s/vc->vc_common/vc->common/
+- remove redundant '_data' suffix
+- OMAP3: vc1 --> vc_mpu, vc2 --> vc_core
+- omap_vc_bypass_scale_voltage() -> omap_vc_bypass_scale()
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+
+merge
+---
+ arch/arm/mach-omap2/vc.c | 90 ++++++++++++-------------
+ arch/arm/mach-omap2/vc.h | 26 ++++----
+ arch/arm/mach-omap2/vc3xxx_data.c | 10 ++--
+ arch/arm/mach-omap2/vc44xx_data.c | 14 ++--
+ arch/arm/mach-omap2/voltage.c | 6 +-
+ arch/arm/mach-omap2/voltage.h | 5 +-
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 4 +-
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 6 +-
+ 8 files changed, 80 insertions(+), 81 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 98f5a4b..7643940 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -15,14 +15,12 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt,
+ u8 *target_vsel, u8 *current_vsel)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ struct omap_volt_data *volt_data;
+- const struct omap_vc_common_data *vc_common;
+ const struct omap_vp_common_data *vp_common;
+ u32 vc_cmdval, vp_errgain_val;
+
+- vc_common = vc->vc_common;
+ vp_common = vdd->vp_data->vp_common;
+
+ /* Check if sufficient pmic info is available for this vdd */
+@@ -54,10 +52,10 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ *current_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+
+ /* Setting the ON voltage to the new target voltage */
+- vc_cmdval = vdd->read_reg(vc->vc_common->prm_mod, vc->cmdval_reg);
+- vc_cmdval &= ~vc_common->cmd_on_mask;
+- vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
+- vdd->write_reg(vc_cmdval, vc->vc_common->prm_mod, vc->cmdval_reg);
++ vc_cmdval = vdd->read_reg(vc->common->prm_mod, vc->cmdval_reg);
++ vc_cmdval &= ~vc->common->cmd_on_mask;
++ vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
++ vdd->write_reg(vc_cmdval, vc->common->prm_mod, vc->cmdval_reg);
+
+ /* Setting vp errorgain based on the voltage */
+ if (volt_data) {
+@@ -90,11 +88,11 @@ void omap_vc_post_scale(struct voltagedomain *voltdm,
+ vdd->curr_volt = target_volt;
+ }
+
+-/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
+-int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+- unsigned long target_volt)
++/* vc_bypass_scale - VC bypass method of voltage scaling */
++int omap_vc_bypass_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+@@ -105,19 +103,19 @@ int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+ if (ret)
+ return ret;
+
+- vc_valid = vc->vc_common->valid;
+- vc_bypass_val_reg = vc->vc_common->bypass_val_reg;
+- vc_bypass_value = (target_vsel << vc->vc_common->data_shift) |
++ vc_valid = vc->common->valid;
++ vc_bypass_val_reg = vc->common->bypass_val_reg;
++ vc_bypass_value = (target_vsel << vc->common->data_shift) |
+ (vdd->pmic_info->pmic_reg <<
+- vc->vc_common->regaddr_shift) |
++ vc->common->regaddr_shift) |
+ (vdd->pmic_info->i2c_slave_addr <<
+- vc->vc_common->slaveaddr_shift);
++ vc->common->slaveaddr_shift);
+
+- vdd->write_reg(vc_bypass_value, vc->vc_common->prm_mod, vc_bypass_val_reg);
+- vdd->write_reg(vc_bypass_value | vc_valid, vc->vc_common->prm_mod,
++ vdd->write_reg(vc_bypass_value, vc->common->prm_mod, vc_bypass_val_reg);
++ vdd->write_reg(vc_bypass_value | vc_valid, vc->common->prm_mod,
+ vc_bypass_val_reg);
+
+- vc_bypass_value = vdd->read_reg(vc->vc_common->prm_mod, vc_bypass_val_reg);
++ vc_bypass_value = vdd->read_reg(vc->common->prm_mod, vc_bypass_val_reg);
+ /*
+ * Loop till the bypass command is acknowledged from the SMPS.
+ * NOTE: This is legacy code. The loop count and retry count needs
+@@ -136,7 +134,7 @@ int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+ loop_cnt = 0;
+ udelay(10);
+ }
+- vc_bypass_value = vdd->read_reg(vc->vc_common->prm_mod,
++ vc_bypass_value = vdd->read_reg(vc->common->prm_mod,
+ vc_bypass_val_reg);
+ }
+
+@@ -146,23 +144,23 @@ int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+
+ static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+
+ /*
+ * Voltage Manager FSM parameters init
+ * XXX This data should be passed in from the board file
+ */
+- vdd->write_reg(OMAP3_CLKSETUP, vc->vc_common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
+- vdd->write_reg(OMAP3_VOLTOFFSET, vc->vc_common->prm_mod,
++ vdd->write_reg(OMAP3_CLKSETUP, vc->common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
++ vdd->write_reg(OMAP3_VOLTOFFSET, vc->common->prm_mod,
+ OMAP3_PRM_VOLTOFFSET_OFFSET);
+- vdd->write_reg(OMAP3_VOLTSETUP2, vc->vc_common->prm_mod,
++ vdd->write_reg(OMAP3_VOLTSETUP2, vc->common->prm_mod,
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
+ }
+
+ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+@@ -176,19 +174,19 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+ ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+ off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+- vc_val = ((on_vsel << vc->vc_common->cmd_on_shift) |
+- (onlp_vsel << vc->vc_common->cmd_onlp_shift) |
+- (ret_vsel << vc->vc_common->cmd_ret_shift) |
+- (off_vsel << vc->vc_common->cmd_off_shift));
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod, vc->cmdval_reg);
++ vc_val = ((on_vsel << vc->common->cmd_on_shift) |
++ (onlp_vsel << vc->common->cmd_onlp_shift) |
++ (ret_vsel << vc->common->cmd_ret_shift) |
++ (off_vsel << vc->common->cmd_off_shift));
++ vdd->write_reg(vc_val, vc->common->prm_mod, vc->cmdval_reg);
+
+ /*
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+ */
+- vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vc->vc_common->prm_mod,
++ vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vc->common->prm_mod,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+- vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vc->vc_common->prm_mod,
++ vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vc->common->prm_mod,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ omap3_vfsm_init(voltdm);
+@@ -200,7 +198,7 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ /* OMAP4 specific voltage init functions */
+ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+ u32 vc_val;
+@@ -217,18 +215,18 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+ OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+ OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
++ vdd->write_reg(vc_val, vc->common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+ /* XXX These are magic numbers and do not belong! */
+ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
++ vdd->write_reg(vc_val, vc->common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+ is_initialized = true;
+ }
+
+ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;
++ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vc_val;
+
+@@ -246,27 +244,27 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ }
+
+ /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(vc->vc_common->prm_mod,
+- vc->vc_common->smps_sa_reg);
++ vc_val = vdd->read_reg(vc->common->prm_mod,
++ vc->common->smps_sa_reg);
+ vc_val &= ~vc->smps_sa_mask;
+ vc_val |= vdd->pmic_info->i2c_slave_addr << vc->smps_sa_shift;
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod,
+- vc->vc_common->smps_sa_reg);
++ vdd->write_reg(vc_val, vc->common->prm_mod,
++ vc->common->smps_sa_reg);
+
+ /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(vc->vc_common->prm_mod,
+- vc->vc_common->smps_volra_reg);
++ vc_val = vdd->read_reg(vc->common->prm_mod,
++ vc->common->smps_volra_reg);
+ vc_val &= ~vc->smps_volra_mask;
+ vc_val |= vdd->pmic_info->pmic_reg << vc->smps_volra_shift;
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod,
+- vc->vc_common->smps_volra_reg);
++ vdd->write_reg(vc_val, vc->common->prm_mod,
++ vc->common->smps_volra_reg);
+
+ /* Configure the setup times */
+- vc_val = vdd->read_reg(vc->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
++ vc_val = vdd->read_reg(vc->common->prm_mod, vdd->vfsm->voltsetup_reg);
+ vc_val &= ~vdd->vfsm->voltsetup_mask;
+ vc_val |= vdd->pmic_info->volt_setup_time <<
+ vdd->vfsm->voltsetup_shift;
+- vdd->write_reg(vc_val, vc->vc_common->prm_mod, vdd->vfsm->voltsetup_reg);
++ vdd->write_reg(vc_val, vc->common->prm_mod, vdd->vfsm->voltsetup_reg);
+
+ if (cpu_is_omap34xx())
+ omap3_vc_init_channel(voltdm);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index d0bf348..51d36a8 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -22,7 +22,7 @@
+ struct voltagedomain;
+
+ /**
+- * struct omap_vc_common_data - per-VC register/bitfield data
++ * struct omap_vc_common - per-VC register/bitfield data
+ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+ * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
+ * @prm_mod: PRM module id used for PRM register access
+@@ -40,7 +40,7 @@ struct voltagedomain;
+ * XXX One of cmd_on_mask and cmd_on_shift are not needed
+ * XXX VALID should probably be a shift, not a mask
+ */
+-struct omap_vc_common_data {
++struct omap_vc_common {
+ u32 cmd_on_mask;
+ u32 valid;
+ s16 prm_mod;
+@@ -57,8 +57,8 @@ struct omap_vc_common_data {
+ };
+
+ /**
+- * struct omap_vc_instance_data - VC per-instance data
+- * @vc_common: pointer to VC common data for this platform
++ * struct omap_vc_channel - VC per-instance data
++ * @common: pointer to VC common data for this platform
+ * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
+@@ -67,8 +67,8 @@ struct omap_vc_common_data {
+ * XXX It is not necessary to have both a *_mask and a *_shift -
+ * remove one
+ */
+-struct omap_vc_instance_data {
+- const struct omap_vc_common_data *vc_common;
++struct omap_vc_channel {
++ const struct omap_vc_common *common;
+ u32 smps_sa_mask;
+ u32 smps_volra_mask;
+ u8 cmdval_reg;
+@@ -76,12 +76,12 @@ struct omap_vc_instance_data {
+ u8 smps_volra_shift;
+ };
+
+-extern struct omap_vc_instance_data omap3_vc1_data;
+-extern struct omap_vc_instance_data omap3_vc2_data;
++extern struct omap_vc_channel omap3_vc_mpu;
++extern struct omap_vc_channel omap3_vc_core;
+
+-extern struct omap_vc_instance_data omap4_vc_mpu_data;
+-extern struct omap_vc_instance_data omap4_vc_iva_data;
+-extern struct omap_vc_instance_data omap4_vc_core_data;
++extern struct omap_vc_channel omap4_vc_mpu;
++extern struct omap_vc_channel omap4_vc_iva;
++extern struct omap_vc_channel omap4_vc_core;
+
+ void omap_vc_init_channel(struct voltagedomain *voltdm);
+ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+@@ -90,8 +90,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ void omap_vc_post_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt,
+ u8 target_vsel, u8 current_vsel);
+-int omap_vc_bypass_scale_voltage(struct voltagedomain *voltdm,
+- unsigned long target_volt);
++int omap_vc_bypass_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt);
+
+ #endif
+
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index 55caccb..1a17ed4 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -29,7 +29,7 @@
+ * VC data common to 34xx/36xx chips
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+-static struct omap_vc_common_data omap3_vc_common = {
++static struct omap_vc_common omap3_vc_common = {
+ .prm_mod = OMAP3430_GR_MOD,
+ .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+@@ -45,8 +45,8 @@ static struct omap_vc_common_data omap3_vc_common = {
+ .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
+ };
+
+-struct omap_vc_instance_data omap3_vc1_data = {
+- .vc_common = &omap3_vc_common,
++struct omap_vc_channel omap3_vc_mpu = {
++ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
+ .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+@@ -54,8 +54,8 @@ struct omap_vc_instance_data omap3_vc1_data = {
+ .smps_volra_mask = OMAP3430_VOLRA0_MASK,
+ };
+
+-struct omap_vc_instance_data omap3_vc2_data = {
+- .vc_common = &omap3_vc_common,
++struct omap_vc_channel omap3_vc_core = {
++ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
+ .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index b62678e..56f3f4a 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -30,7 +30,7 @@
+ * VC data common to 44xx chips
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+-static const struct omap_vc_common_data omap4_vc_common = {
++static const struct omap_vc_common omap4_vc_common = {
+ .prm_mod = OMAP4430_PRM_DEVICE_INST,
+ .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+@@ -47,8 +47,8 @@ static const struct omap_vc_common_data omap4_vc_common = {
+ };
+
+ /* VC instance data for each controllable voltage line */
+-struct omap_vc_instance_data omap4_vc_mpu_data = {
+- .vc_common = &omap4_vc_common,
++struct omap_vc_channel omap4_vc_mpu = {
++ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+ .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+@@ -56,8 +56,8 @@ struct omap_vc_instance_data omap4_vc_mpu_data = {
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
+ };
+
+-struct omap_vc_instance_data omap4_vc_iva_data = {
+- .vc_common = &omap4_vc_common,
++struct omap_vc_channel omap4_vc_iva = {
++ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
+ .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
+@@ -65,8 +65,8 @@ struct omap_vc_instance_data omap4_vc_iva_data = {
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
+ };
+
+-struct omap_vc_instance_data omap4_vc_core_data = {
+- .vc_common = &omap4_vc_common,
++struct omap_vc_channel omap4_vc_core = {
++ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
+ .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 6ba6e49..c6352e3 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -769,7 +769,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ vdd->volt_scale = vp_forceupdate_scale_voltage;
+ return;
+ case VOLTSCALE_VCBYPASS:
+- vdd->volt_scale = omap_vc_bypass_scale_voltage;
++ vdd->volt_scale = omap_vc_bypass_scale;
+ return;
+ default:
+ pr_warning("%s: Trying to change the method of voltage scaling"
+@@ -802,10 +802,12 @@ int __init omap_voltage_late_init(void)
+ if (!voltdm->scalable)
+ continue;
+
++ if (voltdm->vc)
++ omap_vc_init_channel(voltdm);
++
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+ continue;
+- omap_vc_init_channel(voltdm);
+ vp_init(voltdm);
+ vdd_debugfs_init(voltdm);
+ }
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index b41d9f1..b06e03f 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -66,6 +66,8 @@ struct voltagedomain {
+ bool scalable;
+ struct list_head node;
+ struct list_head pwrdm_list;
++ struct omap_vc_channel *vc;
++
+ struct omap_vdd_info *vdd;
+ };
+
+@@ -125,8 +127,6 @@ struct omap_volt_pmic_info {
+ * @vp_data : the register values, shifts, masks for various
+ * vp registers
+ * @vp_rt_data : VP data derived at runtime, not predefined
+- * @vc_data : structure containing various various vc registers,
+- * shifts, masks etc.
+ * @vfsm : voltage manager FSM data
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+@@ -139,7 +139,6 @@ struct omap_vdd_info {
+ struct omap_volt_pmic_info *pmic_info;
+ struct omap_vp_instance_data *vp_data;
+ struct omap_vp_runtime_data vp_rt_data;
+- struct omap_vc_instance_data *vc_data;
+ const struct omap_vfsm_instance_data *vfsm;
+ struct dentry *debug_dir;
+ u32 curr_volt;
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index d7e1052..7cb27ec 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -41,7 +41,6 @@ static struct omap_vdd_info omap3_vdd1_info = {
+ .prm_irqst_mod = OCP_MOD,
+ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp1_data,
+- .vc_data = &omap3_vc1_data,
+ .vfsm = &omap3_vdd1_vfsm_data,
+ };
+
+@@ -55,19 +54,20 @@ static struct omap_vdd_info omap3_vdd2_info = {
+ .prm_irqst_mod = OCP_MOD,
+ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp2_data,
+- .vc_data = &omap3_vc2_data,
+ .vfsm = &omap3_vdd2_vfsm_data,
+ };
+
+ static struct voltagedomain omap3_voltdm_mpu = {
+ .name = "mpu_iva",
+ .scalable = true,
++ .vc = &omap3_vc_mpu,
+ .vdd = &omap3_vdd1_info,
+ };
+
+ static struct voltagedomain omap3_voltdm_core = {
+ .name = "core",
+ .scalable = true,
++ .vc = &omap3_vc_core,
+ .vdd = &omap3_vdd2_info,
+ };
+
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 9a17b5e..a05d90a 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -40,7 +40,6 @@ static struct omap_vdd_info omap4_vdd_mpu_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+ .vp_data = &omap4_vp_mpu_data,
+- .vc_data = &omap4_vc_mpu_data,
+ .vfsm = &omap4_vdd_mpu_vfsm_data,
+ };
+
+@@ -52,7 +51,6 @@ static struct omap_vdd_info omap4_vdd_iva_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_iva_data,
+- .vc_data = &omap4_vc_iva_data,
+ .vfsm = &omap4_vdd_iva_vfsm_data,
+ };
+
+@@ -64,25 +62,27 @@ static struct omap_vdd_info omap4_vdd_core_info = {
+ .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_core_data,
+- .vc_data = &omap4_vc_core_data,
+ .vfsm = &omap4_vdd_core_vfsm_data,
+ };
+
+ static struct voltagedomain omap4_voltdm_mpu = {
+ .name = "mpu",
+ .scalable = true,
++ .vc = &omap4_vc_mpu,
+ .vdd = &omap4_vdd_mpu_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_iva = {
+ .name = "iva",
+ .scalable = true,
++ .vc = &omap4_vc_iva,
+ .vdd = &omap4_vdd_iva_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_core = {
+ .name = "core",
+ .scalable = true,
++ .vc = &omap4_vc_core,
+ .vdd = &omap4_vdd_core_info,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0111-OMAP2-voltage-enable-VC-bypass-scale-method-when-VC-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0111-OMAP2-voltage-enable-VC-bypass-scale-method-when-VC-.patch
--- /dev/null
@@ -0,0 +1,37 @@
+From 62a89781df3eef1d865b6da4c0714e19dad59535 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 18 Jul 2011 15:48:22 -0700
+Subject: [PATCH 111/149] OMAP2+: voltage: enable VC bypass scale method when VC is initialized
+
+VC is initialized first, set default scaling method to VC bypass.
+If/when VP is initialized, default scaling method will be changed to
+VP force-update.
+
+Enabling VC bypass as default as soon as VC is initialized allows for
+VC bypass scaling to work when no VP is configured/initialized for a
+given voltage domain.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index c6352e3..e1a22a3 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -802,8 +802,10 @@ int __init omap_voltage_late_init(void)
+ if (!voltdm->scalable)
+ continue;
+
+- if (voltdm->vc)
++ if (voltdm->vc) {
++ voltdm->vdd->volt_scale = omap_vc_bypass_scale;
+ omap_vc_init_channel(voltdm);
++ }
+
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0112-OMAP2-voltage-split-out-voltage-processor-VP-code-in.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0112-OMAP2-voltage-split-out-voltage-processor-VP-code-in.patch
--- /dev/null
@@ -0,0 +1,874 @@
+From 3051846afad9af89e30726b8e5c5c42cb71e9a30 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 21 Mar 2011 14:29:13 -0700
+Subject: [PATCH 112/149] OMAP2+: voltage: split out voltage processor (VP) code into new layer
+
+This patch is primarily a move of VP specific code from voltage.c into
+its own code in vp.c and adds prototypes to vp.h
+
+No functional changes, except debugfs...
+
+VP debugfs moved to 'vp' subdir of <debugfs>/voltage/ and 'vp_'
+prefixes removed from all debugfs filenames.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/voltage.c | 348 +-------------------------------------
+ arch/arm/mach-omap2/voltage.h | 3 -
+ arch/arm/mach-omap2/vp.c | 374 +++++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/vp.h | 9 +
+ 5 files changed, 387 insertions(+), 349 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/vp.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index ecbf361..8e79ca5 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -90,7 +90,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+
+ # OMAP voltage domains
+ ifeq ($(CONFIG_PM),y)
+-voltagedomain-common := voltage.o vc.o
++voltagedomain-common := voltage.o vc.o vp.o
+ obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
+ voltagedomains2xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index e1a22a3..9b9f019 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -46,10 +46,6 @@ static LIST_HEAD(voltdm_list);
+ #define VOLTAGE_DIR_SIZE 16
+ static struct dentry *voltage_dir;
+
+-/* Init function pointers */
+-static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+- unsigned long target_volt);
+-
+ static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+ {
+ return omap2_prm_read_mod_reg(mod, offset);
+@@ -105,7 +101,7 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ sys_clk_speed /= 1000;
+
+ /* Generic voltage parameters */
+- vdd->volt_scale = vp_forceupdate_scale_voltage;
++ vdd->volt_scale = omap_vp_forceupdate_scale;
+ vdd->vp_enabled = false;
+
+ vdd->vp_rt_data.vpconfig_erroroffset =
+@@ -127,30 +123,6 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+-/* Voltage debugfs support */
+-static int vp_volt_debug_get(void *data, u64 *val)
+-{
+- struct voltagedomain *voltdm = (struct voltagedomain *)data;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u8 vsel;
+-
+- if (!vdd) {
+- pr_warning("Wrong paramater passed\n");
+- return -EINVAL;
+- }
+-
+- vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+-
+- if (!vdd->pmic_info->vsel_to_uv) {
+- pr_warning("PMIC function to convert vsel to voltage"
+- "in uV not registerd\n");
+- return -EINVAL;
+- }
+-
+- *val = vdd->pmic_info->vsel_to_uv(vsel);
+- return 0;
+-}
+-
+ static int nom_volt_debug_get(void *data, u64 *val)
+ {
+ struct voltagedomain *voltdm = (struct voltagedomain *)data;
+@@ -165,85 +137,8 @@ static int nom_volt_debug_get(void *data, u64 *val)
+ return 0;
+ }
+
+-DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
+ DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+ "%llu\n");
+-static void vp_latch_vsel(struct voltagedomain *voltdm)
+-{
+- u32 vpconfig;
+- unsigned long uvdc;
+- char vsel;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+-
+- uvdc = omap_voltage_get_nom_volt(voltdm);
+- if (!uvdc) {
+- pr_warning("%s: unable to find current voltage for vdd_%s\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+- pr_warning("%s: PMIC function to convert voltage in uV to"
+- " vsel not registered\n", __func__);
+- return;
+- }
+-
+- vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+-
+- vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
+- vdd->vp_data->vp_common->vpconfig_initvdd);
+- vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
+-
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /* Trigger initVDD value copy to voltage processor */
+- vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
+- vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /* Clear initVDD copy trigger bit */
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-}
+-
+-/* Generic voltage init functions */
+-static void __init vp_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vp_val;
+-
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+- (vdd->vp_rt_data.vpconfig_errorgain <<
+- vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
+- vdd->vp_data->vp_common->vpconfig_timeouten;
+- vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+- vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
+- (vdd->vp_rt_data.vstepmin_stepmin <<
+- vdd->vp_data->vp_common->vstepmin_stepmin_shift));
+- vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstepmin);
+-
+- vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+- vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
+- (vdd->vp_rt_data.vstepmax_stepmax <<
+- vdd->vp_data->vp_common->vstepmax_stepmax_shift));
+- vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstepmax);
+-
+- vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+- vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
+- (vdd->vp_rt_data.vlimitto_vddmin <<
+- vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
+- (vdd->vp_rt_data.vlimitto_timeout <<
+- vdd->vp_data->vp_common->vlimitto_timeout_shift));
+- vdd->write_reg(vp_val, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vlimitto);
+-}
+-
+ static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+ {
+ char *name;
+@@ -268,125 +163,11 @@ static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+ return;
+ }
+
+- (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vpconfig_errorgain));
+- (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
+- vdd->debug_dir,
+- &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
+- (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vstepmin_stepmin));
+- (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
+- vdd->debug_dir,
+- &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
+- (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vstepmax_stepmax));
+- (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vlimitto_vddmax));
+- (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vlimitto_vddmin));
+- (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_rt_data.vlimitto_timeout));
+- (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
+- (void *) voltdm, &vp_volt_debug_fops);
+ (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+ vdd->debug_dir, (void *) voltdm,
+ &nom_volt_debug_fops);
+ }
+
+-/* VP force update method of voltage scaling */
+-static int vp_forceupdate_scale_voltage(struct voltagedomain *voltdm,
+- unsigned long target_volt)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vpconfig;
+- u8 target_vsel, current_vsel;
+- int ret, timeout = 0;
+-
+- ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
+- if (ret)
+- return ret;
+-
+- /*
+- * Clear all pending TransactionDone interrupt/status. Typical latency
+- * is <3us
+- */
+- while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+- vdd->vp_data->prm_irqst_data->tranxdone_status))
+- break;
+- udelay(1);
+- }
+- if (timeout >= VP_TRANXDONE_TIMEOUT) {
+- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+- "Voltage change aborted", __func__, voltdm->name);
+- return -ETIMEDOUT;
+- }
+-
+- /* Configure for VP-Force Update */
+- vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
+- vdd->vp_data->vp_common->vpconfig_forceupdate |
+- vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
+- vpconfig |= ((target_vsel <<
+- vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /* Trigger initVDD value copy to voltage processor */
+- vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /* Force update of voltage */
+- vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /*
+- * Wait for TransactionDone. Typical latency is <200us.
+- * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+- */
+- timeout = 0;
+- omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod,
+- vdd->prm_irqst_reg) &
+- vdd->vp_data->prm_irqst_data->tranxdone_status),
+- VP_TRANXDONE_TIMEOUT, timeout);
+- if (timeout >= VP_TRANXDONE_TIMEOUT)
+- pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+- "TRANXDONE never got set after the voltage update\n",
+- __func__, voltdm->name);
+-
+- omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+-
+- /*
+- * Disable TransactionDone interrupt , clear all status, clear
+- * control registers
+- */
+- timeout = 0;
+- while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+- vdd->vp_data->prm_irqst_data->tranxdone_status))
+- break;
+- udelay(1);
+- }
+-
+- if (timeout >= VP_TRANXDONE_TIMEOUT)
+- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+- "to clear the TRANXDONE status\n",
+- __func__, voltdm->name);
+-
+- vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- /* Clear initVDD copy trigger bit */
+- vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- /* Clear force bit */
+- vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- return 0;
+-}
+-
+ static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ {
+ struct omap_vdd_info *vdd = voltdm->vdd;
+@@ -439,129 +220,6 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ }
+
+ /**
+- * omap_vp_get_curr_volt() - API to get the current vp voltage.
+- * @voltdm: pointer to the VDD.
+- *
+- * This API returns the current voltage for the specified voltage processor
+- */
+-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd;
+- u8 curr_vsel;
+-
+- if (!voltdm || IS_ERR(voltdm)) {
+- pr_warning("%s: VDD specified does not exist!\n", __func__);
+- return 0;
+- }
+-
+- vdd = voltdm->vdd;
+- if (!vdd->read_reg) {
+- pr_err("%s: No read API for reading vdd_%s regs\n",
+- __func__, voltdm->name);
+- return 0;
+- }
+-
+- curr_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
+-
+- if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+- pr_warning("%s: PMIC function to convert vsel to voltage"
+- "in uV not registerd\n", __func__);
+- return 0;
+- }
+-
+- return vdd->pmic_info->vsel_to_uv(curr_vsel);
+-}
+-
+-/**
+- * omap_vp_enable() - API to enable a particular VP
+- * @voltdm: pointer to the VDD whose VP is to be enabled.
+- *
+- * This API enables a particular voltage processor. Needed by the smartreflex
+- * class drivers.
+- */
+-void omap_vp_enable(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd;
+- u32 vpconfig;
+-
+- if (!voltdm || IS_ERR(voltdm)) {
+- pr_warning("%s: VDD specified does not exist!\n", __func__);
+- return;
+- }
+-
+- vdd = voltdm->vdd;
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- /* If VP is already enabled, do nothing. Return */
+- if (vdd->vp_enabled)
+- return;
+-
+- vp_latch_vsel(voltdm);
+-
+- /* Enable VP */
+- vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- vdd->vp_enabled = true;
+-}
+-
+-/**
+- * omap_vp_disable() - API to disable a particular VP
+- * @voltdm: pointer to the VDD whose VP is to be disabled.
+- *
+- * This API disables a particular voltage processor. Needed by the smartreflex
+- * class drivers.
+- */
+-void omap_vp_disable(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd;
+- u32 vpconfig;
+- int timeout;
+-
+- if (!voltdm || IS_ERR(voltdm)) {
+- pr_warning("%s: VDD specified does not exist!\n", __func__);
+- return;
+- }
+-
+- vdd = voltdm->vdd;
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- /* If VP is already disabled, do nothing. Return */
+- if (!vdd->vp_enabled) {
+- pr_warning("%s: Trying to disable VP for vdd_%s when"
+- "it is already disabled\n", __func__, voltdm->name);
+- return;
+- }
+-
+- /* Disable VP */
+- vpconfig = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+- vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vpconfig);
+-
+- /*
+- * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+- */
+- omap_test_timeout((vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->vstatus)),
+- VP_IDLE_TIMEOUT, timeout);
+-
+- if (timeout >= VP_IDLE_TIMEOUT)
+- pr_warning("%s: vdd_%s idle timedout\n",
+- __func__, voltdm->name);
+-
+- vdd->vp_enabled = false;
+-
+- return;
+-}
+-
+-/**
+ * omap_voltage_scale_vdd() - API to scale voltage of a particular
+ * voltage domain.
+ * @voltdm: pointer to the VDD which is to be scaled.
+@@ -766,7 +424,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+
+ switch (voltscale_method) {
+ case VOLTSCALE_VPFORCEUPDATE:
+- vdd->volt_scale = vp_forceupdate_scale_voltage;
++ vdd->volt_scale = omap_vp_forceupdate_scale;
+ return;
+ case VOLTSCALE_VCBYPASS:
+ vdd->volt_scale = omap_vc_bypass_scale;
+@@ -810,8 +468,8 @@ int __init omap_voltage_late_init(void)
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+ continue;
+- vp_init(voltdm);
+ vdd_debugfs_init(voltdm);
++ omap_vp_init(voltdm);
+ }
+ }
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index b06e03f..83fa239 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -152,9 +152,6 @@ struct omap_vdd_info {
+ unsigned long target_volt);
+ };
+
+-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+-void omap_vp_enable(struct voltagedomain *voltdm);
+-void omap_vp_disable(struct voltagedomain *voltdm);
+ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+ unsigned long target_volt);
+ void omap_voltage_reset(struct voltagedomain *voltdm);
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+new file mode 100644
+index 0000000..f3503de
+--- /dev/null
++++ b/arch/arm/mach-omap2/vp.c
+@@ -0,0 +1,374 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/debugfs.h>
++
++#include <plat/common.h>
++
++#include "voltage.h"
++#include "vp.h"
++#include "prm-regbits-34xx.h"
++#include "prm-regbits-44xx.h"
++#include "prm44xx.h"
++
++static void __init vp_debugfs_init(struct voltagedomain *voltdm);
++
++static void vp_latch_vsel(struct voltagedomain *voltdm)
++{
++ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ u32 vpconfig;
++ unsigned long uvdc;
++ char vsel;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++
++ uvdc = omap_voltage_get_nom_volt(voltdm);
++ if (!uvdc) {
++ pr_warning("%s: unable to find current voltage for vdd_%s\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
++ pr_warning("%s: PMIC function to convert voltage in uV to"
++ " vsel not registered\n", __func__);
++ return;
++ }
++
++ vsel = vdd->pmic_info->uv_to_vsel(uvdc);
++
++ vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig &= ~(vp->vp_common->vpconfig_initvoltage_mask |
++ vp->vp_common->vpconfig_initvdd);
++ vpconfig |= vsel << vp->vp_common->vpconfig_initvoltage_shift;
++
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ /* Trigger initVDD value copy to voltage processor */
++ vdd->write_reg((vpconfig | vp->vp_common->vpconfig_initvdd),
++ vp->vp_common->prm_mod, vp->vpconfig);
++
++ /* Clear initVDD copy trigger bit */
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++}
++
++/* Generic voltage init functions */
++void __init omap_vp_init(struct voltagedomain *voltdm)
++{
++ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 vp_val;
++
++ if (!vdd->read_reg || !vdd->write_reg) {
++ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
++ (vdd->vp_rt_data.vpconfig_errorgain <<
++ vp->vp_common->vpconfig_errorgain_shift) |
++ vp->vp_common->vpconfig_timeouten;
++ vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vpconfig);
++
++ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
++ vp->vp_common->vstepmin_smpswaittimemin_shift) |
++ (vdd->vp_rt_data.vstepmin_stepmin <<
++ vp->vp_common->vstepmin_stepmin_shift));
++ vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vstepmin);
++
++ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
++ vp->vp_common->vstepmax_smpswaittimemax_shift) |
++ (vdd->vp_rt_data.vstepmax_stepmax <<
++ vp->vp_common->vstepmax_stepmax_shift));
++ vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vstepmax);
++
++ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
++ vp->vp_common->vlimitto_vddmax_shift) |
++ (vdd->vp_rt_data.vlimitto_vddmin <<
++ vp->vp_common->vlimitto_vddmin_shift) |
++ (vdd->vp_rt_data.vlimitto_timeout <<
++ vp->vp_common->vlimitto_timeout_shift));
++ vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vlimitto);
++
++ vp_debugfs_init(voltdm);
++}
++
++/* VP force update method of voltage scaling */
++int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt)
++{
++ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 vpconfig;
++ u8 target_vsel, current_vsel;
++ int ret, timeout = 0;
++
++ ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
++ if (ret)
++ return ret;
++
++ /*
++ * Clear all pending TransactionDone interrupt/status. Typical latency
++ * is <3us
++ */
++ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
++ vdd->write_reg(vp->prm_irqst_data->tranxdone_status,
++ vdd->prm_irqst_mod, vdd->prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
++ vp->prm_irqst_data->tranxdone_status))
++ break;
++ udelay(1);
++ }
++ if (timeout >= VP_TRANXDONE_TIMEOUT) {
++ pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
++ "Voltage change aborted", __func__, voltdm->name);
++ return -ETIMEDOUT;
++ }
++
++ /* Configure for VP-Force Update */
++ vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig &= ~(vp->vp_common->vpconfig_initvdd |
++ vp->vp_common->vpconfig_forceupdate |
++ vp->vp_common->vpconfig_initvoltage_mask);
++ vpconfig |= ((target_vsel <<
++ vp->vp_common->vpconfig_initvoltage_shift));
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ /* Trigger initVDD value copy to voltage processor */
++ vpconfig |= vp->vp_common->vpconfig_initvdd;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ /* Force update of voltage */
++ vpconfig |= vp->vp_common->vpconfig_forceupdate;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ /*
++ * Wait for TransactionDone. Typical latency is <200us.
++ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
++ */
++ timeout = 0;
++ omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod,
++ vdd->prm_irqst_reg) &
++ vp->prm_irqst_data->tranxdone_status),
++ VP_TRANXDONE_TIMEOUT, timeout);
++ if (timeout >= VP_TRANXDONE_TIMEOUT)
++ pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
++ "TRANXDONE never got set after the voltage update\n",
++ __func__, voltdm->name);
++
++ omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
++
++ /*
++ * Disable TransactionDone interrupt , clear all status, clear
++ * control registers
++ */
++ timeout = 0;
++ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
++ vdd->write_reg(vp->prm_irqst_data->tranxdone_status,
++ vdd->prm_irqst_mod, vdd->prm_irqst_reg);
++ if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
++ vp->prm_irqst_data->tranxdone_status))
++ break;
++ udelay(1);
++ }
++
++ if (timeout >= VP_TRANXDONE_TIMEOUT)
++ pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
++ "to clear the TRANXDONE status\n",
++ __func__, voltdm->name);
++
++ vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ /* Clear initVDD copy trigger bit */
++ vpconfig &= ~vp->vp_common->vpconfig_initvdd;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ /* Clear force bit */
++ vpconfig &= ~vp->vp_common->vpconfig_forceupdate;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ return 0;
++}
++
++/**
++ * omap_vp_get_curr_volt() - API to get the current vp voltage.
++ * @voltdm: pointer to the VDD.
++ *
++ * This API returns the current voltage for the specified voltage processor
++ */
++unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
++{
++ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vdd_info *vdd;
++ u8 curr_vsel;
++
++ if (!voltdm || IS_ERR(voltdm)) {
++ pr_warning("%s: VDD specified does not exist!\n", __func__);
++ return 0;
++ }
++
++ vdd = voltdm->vdd;
++ if (!vdd->read_reg) {
++ pr_err("%s: No read API for reading vdd_%s regs\n",
++ __func__, voltdm->name);
++ return 0;
++ }
++
++ curr_vsel = vdd->read_reg(vp->vp_common->prm_mod, vp->voltage);
++
++ if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
++ pr_warning("%s: PMIC function to convert vsel to voltage"
++ "in uV not registerd\n", __func__);
++ return 0;
++ }
++
++ return vdd->pmic_info->vsel_to_uv(curr_vsel);
++}
++
++/**
++ * omap_vp_enable() - API to enable a particular VP
++ * @voltdm: pointer to the VDD whose VP is to be enabled.
++ *
++ * This API enables a particular voltage processor. Needed by the smartreflex
++ * class drivers.
++ */
++void omap_vp_enable(struct voltagedomain *voltdm)
++{
++ struct omap_vp_instance_data *vp;
++ struct omap_vdd_info *vdd;
++ u32 vpconfig;
++
++ if (!voltdm || IS_ERR(voltdm)) {
++ pr_warning("%s: VDD specified does not exist!\n", __func__);
++ return;
++ }
++
++ vdd = voltdm->vdd;
++ vp = voltdm->vdd->vp_data;
++ if (!vdd->read_reg || !vdd->write_reg) {
++ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ /* If VP is already enabled, do nothing. Return */
++ if (vdd->vp_enabled)
++ return;
++
++ vp_latch_vsel(voltdm);
++
++ /* Enable VP */
++ vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig |= vp->vp_common->vpconfig_vpenable;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ vdd->vp_enabled = true;
++}
++
++/**
++ * omap_vp_disable() - API to disable a particular VP
++ * @voltdm: pointer to the VDD whose VP is to be disabled.
++ *
++ * This API disables a particular voltage processor. Needed by the smartreflex
++ * class drivers.
++ */
++void omap_vp_disable(struct voltagedomain *voltdm)
++{
++ struct omap_vp_instance_data *vp;
++ struct omap_vdd_info *vdd;
++ u32 vpconfig;
++ int timeout;
++
++ if (!voltdm || IS_ERR(voltdm)) {
++ pr_warning("%s: VDD specified does not exist!\n", __func__);
++ return;
++ }
++
++ vdd = voltdm->vdd;
++ vp = voltdm->vdd->vp_data;
++ if (!vdd->read_reg || !vdd->write_reg) {
++ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ /* If VP is already disabled, do nothing. Return */
++ if (!vdd->vp_enabled) {
++ pr_warning("%s: Trying to disable VP for vdd_%s when"
++ "it is already disabled\n", __func__, voltdm->name);
++ return;
++ }
++
++ /* Disable VP */
++ vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig &= ~vp->vp_common->vpconfig_vpenable;
++ vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++
++ /*
++ * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
++ */
++ omap_test_timeout((vdd->read_reg(vp->vp_common->prm_mod, vp->vstatus)),
++ VP_IDLE_TIMEOUT, timeout);
++
++ if (timeout >= VP_IDLE_TIMEOUT)
++ pr_warning("%s: vdd_%s idle timedout\n",
++ __func__, voltdm->name);
++
++ vdd->vp_enabled = false;
++
++ return;
++}
++
++/* Voltage debugfs support */
++static int vp_volt_debug_get(void *data, u64 *val)
++{
++ struct voltagedomain *voltdm = (struct voltagedomain *)data;
++ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ u8 vsel;
++
++ if (!vdd) {
++ pr_warning("Wrong paramater passed\n");
++ return -EINVAL;
++ }
++
++ vsel = vdd->read_reg(vp->vp_common->prm_mod, vp->voltage);
++
++ if (!vdd->pmic_info->vsel_to_uv) {
++ pr_warning("PMIC function to convert vsel to voltage"
++ "in uV not registerd\n");
++ return -EINVAL;
++ }
++
++ *val = vdd->pmic_info->vsel_to_uv(vsel);
++ return 0;
++}
++
++DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
++
++static void __init vp_debugfs_init(struct voltagedomain *voltdm)
++{
++ struct omap_vdd_info *vdd = voltdm->vdd;
++ struct dentry *debug_dir;
++
++ debug_dir = debugfs_create_dir("vp", vdd->debug_dir);
++ if (IS_ERR(debug_dir))
++ pr_err("%s: Unable to create VP debugfs dir dir\n", __func__);
++
++ (void) debugfs_create_x16("errorgain", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vpconfig_errorgain));
++ (void) debugfs_create_x16("smpswaittimemin", S_IRUGO,
++ debug_dir,
++ &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
++ (void) debugfs_create_x8("stepmin", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vstepmin_stepmin));
++ (void) debugfs_create_x16("smpswaittimemax", S_IRUGO,
++ debug_dir,
++ &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
++ (void) debugfs_create_x8("stepmax", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vstepmax_stepmax));
++ (void) debugfs_create_x8("vddmax", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vlimitto_vddmax));
++ (void) debugfs_create_x8("vddmin", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vlimitto_vddmin));
++ (void) debugfs_create_x16("timeout", S_IRUGO, debug_dir,
++ &(vdd->vp_rt_data.vlimitto_timeout));
++ (void) debugfs_create_file("curr_volt", S_IRUGO, debug_dir,
++ (void *) voltdm, &vp_volt_debug_fops);
++}
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 5406b08..025cf16 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -19,6 +19,8 @@
+
+ #include <linux/kernel.h>
+
++struct voltagedomain;
++
+ /* XXX document */
+ #define VP_IDLE_TIMEOUT 200
+ #define VP_TRANXDONE_TIMEOUT 300
+@@ -139,4 +141,11 @@ extern struct omap_vp_instance_data omap4_vp_mpu_data;
+ extern struct omap_vp_instance_data omap4_vp_iva_data;
+ extern struct omap_vp_instance_data omap4_vp_core_data;
+
++void omap_vp_init(struct voltagedomain *voltdm);
++void omap_vp_enable(struct voltagedomain *voltdm);
++void omap_vp_disable(struct voltagedomain *voltdm);
++unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
++int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt);
++
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0113-OMAP2-VC-support-PMICs-with-separate-voltage-and-com.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0113-OMAP2-VC-support-PMICs-with-separate-voltage-and-com.patch
--- /dev/null
@@ -0,0 +1,109 @@
+From 5b8106df22b9fab4597d531500ce4bef75e14682 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 22 Mar 2011 14:12:37 -0700
+Subject: [PATCH 113/149] OMAP2+: VC: support PMICs with separate voltage and command registers
+
+The VC layer can support PMICs with separate voltage and command
+registers by putting the different registers in the PRM_VC_SMPS_VOL_RA
+and PRCM_VC_SMPS_CMD_RA registers respectively.
+
+The PMIC data must supply at least a voltage register address
+(volt_reg_addr). The command register address (cmd_reg_addr) is
+optional. If the PMIC data does not supply a separate command
+register address, the VC will use the voltage register address for both.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 10 +++++-----
+ arch/arm/mach-omap2/vc.c | 4 ++--
+ arch/arm/mach-omap2/voltage.h | 3 ++-
+ 3 files changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 760487b..3249fe3 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -158,7 +158,7 @@ static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+ .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+- .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG,
++ .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+@@ -178,7 +178,7 @@ static struct omap_volt_pmic_info omap3_core_volt_info = {
+ .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+- .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG,
++ .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+@@ -198,7 +198,7 @@ static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+ .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+- .pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG,
++ .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+@@ -218,7 +218,7 @@ static struct omap_volt_pmic_info omap4_iva_volt_info = {
+ .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+- .pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG,
++ .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+@@ -238,7 +238,7 @@ static struct omap_volt_pmic_info omap4_core_volt_info = {
+ .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+- .pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG,
++ .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 7643940..720c0cd 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -106,7 +106,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ vc_valid = vc->common->valid;
+ vc_bypass_val_reg = vc->common->bypass_val_reg;
+ vc_bypass_value = (target_vsel << vc->common->data_shift) |
+- (vdd->pmic_info->pmic_reg <<
++ (vdd->pmic_info->volt_reg_addr <<
+ vc->common->regaddr_shift) |
+ (vdd->pmic_info->i2c_slave_addr <<
+ vc->common->slaveaddr_shift);
+@@ -255,7 +255,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc_val = vdd->read_reg(vc->common->prm_mod,
+ vc->common->smps_volra_reg);
+ vc_val &= ~vc->smps_volra_mask;
+- vc_val |= vdd->pmic_info->pmic_reg << vc->smps_volra_shift;
++ vc_val |= vdd->pmic_info->volt_reg_addr << vc->smps_volra_shift;
+ vdd->write_reg(vc_val, vc->common->prm_mod,
+ vc->common->smps_volra_reg);
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 83fa239..641597c 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -112,7 +112,8 @@ struct omap_volt_pmic_info {
+ u8 vp_vddmax;
+ u8 vp_timeout_us;
+ u8 i2c_slave_addr;
+- u8 pmic_reg;
++ u8 volt_reg_addr;
++ u8 cmd_reg_addr;
+ unsigned long (*vsel_to_uv) (const u8 vsel);
+ u8 (*uv_to_vsel) (unsigned long uV);
+ };
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0114-OMAP2-add-PRM-VP-functions-for-checking-clearing-VP-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0114-OMAP2-add-PRM-VP-functions-for-checking-clearing-VP-.patch
--- /dev/null
@@ -0,0 +1,375 @@
+From c5e08ab208309b2897d8749def97850a821dae68 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 28 Mar 2011 10:52:04 -0700
+Subject: [PATCH 114/149] OMAP2+: add PRM VP functions for checking/clearing VP TX done status
+
+Add SoC specific PRM VP helper functions for checking and clearing
+the VP transaction done status.
+
+Longer term, these events should be handled by the forthcoming PRCM
+interrupt handler.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/prm2xxx_3xxx.c | 41 ++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 +++
+ arch/arm/mach-omap2/prm44xx.c | 49 ++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/prm44xx.h | 4 +++
+ arch/arm/mach-omap2/vp.h | 33 ++++++++++++++---------
+ arch/arm/mach-omap2/vp3xxx_data.c | 19 ++++++-------
+ arch/arm/mach-omap2/vp44xx_data.c | 25 ++++++-----------
+ 7 files changed, 136 insertions(+), 39 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+index 051213f..58c5c87 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+@@ -20,6 +20,8 @@
+ #include <plat/cpu.h>
+ #include <plat/prcm.h>
+
++#include "vp.h"
++
+ #include "prm2xxx_3xxx.h"
+ #include "cm2xxx_3xxx.h"
+ #include "prm-regbits-24xx.h"
+@@ -156,3 +158,42 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+
+ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+ }
++
++/* PRM VP */
++
++/*
++ * struct omap3_vp - OMAP3 VP register access description.
++ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ */
++struct omap3_vp {
++ u32 tranxdone_status;
++};
++
++struct omap3_vp omap3_vp[] = {
++ [OMAP3_VP_VDD_MPU_ID] = {
++ .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
++ },
++ [OMAP3_VP_VDD_CORE_ID] = {
++ .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
++ },
++};
++
++#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
++
++u32 omap3_prm_vp_check_txdone(u8 vp_id)
++{
++ struct omap3_vp *vp = &omap3_vp[vp_id];
++ u32 irqstatus;
++
++ irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
++ OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
++ return irqstatus & vp->tranxdone_status;
++}
++
++void omap3_prm_vp_clear_txdone(u8 vp_id)
++{
++ struct omap3_vp *vp = &omap3_vp[vp_id];
++
++ omap2_prm_write_mod_reg(vp->tranxdone_status,
++ OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
++}
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index a1fc62a..5112526 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -303,6 +303,10 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+ extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+
++/* OMAP3-specific VP functions */
++u32 omap3_prm_vp_check_txdone(u8 vp_id);
++void omap3_prm_vp_clear_txdone(u8 vp_id);
++
+ #endif /* CONFIG_ARCH_OMAP4 */
+ #endif
+
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index 0016555..390e32c 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -21,6 +21,7 @@
+ #include <plat/cpu.h>
+ #include <plat/prcm.h>
+
++#include "vp.h"
+ #include "prm44xx.h"
+ #include "prm-regbits-44xx.h"
+
+@@ -50,3 +51,51 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+
+ return v;
+ }
++
++/* PRM VP */
++
++/*
++ * struct omap4_vp - OMAP4 VP register access description.
++ * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
++ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ */
++struct omap4_vp {
++ u32 irqstatus_mpu;
++ u32 tranxdone_status;
++};
++
++static struct omap4_vp omap4_vp[] = {
++ [OMAP4_VP_VDD_MPU_ID] = {
++ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
++ .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
++ },
++ [OMAP4_VP_VDD_IVA_ID] = {
++ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
++ },
++ [OMAP4_VP_VDD_CORE_ID] = {
++ .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
++ },
++};
++
++u32 omap4_prm_vp_check_txdone(u8 vp_id)
++{
++ struct omap4_vp *vp = &omap4_vp[vp_id];
++ u32 irqstatus;
++
++ irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_OCP_SOCKET_INST,
++ vp->irqstatus_mpu);
++ return irqstatus & vp->tranxdone_status;
++}
++
++void omap4_prm_vp_clear_txdone(u8 vp_id)
++{
++ struct omap4_vp *vp = &omap4_vp[vp_id];
++
++ omap4_prminst_write_inst_reg(vp->tranxdone_status,
++ OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_OCP_SOCKET_INST,
++ vp->irqstatus_mpu);
++};
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index 7dfa379..b28c87d 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -751,6 +751,10 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+ extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
++/* OMAP4-specific VP functions */
++u32 omap4_prm_vp_check_txdone(u8 vp_id);
++void omap4_prm_vp_clear_txdone(u8 vp_id);
++
+ # endif
+
+ #endif
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 025cf16..2c9cd76 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -21,10 +21,28 @@
+
+ struct voltagedomain;
+
++/*
++ * Voltage Processor (VP) identifiers
++ */
++#define OMAP3_VP_VDD_MPU_ID 0
++#define OMAP3_VP_VDD_CORE_ID 1
++#define OMAP4_VP_VDD_CORE_ID 0
++#define OMAP4_VP_VDD_IVA_ID 1
++#define OMAP4_VP_VDD_MPU_ID 2
++
+ /* XXX document */
+ #define VP_IDLE_TIMEOUT 200
+ #define VP_TRANXDONE_TIMEOUT 300
+
++/**
++ * struct omap_vp_ops - per-VP operations
++ * @check_txdone: check for VP transaction done
++ * @clear_txdone: clear VP transaction done status
++ */
++struct omap_vp_ops {
++ u32 (*check_txdone)(u8 vp_id);
++ void (*clear_txdone)(u8 vp_id);
++};
+
+ /**
+ * struct omap_vp_common_data - register data common to all VDDs
+@@ -68,24 +86,13 @@ struct omap_vp_common_data {
+ u8 vlimitto_vddmin_shift;
+ u8 vlimitto_vddmax_shift;
+ u8 vlimitto_timeout_shift;
+-};
+
+-/**
+- * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
+- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+- *
+- * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
+- * hardware bug
+- * XXX This structure is probably not needed
+- */
+-struct omap_vp_prm_irqst_data {
+- u32 tranxdone_status;
++ const struct omap_vp_ops *ops;
+ };
+
+ /**
+ * struct omap_vp_instance_data - VP register offsets (per-VDD)
+ * @vp_common: pointer to struct omap_vp_common_data * for this SoC
+- * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD
+ * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
+ * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
+ * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
+@@ -96,13 +103,13 @@ struct omap_vp_prm_irqst_data {
+ */
+ struct omap_vp_instance_data {
+ const struct omap_vp_common_data *vp_common;
+- const struct omap_vp_prm_irqst_data *prm_irqst_data;
+ u8 vpconfig;
+ u8 vstepmin;
+ u8 vstepmax;
+ u8 vlimitto;
+ u8 vstatus;
+ u8 voltage;
++ u8 id;
+ };
+
+ /**
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index a8ea045..0372c1a 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -25,6 +25,12 @@
+ #include "voltage.h"
+
+ #include "vp.h"
++#include "prm2xxx_3xxx.h"
++
++static const struct omap_vp_ops omap3_vp_ops = {
++ .check_txdone = omap3_prm_vp_check_txdone,
++ .clear_txdone = omap3_prm_vp_clear_txdone,
++};
+
+ /*
+ * VP data common to 34xx/36xx chips
+@@ -48,13 +54,11 @@ static const struct omap_vp_common_data omap3_vp_common = {
+ .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
+ .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
+ .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
+-};
+-
+-static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
+- .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
++ .ops = &omap3_vp_ops,
+ };
+
+ struct omap_vp_instance_data omap3_vp1_data = {
++ .id = OMAP3_VP_VDD_MPU_ID,
+ .vp_common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+@@ -62,14 +66,10 @@ struct omap_vp_instance_data omap3_vp1_data = {
+ .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
+ .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
+ .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+- .prm_irqst_data = &omap3_vp1_prm_irqst_data,
+-};
+-
+-static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
+- .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+ };
+
+ struct omap_vp_instance_data omap3_vp2_data = {
++ .id = OMAP3_VP_VDD_CORE_ID,
+ .vp_common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+@@ -77,5 +77,4 @@ struct omap_vp_instance_data omap3_vp2_data = {
+ .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
+ .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
+ .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
+- .prm_irqst_data = &omap3_vp2_prm_irqst_data,
+ };
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 0957c24..738ba04 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -27,6 +27,11 @@
+
+ #include "vp.h"
+
++static const struct omap_vp_ops omap4_vp_ops = {
++ .check_txdone = omap4_prm_vp_check_txdone,
++ .clear_txdone = omap4_prm_vp_clear_txdone,
++};
++
+ /*
+ * VP data common to 44xx chips
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+@@ -49,13 +54,11 @@ static const struct omap_vp_common_data omap4_vp_common = {
+ .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
+ .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
+ .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
+-};
+-
+-static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
+- .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
++ .ops = &omap4_vp_ops,
+ };
+
+ struct omap_vp_instance_data omap4_vp_mpu_data = {
++ .id = OMAP4_VP_VDD_MPU_ID,
+ .vp_common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+@@ -63,14 +66,10 @@ struct omap_vp_instance_data omap4_vp_mpu_data = {
+ .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+ .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+ .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+- .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data,
+-};
+-
+-static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
+- .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+ };
+
+ struct omap_vp_instance_data omap4_vp_iva_data = {
++ .id = OMAP4_VP_VDD_IVA_ID,
+ .vp_common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+@@ -78,14 +77,10 @@ struct omap_vp_instance_data omap4_vp_iva_data = {
+ .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+ .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+ .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+- .prm_irqst_data = &omap4_vp_iva_prm_irqst_data,
+-};
+-
+-static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
+- .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+ };
+
+ struct omap_vp_instance_data omap4_vp_core_data = {
++ .id = OMAP4_VP_VDD_CORE_ID,
+ .vp_common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+@@ -93,6 +88,4 @@ struct omap_vp_instance_data omap4_vp_core_data = {
+ .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+ .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+ .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+- .prm_irqst_data = &omap4_vp_core_prm_irqst_data,
+ };
+-
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0115-OMAP3-VP-replace-transaction-done-check-clear-with-V.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0115-OMAP3-VP-replace-transaction-done-check-clear-with-V.patch
--- /dev/null
@@ -0,0 +1,142 @@
+From 52124f6d5f00b6a42e0c66a7650b7ed1f88bb9b3 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 28 Mar 2011 11:57:18 -0700
+Subject: [PATCH 115/149] OMAP3+ VP: replace transaction done check/clear with VP ops
+
+Replace the VP tranxdone check/clear with helper functions from the
+PRM layer.
+
+In the process, remove prm_irqst_* voltage structure fields for IRQ
+status checking which are no longer needed.
+
+Since these reads/writes of the IRQ status bits were the only PRM
+accesses that were not to VC/VP registers, this allows the rest of the
+register accesses in the VC/VP code to use VC/VP specific register
+access functions (done in the following patch.)
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.h | 3 ---
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 4 ----
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 6 ------
+ arch/arm/mach-omap2/vp.c | 16 +++++-----------
+ 4 files changed, 5 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 641597c..363eee4 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -131,7 +131,6 @@ struct omap_volt_pmic_info {
+ * @vfsm : voltage manager FSM data
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+- * @prm_irqst_mod : PRM module id used for PRM IRQ status register access
+ * @vp_enabled : flag to keep track of whether vp is enabled or not
+ * @volt_scale : API to scale the voltage of the vdd.
+ */
+@@ -145,8 +144,6 @@ struct omap_vdd_info {
+ u32 curr_volt;
+ bool vp_enabled;
+
+- s16 prm_irqst_mod;
+- u8 prm_irqst_reg;
+ u32 (*read_reg) (u16 mod, u8 offset);
+ void (*write_reg) (u32 val, u16 mod, u8 offset);
+ int (*volt_scale) (struct voltagedomain *voltdm,
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 7cb27ec..ad8f05b 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -38,8 +38,6 @@ static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap3_vdd1_info = {
+- .prm_irqst_mod = OCP_MOD,
+- .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp1_data,
+ .vfsm = &omap3_vdd1_vfsm_data,
+ };
+@@ -51,8 +49,6 @@ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap3_vdd2_info = {
+- .prm_irqst_mod = OCP_MOD,
+- .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap3_vp2_data,
+ .vfsm = &omap3_vdd2_vfsm_data,
+ };
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index a05d90a..43e1d38 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -37,8 +37,6 @@ static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_mpu_info = {
+- .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+ .vp_data = &omap4_vp_mpu_data,
+ .vfsm = &omap4_vdd_mpu_vfsm_data,
+ };
+@@ -48,8 +46,6 @@ static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_iva_info = {
+- .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_iva_data,
+ .vfsm = &omap4_vdd_iva_vfsm_data,
+ };
+@@ -59,8 +55,6 @@ static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
+ };
+
+ static struct omap_vdd_info omap4_vdd_core_info = {
+- .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+- .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+ .vp_data = &omap4_vp_core_data,
+ .vfsm = &omap4_vdd_core_vfsm_data,
+ };
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index f3503de..113c839 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -111,10 +111,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ * is <3us
+ */
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vp->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+- vp->prm_irqst_data->tranxdone_status))
++ vp->vp_common->ops->clear_txdone(vp->id);
++ if (!vp->vp_common->ops->check_txdone(vp->id))
+ break;
+ udelay(1);
+ }
+@@ -146,9 +144,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ */
+ timeout = 0;
+- omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod,
+- vdd->prm_irqst_reg) &
+- vp->prm_irqst_data->tranxdone_status),
++ omap_test_timeout(vp->vp_common->ops->check_txdone(vp->id),
+ VP_TRANXDONE_TIMEOUT, timeout);
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+@@ -163,10 +159,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ */
+ timeout = 0;
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vp->prm_irqst_data->tranxdone_status,
+- vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+- if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
+- vp->prm_irqst_data->tranxdone_status))
++ vp->vp_common->ops->clear_txdone(vp->id);
++ if (!vp->vp_common->ops->check_txdone(vp->id))
+ break;
+ udelay(1);
+ }
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0116-OMAP2-PRM-add-register-access-functions-for-VC-VP.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0116-OMAP2-PRM-add-register-access-functions-for-VC-VP.patch
--- /dev/null
@@ -0,0 +1,119 @@
+From 3cd0e8de034769e7ffff9cd262d9881c7b154c12 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 28 Mar 2011 10:25:12 -0700
+Subject: [PATCH 116/149] OMAP2+: PRM: add register access functions for VC/VP
+
+On OMAP3+, the voltage controller (VC) and voltage processor (VP) are
+inside the PRM. Add some PRM helper functions for register access to
+these module registers.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/prm2xxx_3xxx.c | 15 +++++++++++++++
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 8 ++++++++
+ arch/arm/mach-omap2/prm44xx.c | 22 ++++++++++++++++++++++
+ arch/arm/mach-omap2/prm44xx.h | 8 ++++++++
+ 4 files changed, 53 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+index 58c5c87..3b83763 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+@@ -197,3 +197,18 @@ void omap3_prm_vp_clear_txdone(u8 vp_id)
+ omap2_prm_write_mod_reg(vp->tranxdone_status,
+ OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ }
++
++u32 omap3_prm_vcvp_read(u8 offset)
++{
++ return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
++}
++
++void omap3_prm_vcvp_write(u32 val, u8 offset)
++{
++ omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
++}
++
++u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
++{
++ return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
++}
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index 5112526..cef533d 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -307,7 +307,15 @@ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+ u32 omap3_prm_vp_check_txdone(u8 vp_id);
+ void omap3_prm_vp_clear_txdone(u8 vp_id);
+
++/*
++ * OMAP3 access functions for voltage controller (VC) and
++ * voltage proccessor (VP) in the PRM.
++ */
++extern u32 omap3_prm_vcvp_read(u8 offset);
++extern void omap3_prm_vcvp_write(u32 val, u8 offset);
++extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+ #endif /* CONFIG_ARCH_OMAP4 */
++
+ #endif
+
+ /*
+diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
+index 390e32c..495a31a 100644
+--- a/arch/arm/mach-omap2/prm44xx.c
++++ b/arch/arm/mach-omap2/prm44xx.c
+@@ -24,6 +24,8 @@
+ #include "vp.h"
+ #include "prm44xx.h"
+ #include "prm-regbits-44xx.h"
++#include "prcm44xx.h"
++#include "prminst44xx.h"
+
+ /* PRM low-level functions */
+
+@@ -99,3 +101,23 @@ void omap4_prm_vp_clear_txdone(u8 vp_id)
+ OMAP4430_PRM_OCP_SOCKET_INST,
+ vp->irqstatus_mpu);
+ };
++
++u32 omap4_prm_vcvp_read(u8 offset)
++{
++ return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST, offset);
++}
++
++void omap4_prm_vcvp_write(u32 val, u8 offset)
++{
++ omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST, offset);
++}
++
++u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
++{
++ return omap4_prminst_rmw_inst_reg_bits(mask, bits,
++ OMAP4430_PRM_PARTITION,
++ OMAP4430_PRM_DEVICE_INST,
++ offset);
++}
+diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
+index b28c87d..3d66ccd 100644
+--- a/arch/arm/mach-omap2/prm44xx.h
++++ b/arch/arm/mach-omap2/prm44xx.h
+@@ -755,6 +755,14 @@ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+ u32 omap4_prm_vp_check_txdone(u8 vp_id);
+ void omap4_prm_vp_clear_txdone(u8 vp_id);
+
++/*
++ * OMAP4 access functions for voltage controller (VC) and
++ * voltage proccessor (VP) in the PRM.
++ */
++extern u32 omap4_prm_vcvp_read(u8 offset);
++extern void omap4_prm_vcvp_write(u32 val, u8 offset);
++extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
++
+ # endif
+
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0117-OMAP3-voltage-convert-to-PRM-register-access-functio.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0117-OMAP3-voltage-convert-to-PRM-register-access-functio.patch
--- /dev/null
@@ -0,0 +1,627 @@
+From 5e902c551f87c28b3847dbefbab2a2ff05630656 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 28 Mar 2011 10:40:15 -0700
+Subject: [PATCH 117/149] OMAP3+: voltage: convert to PRM register access functions
+
+Convert VC/VP register access to use PRM VC/VP accessor functions. In
+the process, move the read/write function pointers from vdd_info into
+struct voltagedomain.
+
+No functional changes.
+
+Additional cleanup:
+- remove prm_mod field from VC/VP data structures, the PRM register
+ access functions know which PRM module to use.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 69 ++++++++++---------------
+ arch/arm/mach-omap2/vc.h | 2 -
+ arch/arm/mach-omap2/vc3xxx_data.c | 1 -
+ arch/arm/mach-omap2/vc44xx_data.c | 1 -
+ arch/arm/mach-omap2/voltage.c | 31 +-----------
+ arch/arm/mach-omap2/voltage.h | 7 ++-
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 6 ++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 9 +++
+ arch/arm/mach-omap2/vp.c | 57 ++++++++++----------
+ arch/arm/mach-omap2/vp.h | 2 -
+ arch/arm/mach-omap2/vp3xxx_data.c | 1 -
+ arch/arm/mach-omap2/vp44xx_data.c | 1 -
+ 12 files changed, 76 insertions(+), 111 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 720c0cd..9c2706c 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -37,7 +37,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ return -ENODATA;
+ }
+
+- if (!vdd->read_reg || !vdd->write_reg) {
++ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+ return -EINVAL;
+@@ -49,24 +49,22 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ volt_data = NULL;
+
+ *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+- *current_vsel = vdd->read_reg(vdd->vp_data->vp_common->prm_mod, vdd->vp_data->voltage);
++ *current_vsel = voltdm->read(vdd->vp_data->voltage);
+
+ /* Setting the ON voltage to the new target voltage */
+- vc_cmdval = vdd->read_reg(vc->common->prm_mod, vc->cmdval_reg);
++ vc_cmdval = voltdm->read(vc->cmdval_reg);
+ vc_cmdval &= ~vc->common->cmd_on_mask;
+ vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
+- vdd->write_reg(vc_cmdval, vc->common->prm_mod, vc->cmdval_reg);
++ voltdm->write(vc_cmdval, vc->cmdval_reg);
+
+ /* Setting vp errorgain based on the voltage */
+ if (volt_data) {
+- vp_errgain_val = vdd->read_reg(vdd->vp_data->vp_common->prm_mod,
+- vdd->vp_data->vpconfig);
++ vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
+ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+ vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
+ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+ vp_common->vpconfig_errorgain_shift;
+- vdd->write_reg(vp_errgain_val, vdd->vp_data->vp_common->prm_mod,
+- vdd->vp_data->vpconfig);
++ voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
+ }
+
+ return 0;
+@@ -111,11 +109,10 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ (vdd->pmic_info->i2c_slave_addr <<
+ vc->common->slaveaddr_shift);
+
+- vdd->write_reg(vc_bypass_value, vc->common->prm_mod, vc_bypass_val_reg);
+- vdd->write_reg(vc_bypass_value | vc_valid, vc->common->prm_mod,
+- vc_bypass_val_reg);
++ voltdm->write(vc_bypass_value, vc_bypass_val_reg);
++ voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
+
+- vc_bypass_value = vdd->read_reg(vc->common->prm_mod, vc_bypass_val_reg);
++ vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+ /*
+ * Loop till the bypass command is acknowledged from the SMPS.
+ * NOTE: This is legacy code. The loop count and retry count needs
+@@ -134,8 +131,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ loop_cnt = 0;
+ udelay(10);
+ }
+- vc_bypass_value = vdd->read_reg(vc->common->prm_mod,
+- vc_bypass_val_reg);
++ vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+ }
+
+ omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+@@ -144,18 +140,13 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+
+ static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+-
+ /*
+ * Voltage Manager FSM parameters init
+ * XXX This data should be passed in from the board file
+ */
+- vdd->write_reg(OMAP3_CLKSETUP, vc->common->prm_mod, OMAP3_PRM_CLKSETUP_OFFSET);
+- vdd->write_reg(OMAP3_VOLTOFFSET, vc->common->prm_mod,
+- OMAP3_PRM_VOLTOFFSET_OFFSET);
+- vdd->write_reg(OMAP3_VOLTSETUP2, vc->common->prm_mod,
+- OMAP3_PRM_VOLTSETUP2_OFFSET);
++ voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
++ voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
++ voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
+ }
+
+ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+@@ -178,16 +169,16 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ (onlp_vsel << vc->common->cmd_onlp_shift) |
+ (ret_vsel << vc->common->cmd_ret_shift) |
+ (off_vsel << vc->common->cmd_off_shift));
+- vdd->write_reg(vc_val, vc->common->prm_mod, vc->cmdval_reg);
++ voltdm->write(vc_val, vc->cmdval_reg);
+
+ /*
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+ */
+- vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, vc->common->prm_mod,
+- OMAP3_PRM_VC_CH_CONF_OFFSET);
+- vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, vc->common->prm_mod,
+- OMAP3_PRM_VC_I2C_CFG_OFFSET);
++ voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
++ OMAP3_PRM_VC_CH_CONF_OFFSET);
++ voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
++ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ omap3_vfsm_init(voltdm);
+
+@@ -198,8 +189,6 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ /* OMAP4 specific voltage init functions */
+ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+ u32 vc_val;
+
+@@ -215,11 +204,11 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+ OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+ OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- vdd->write_reg(vc_val, vc->common->prm_mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
++ voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+ /* XXX These are magic numbers and do not belong! */
+ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+- vdd->write_reg(vc_val, vc->common->prm_mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
++ voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+ is_initialized = true;
+ }
+@@ -237,34 +226,30 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ return;
+ }
+
+- if (!vdd->read_reg || !vdd->write_reg) {
++ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+ return;
+ }
+
+ /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(vc->common->prm_mod,
+- vc->common->smps_sa_reg);
++ vc_val = voltdm->read(vc->common->smps_sa_reg);
+ vc_val &= ~vc->smps_sa_mask;
+ vc_val |= vdd->pmic_info->i2c_slave_addr << vc->smps_sa_shift;
+- vdd->write_reg(vc_val, vc->common->prm_mod,
+- vc->common->smps_sa_reg);
++ voltdm->write(vc_val, vc->common->smps_sa_reg);
+
+ /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(vc->common->prm_mod,
+- vc->common->smps_volra_reg);
++ vc_val = voltdm->read(vc->common->smps_volra_reg);
+ vc_val &= ~vc->smps_volra_mask;
+ vc_val |= vdd->pmic_info->volt_reg_addr << vc->smps_volra_shift;
+- vdd->write_reg(vc_val, vc->common->prm_mod,
+- vc->common->smps_volra_reg);
++ voltdm->write(vc_val, vc->common->smps_volra_reg);
+
+ /* Configure the setup times */
+- vc_val = vdd->read_reg(vc->common->prm_mod, vdd->vfsm->voltsetup_reg);
++ vc_val = voltdm->read(vdd->vfsm->voltsetup_reg);
+ vc_val &= ~vdd->vfsm->voltsetup_mask;
+ vc_val |= vdd->pmic_info->volt_setup_time <<
+ vdd->vfsm->voltsetup_shift;
+- vdd->write_reg(vc_val, vc->common->prm_mod, vdd->vfsm->voltsetup_reg);
++ voltdm->write(vc_val, vdd->vfsm->voltsetup_reg);
+
+ if (cpu_is_omap34xx())
+ omap3_vc_init_channel(voltdm);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index 51d36a8..d0050f0 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -25,7 +25,6 @@ struct voltagedomain;
+ * struct omap_vc_common - per-VC register/bitfield data
+ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+ * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
+- * @prm_mod: PRM module id used for PRM register access
+ * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
+ * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
+ * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
+@@ -43,7 +42,6 @@ struct voltagedomain;
+ struct omap_vc_common {
+ u32 cmd_on_mask;
+ u32 valid;
+- s16 prm_mod;
+ u8 smps_sa_reg;
+ u8 smps_volra_reg;
+ u8 bypass_val_reg;
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index 1a17ed4..6b67203 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -30,7 +30,6 @@
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+ static struct omap_vc_common omap3_vc_common = {
+- .prm_mod = OMAP3430_GR_MOD,
+ .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+ .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index 56f3f4a..e3125a3 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -31,7 +31,6 @@
+ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ */
+ static const struct omap_vc_common omap4_vc_common = {
+- .prm_mod = OMAP4430_PRM_DEVICE_INST,
+ .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+ .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 9b9f019..9f9f014 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -46,27 +46,6 @@ static LIST_HEAD(voltdm_list);
+ #define VOLTAGE_DIR_SIZE 16
+ static struct dentry *voltage_dir;
+
+-static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+-{
+- return omap2_prm_read_mod_reg(mod, offset);
+-}
+-
+-static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
+-{
+- omap2_prm_write_mod_reg(val, mod, offset);
+-}
+-
+-static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
+-{
+- return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+- mod, offset);
+-}
+-
+-static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+-{
+- omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+-}
+-
+ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+ char *sys_ck_name;
+@@ -183,15 +162,7 @@ static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ if (IS_ERR_VALUE(_config_common_vdd_data(voltdm)))
+ goto ovdc_out;
+
+- if (cpu_is_omap34xx()) {
+- vdd->read_reg = omap3_voltage_read_reg;
+- vdd->write_reg = omap3_voltage_write_reg;
+- ret = 0;
+- } else if (cpu_is_omap44xx()) {
+- vdd->read_reg = omap4_voltage_read_reg;
+- vdd->write_reg = omap4_voltage_write_reg;
+- ret = 0;
+- }
++ ret = 0;
+
+ ovdc_out:
+ return ret;
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 363eee4..f4198aa 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -68,6 +68,11 @@ struct voltagedomain {
+ struct list_head pwrdm_list;
+ struct omap_vc_channel *vc;
+
++ /* VC/VP register access functions: SoC specific */
++ u32 (*read) (u8 offset);
++ void (*write) (u32 val, u8 offset);
++ u32 (*rmw)(u32 mask, u32 bits, u8 offset);
++
+ struct omap_vdd_info *vdd;
+ };
+
+@@ -144,8 +149,6 @@ struct omap_vdd_info {
+ u32 curr_volt;
+ bool vp_enabled;
+
+- u32 (*read_reg) (u16 mod, u8 offset);
+- void (*write_reg) (u32 val, u16 mod, u8 offset);
+ int (*volt_scale) (struct voltagedomain *voltdm,
+ unsigned long target_volt);
+ };
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index ad8f05b..1d66749 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -56,6 +56,9 @@ static struct omap_vdd_info omap3_vdd2_info = {
+ static struct voltagedomain omap3_voltdm_mpu = {
+ .name = "mpu_iva",
+ .scalable = true,
++ .read = omap3_prm_vcvp_read,
++ .write = omap3_prm_vcvp_write,
++ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_mpu,
+ .vdd = &omap3_vdd1_info,
+ };
+@@ -63,6 +66,9 @@ static struct voltagedomain omap3_voltdm_mpu = {
+ static struct voltagedomain omap3_voltdm_core = {
+ .name = "core",
+ .scalable = true,
++ .read = omap3_prm_vcvp_read,
++ .write = omap3_prm_vcvp_write,
++ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_core,
+ .vdd = &omap3_vdd2_info,
+ };
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 43e1d38..e435795 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -62,6 +62,9 @@ static struct omap_vdd_info omap4_vdd_core_info = {
+ static struct voltagedomain omap4_voltdm_mpu = {
+ .name = "mpu",
+ .scalable = true,
++ .read = omap4_prm_vcvp_read,
++ .write = omap4_prm_vcvp_write,
++ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_mpu,
+ .vdd = &omap4_vdd_mpu_info,
+ };
+@@ -69,6 +72,9 @@ static struct voltagedomain omap4_voltdm_mpu = {
+ static struct voltagedomain omap4_voltdm_iva = {
+ .name = "iva",
+ .scalable = true,
++ .read = omap4_prm_vcvp_read,
++ .write = omap4_prm_vcvp_write,
++ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_iva,
+ .vdd = &omap4_vdd_iva_info,
+ };
+@@ -76,6 +82,9 @@ static struct voltagedomain omap4_voltdm_iva = {
+ static struct voltagedomain omap4_voltdm_core = {
+ .name = "core",
+ .scalable = true,
++ .read = omap4_prm_vcvp_read,
++ .write = omap4_prm_vcvp_write,
++ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_core,
+ .vdd = &omap4_vdd_core_info,
+ };
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 113c839..88ac742 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -35,19 +35,19 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+
+ vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+
+- vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~(vp->vp_common->vpconfig_initvoltage_mask |
+ vp->vp_common->vpconfig_initvdd);
+ vpconfig |= vsel << vp->vp_common->vpconfig_initvoltage_shift;
+
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+- vdd->write_reg((vpconfig | vp->vp_common->vpconfig_initvdd),
+- vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write((vpconfig | vp->vp_common->vpconfig_initvdd),
++ vp->vpconfig);
+
+ /* Clear initVDD copy trigger bit */
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+ }
+
+ /* Generic voltage init functions */
+@@ -57,7 +57,7 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vp_val;
+
+- if (!vdd->read_reg || !vdd->write_reg) {
++ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+ return;
+@@ -67,19 +67,19 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ (vdd->vp_rt_data.vpconfig_errorgain <<
+ vp->vp_common->vpconfig_errorgain_shift) |
+ vp->vp_common->vpconfig_timeouten;
+- vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vp_val, vp->vpconfig);
+
+ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+ vp->vp_common->vstepmin_smpswaittimemin_shift) |
+ (vdd->vp_rt_data.vstepmin_stepmin <<
+ vp->vp_common->vstepmin_stepmin_shift));
+- vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vstepmin);
++ voltdm->write(vp_val, vp->vstepmin);
+
+ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+ vp->vp_common->vstepmax_smpswaittimemax_shift) |
+ (vdd->vp_rt_data.vstepmax_stepmax <<
+ vp->vp_common->vstepmax_stepmax_shift));
+- vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vstepmax);
++ voltdm->write(vp_val, vp->vstepmax);
+
+ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+ vp->vp_common->vlimitto_vddmax_shift) |
+@@ -87,7 +87,7 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ vp->vp_common->vlimitto_vddmin_shift) |
+ (vdd->vp_rt_data.vlimitto_timeout <<
+ vp->vp_common->vlimitto_timeout_shift));
+- vdd->write_reg(vp_val, vp->vp_common->prm_mod, vp->vlimitto);
++ voltdm->write(vp_val, vp->vlimitto);
+
+ vp_debugfs_init(voltdm);
+ }
+@@ -97,7 +97,6 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
+ struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vpconfig;
+ u8 target_vsel, current_vsel;
+ int ret, timeout = 0;
+@@ -123,21 +122,21 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ }
+
+ /* Configure for VP-Force Update */
+- vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~(vp->vp_common->vpconfig_initvdd |
+ vp->vp_common->vpconfig_forceupdate |
+ vp->vp_common->vpconfig_initvoltage_mask);
+ vpconfig |= ((target_vsel <<
+ vp->vp_common->vpconfig_initvoltage_shift));
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+ vpconfig |= vp->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Force update of voltage */
+ vpconfig |= vp->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ /*
+ * Wait for TransactionDone. Typical latency is <200us.
+@@ -170,13 +169,13 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ "to clear the TRANXDONE status\n",
+ __func__, voltdm->name);
+
+- vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig = voltdm->read(vp->vpconfig);
+ /* Clear initVDD copy trigger bit */
+ vpconfig &= ~vp->vp_common->vpconfig_initvdd;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+ /* Clear force bit */
+ vpconfig &= ~vp->vp_common->vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ return 0;
+ }
+@@ -199,13 +198,13 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ }
+
+ vdd = voltdm->vdd;
+- if (!vdd->read_reg) {
++ if (!voltdm->read) {
+ pr_err("%s: No read API for reading vdd_%s regs\n",
+ __func__, voltdm->name);
+ return 0;
+ }
+
+- curr_vsel = vdd->read_reg(vp->vp_common->prm_mod, vp->voltage);
++ curr_vsel = voltdm->read(vp->voltage);
+
+ if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+ pr_warning("%s: PMIC function to convert vsel to voltage"
+@@ -236,7 +235,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+
+ vdd = voltdm->vdd;
+ vp = voltdm->vdd->vp_data;
+- if (!vdd->read_reg || !vdd->write_reg) {
++ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+ return;
+@@ -249,9 +248,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ vp_latch_vsel(voltdm);
+
+ /* Enable VP */
+- vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig |= vp->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+ vdd->vp_enabled = true;
+ }
+
+@@ -276,7 +275,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+
+ vdd = voltdm->vdd;
+ vp = voltdm->vdd->vp_data;
+- if (!vdd->read_reg || !vdd->write_reg) {
++ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+ return;
+@@ -290,15 +289,15 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ }
+
+ /* Disable VP */
+- vpconfig = vdd->read_reg(vp->vp_common->prm_mod, vp->vpconfig);
++ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~vp->vp_common->vpconfig_vpenable;
+- vdd->write_reg(vpconfig, vp->vp_common->prm_mod, vp->vpconfig);
++ voltdm->write(vpconfig, vp->vpconfig);
+
+ /*
+ * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+ */
+- omap_test_timeout((vdd->read_reg(vp->vp_common->prm_mod, vp->vstatus)),
+- VP_IDLE_TIMEOUT, timeout);
++ omap_test_timeout((voltdm->read(vp->vstatus)),
++ VP_IDLE_TIMEOUT, timeout);
+
+ if (timeout >= VP_IDLE_TIMEOUT)
+ pr_warning("%s: vdd_%s idle timedout\n",
+@@ -322,7 +321,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
+ return -EINVAL;
+ }
+
+- vsel = vdd->read_reg(vp->vp_common->prm_mod, vp->voltage);
++ vsel = voltdm->read(vp->voltage);
+
+ if (!vdd->pmic_info->vsel_to_uv) {
+ pr_warning("PMIC function to convert vsel to voltage"
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 2c9cd76..79aa8d3 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -62,7 +62,6 @@ struct omap_vp_ops {
+ * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+- * @prm_mod: PRM module id used for PRM register access
+ *
+ * XXX It it not necessary to have both a mask and a shift for the same
+ * bitfield - remove one
+@@ -75,7 +74,6 @@ struct omap_vp_common_data {
+ u32 vpconfig_initvdd;
+ u32 vpconfig_forceupdate;
+ u32 vpconfig_vpenable;
+- s16 prm_mod;
+ u8 vpconfig_erroroffset_shift;
+ u8 vpconfig_errorgain_shift;
+ u8 vpconfig_initvoltage_shift;
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index 0372c1a..b01d333 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -37,7 +37,6 @@ static const struct omap_vp_ops omap3_vp_ops = {
+ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ */
+ static const struct omap_vp_common_data omap3_vp_common = {
+- .prm_mod = OMAP3430_GR_MOD,
+ .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 738ba04..9704c7b 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -37,7 +37,6 @@ static const struct omap_vp_ops omap4_vp_ops = {
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+ */
+ static const struct omap_vp_common_data omap4_vp_common = {
+- .prm_mod = OMAP4430_PRM_DEVICE_INST,
+ .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0118-OMAP3-VC-cleanup-i2c-slave-address-configuration.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0118-OMAP3-VC-cleanup-i2c-slave-address-configuration.patch
--- /dev/null
@@ -0,0 +1,145 @@
+From 5397d0a64d9fb1a584775e00a56850954c472915 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 29 Mar 2011 14:02:36 -0700
+Subject: [PATCH 118/149] OMAP3+: VC: cleanup i2c slave address configuration
+
+- Add an i2c_slave_address field to the omap_vc_channel
+- use VC/VP read/modify/write helper instead of open-coding
+- remove smps_sa_shift, use __ffs(mask) for shift value
+- I2C addresses 10-bit, change size to u16
+
+Special thanks to Shweta Gulati <shweta.gulati@ti.com> for suggesting
+the use of __ffs(x) instead of ffs(x) - 1.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 12 +++++++-----
+ arch/arm/mach-omap2/vc.h | 8 +++++---
+ arch/arm/mach-omap2/vc3xxx_data.c | 2 --
+ arch/arm/mach-omap2/vc44xx_data.c | 3 ---
+ arch/arm/mach-omap2/voltage.h | 2 +-
+ 5 files changed, 13 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 9c2706c..ca6165d 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -232,11 +232,13 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ return;
+ }
+
+- /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = voltdm->read(vc->common->smps_sa_reg);
+- vc_val &= ~vc->smps_sa_mask;
+- vc_val |= vdd->pmic_info->i2c_slave_addr << vc->smps_sa_shift;
+- voltdm->write(vc_val, vc->common->smps_sa_reg);
++ /* get PMIC/board specific settings */
++ vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
++
++ /* Configure the i2c slave address for this VC */
++ voltdm->rmw(vc->smps_sa_mask,
++ vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
++ vc->common->smps_sa_reg);
+
+ /* Setup the VOLRA(pmic reg addr) in VC */
+ vc_val = voltdm->read(vc->common->smps_volra_reg);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index d0050f0..165fc74 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -57,20 +57,22 @@ struct omap_vc_common {
+ /**
+ * struct omap_vc_channel - VC per-instance data
+ * @common: pointer to VC common data for this platform
+- * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
++ * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+- * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
+ * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
+ *
+ * XXX It is not necessary to have both a *_mask and a *_shift -
+ * remove one
+ */
+ struct omap_vc_channel {
++ /* channel state */
++ u16 i2c_slave_addr;
++
++ /* register access data */
+ const struct omap_vc_common *common;
+ u32 smps_sa_mask;
+ u32 smps_volra_mask;
+ u8 cmdval_reg;
+- u8 smps_sa_shift;
+ u8 smps_volra_shift;
+ };
+
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index 6b67203..86be50c 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -47,7 +47,6 @@ static struct omap_vc_common omap3_vc_common = {
+ struct omap_vc_channel omap3_vc_mpu = {
+ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
+- .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+ .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
+ .smps_volra_mask = OMAP3430_VOLRA0_MASK,
+@@ -56,7 +55,6 @@ struct omap_vc_channel omap3_vc_mpu = {
+ struct omap_vc_channel omap3_vc_core = {
+ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
+- .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+ .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
+ .smps_volra_mask = OMAP3430_VOLRA1_MASK,
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index e3125a3..af922b4 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -49,7 +49,6 @@ static const struct omap_vc_common omap4_vc_common = {
+ struct omap_vc_channel omap4_vc_mpu = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+- .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+ .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
+@@ -58,7 +57,6 @@ struct omap_vc_channel omap4_vc_mpu = {
+ struct omap_vc_channel omap4_vc_iva = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
+- .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
+ .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
+@@ -67,7 +65,6 @@ struct omap_vc_channel omap4_vc_iva = {
+ struct omap_vc_channel omap4_vc_core = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
+- .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
+ .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+ .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index f4198aa..639e85c 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -110,13 +110,13 @@ struct omap_volt_pmic_info {
+ u32 ret_volt;
+ u32 off_volt;
+ u16 volt_setup_time;
++ u16 i2c_slave_addr;
+ u8 vp_erroroffset;
+ u8 vp_vstepmin;
+ u8 vp_vstepmax;
+ u8 vp_vddmin;
+ u8 vp_vddmax;
+ u8 vp_timeout_us;
+- u8 i2c_slave_addr;
+ u8 volt_reg_addr;
+ u8 cmd_reg_addr;
+ unsigned long (*vsel_to_uv) (const u8 vsel);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0119-OMAP3-VC-cleanup-PMIC-register-address-configuration.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0119-OMAP3-VC-cleanup-PMIC-register-address-configuration.patch
--- /dev/null
@@ -0,0 +1,185 @@
+From 10924b191511d8088bfd7a92f26e9ece6f5ecf0d Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Thu, 9 Jun 2011 11:01:55 -0700
+Subject: [PATCH 119/149] OMAP3+: VC: cleanup PMIC register address configuration
+
+- support both voltage register address and command register address
+ for each VC channel
+- add fields for voltage register address (volra) and command register
+ address (cmdra) to struct omap_vc_channel
+- use VC/VP register access read/modify/write helper
+- remove volra_shift field (use __ffs(mask) for shift value)
+- I2C addresses 10-bit, change size to u16
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 17 ++++++++++++-----
+ arch/arm/mach-omap2/vc.h | 9 ++++-----
+ arch/arm/mach-omap2/vc3xxx_data.c | 5 +++--
+ arch/arm/mach-omap2/vc44xx_data.c | 7 ++++---
+ arch/arm/mach-omap2/voltage.h | 4 ++--
+ 5 files changed, 25 insertions(+), 17 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index ca6165d..50b1f7c 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -234,17 +234,24 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+
+ /* get PMIC/board specific settings */
+ vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
++ vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
++ vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
+
+ /* Configure the i2c slave address for this VC */
+ voltdm->rmw(vc->smps_sa_mask,
+ vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
+ vc->common->smps_sa_reg);
+
+- /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = voltdm->read(vc->common->smps_volra_reg);
+- vc_val &= ~vc->smps_volra_mask;
+- vc_val |= vdd->pmic_info->volt_reg_addr << vc->smps_volra_shift;
+- voltdm->write(vc_val, vc->common->smps_volra_reg);
++ /*
++ * Configure the PMIC register addresses.
++ */
++ voltdm->rmw(vc->smps_volra_mask,
++ vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
++ vc->common->smps_volra_reg);
++ if (vc->cmd_reg_addr)
++ voltdm->rmw(vc->smps_cmdra_mask,
++ vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
++ vc->common->smps_cmdra_reg);
+
+ /* Configure the setup times */
+ vc_val = voltdm->read(vdd->vfsm->voltsetup_reg);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index 165fc74..f3b0551 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -44,6 +44,7 @@ struct omap_vc_common {
+ u32 valid;
+ u8 smps_sa_reg;
+ u8 smps_volra_reg;
++ u8 smps_cmdra_reg;
+ u8 bypass_val_reg;
+ u8 data_shift;
+ u8 slaveaddr_shift;
+@@ -59,21 +60,19 @@ struct omap_vc_common {
+ * @common: pointer to VC common data for this platform
+ * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+- * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
+- *
+- * XXX It is not necessary to have both a *_mask and a *_shift -
+- * remove one
+ */
+ struct omap_vc_channel {
+ /* channel state */
+ u16 i2c_slave_addr;
++ u16 volt_reg_addr;
++ u16 cmd_reg_addr;
+
+ /* register access data */
+ const struct omap_vc_common *common;
+ u32 smps_sa_mask;
+ u32 smps_volra_mask;
++ u32 smps_cmdra_mask;
+ u8 cmdval_reg;
+- u8 smps_volra_shift;
+ };
+
+ extern struct omap_vc_channel omap3_vc_mpu;
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index 86be50c..df8bd5e 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -32,6 +32,7 @@
+ static struct omap_vc_common omap3_vc_common = {
+ .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
++ .smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
+ .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
+ .data_shift = OMAP3430_DATA_SHIFT,
+ .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
+@@ -48,14 +49,14 @@ struct omap_vc_channel omap3_vc_mpu = {
+ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+- .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
+ .smps_volra_mask = OMAP3430_VOLRA0_MASK,
++ .smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
+ };
+
+ struct omap_vc_channel omap3_vc_core = {
+ .common = &omap3_vc_common,
+ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+- .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
+ .smps_volra_mask = OMAP3430_VOLRA1_MASK,
++ .smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
+ };
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index af922b4..5d104ff 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -33,6 +33,7 @@
+ static const struct omap_vc_common omap4_vc_common = {
+ .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
+ .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
++ .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
+ .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
+ .data_shift = OMAP4430_DATA_SHIFT,
+ .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
+@@ -50,23 +51,23 @@ struct omap_vc_channel omap4_vc_mpu = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+- .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
++ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
+ };
+
+ struct omap_vc_channel omap4_vc_iva = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
+ .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
+- .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
++ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
+ };
+
+ struct omap_vc_channel omap4_vc_core = {
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
+ .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+- .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
++ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
+ };
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 639e85c..3129d64 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -111,14 +111,14 @@ struct omap_volt_pmic_info {
+ u32 off_volt;
+ u16 volt_setup_time;
+ u16 i2c_slave_addr;
++ u16 volt_reg_addr;
++ u16 cmd_reg_addr;
+ u8 vp_erroroffset;
+ u8 vp_vstepmin;
+ u8 vp_vstepmax;
+ u8 vp_vddmin;
+ u8 vp_vddmax;
+ u8 vp_timeout_us;
+- u8 volt_reg_addr;
+- u8 cmd_reg_addr;
+ unsigned long (*vsel_to_uv) (const u8 vsel);
+ u8 (*uv_to_vsel) (unsigned long uV);
+ };
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0120-OMAP3-VC-bypass-use-fields-from-VC-struct-instead-of.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0120-OMAP3-VC-bypass-use-fields-from-VC-struct-instead-of.patch
--- /dev/null
@@ -0,0 +1,42 @@
+From 3db184c28323c3e35caca12cfc44ff6006d90987 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 29 Mar 2011 14:24:47 -0700
+Subject: [PATCH 120/149] OMAP3+: VC bypass: use fields from VC struct instead of PMIC info
+
+The PMIC configurable variables should be isolated to VC initialization.
+The rest of the VC functions (like VC bypass) should use the i2c slave address
+and voltage register address fields from struct omap_vc_channel.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 7 ++-----
+ 1 files changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 50b1f7c..9e0dc8d 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -91,7 +91,6 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+ u8 target_vsel, current_vsel;
+@@ -104,10 +103,8 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ vc_valid = vc->common->valid;
+ vc_bypass_val_reg = vc->common->bypass_val_reg;
+ vc_bypass_value = (target_vsel << vc->common->data_shift) |
+- (vdd->pmic_info->volt_reg_addr <<
+- vc->common->regaddr_shift) |
+- (vdd->pmic_info->i2c_slave_addr <<
+- vc->common->slaveaddr_shift);
++ (vc->volt_reg_addr << vc->common->regaddr_shift) |
++ (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
+
+ voltdm->write(vc_bypass_value, vc_bypass_val_reg);
+ voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0121-OMAP3-VC-cleanup-voltage-setup-time-configuration.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0121-OMAP3-VC-cleanup-voltage-setup-time-configuration.patch
--- /dev/null
@@ -0,0 +1,227 @@
+From 087e1e0d1abd8b6145c1097e039687d97bc49677 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 29 Mar 2011 14:36:04 -0700
+Subject: [PATCH 121/149] OMAP3+: VC: cleanup voltage setup time configuration
+
+- add setup_time field to struct omap_vc_channel (init'd from PMIC data)
+- use VC/VP register access helper for read/modify/write
+- move VFSM structure from omap_vdd_info into struct voltagedomain
+- remove redunant _data suffix from VFSM structures and variables
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 10 ++++------
+ arch/arm/mach-omap2/vc.h | 1 +
+ arch/arm/mach-omap2/voltage.h | 7 +++----
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 8 ++++----
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 12 ++++++------
+ 5 files changed, 18 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 9e0dc8d..d7415ea 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -214,7 +214,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vc_val;
+
+ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+ pr_err("%s: PMIC info requried to configure vc for"
+@@ -233,6 +232,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
+ vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
+ vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
++ vc->setup_time = vdd->pmic_info->volt_setup_time;
+
+ /* Configure the i2c slave address for this VC */
+ voltdm->rmw(vc->smps_sa_mask,
+@@ -251,11 +251,9 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc->common->smps_cmdra_reg);
+
+ /* Configure the setup times */
+- vc_val = voltdm->read(vdd->vfsm->voltsetup_reg);
+- vc_val &= ~vdd->vfsm->voltsetup_mask;
+- vc_val |= vdd->pmic_info->volt_setup_time <<
+- vdd->vfsm->voltsetup_shift;
+- voltdm->write(vc_val, vdd->vfsm->voltsetup_reg);
++ voltdm->rmw(voltdm->vfsm->voltsetup_mask,
++ vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
++ voltdm->vfsm->voltsetup_reg);
+
+ if (cpu_is_omap34xx())
+ omap3_vc_init_channel(voltdm);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index f3b0551..45e63cf 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -66,6 +66,7 @@ struct omap_vc_channel {
+ u16 i2c_slave_addr;
+ u16 volt_reg_addr;
+ u16 cmd_reg_addr;
++ u16 setup_time;
+
+ /* register access data */
+ const struct omap_vc_common *common;
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 3129d64..2b2ab56 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -36,7 +36,7 @@ struct powerdomain;
+ struct omap_vdd_info;
+
+ /**
+- * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
++ * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
+ * data
+ * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
+ * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
+@@ -46,7 +46,7 @@ struct omap_vdd_info;
+ * XXX It is not necessary to have both a _mask and a _shift for the same
+ * bitfield - remove one!
+ */
+-struct omap_vfsm_instance_data {
++struct omap_vfsm_instance {
+ u32 voltsetup_mask;
+ u8 voltsetup_reg;
+ u8 voltsetup_shift;
+@@ -67,6 +67,7 @@ struct voltagedomain {
+ struct list_head node;
+ struct list_head pwrdm_list;
+ struct omap_vc_channel *vc;
++ const struct omap_vfsm_instance *vfsm;
+
+ /* VC/VP register access functions: SoC specific */
+ u32 (*read) (u8 offset);
+@@ -133,7 +134,6 @@ struct omap_volt_pmic_info {
+ * @vp_data : the register values, shifts, masks for various
+ * vp registers
+ * @vp_rt_data : VP data derived at runtime, not predefined
+- * @vfsm : voltage manager FSM data
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+ * @vp_enabled : flag to keep track of whether vp is enabled or not
+@@ -144,7 +144,6 @@ struct omap_vdd_info {
+ struct omap_volt_pmic_info *pmic_info;
+ struct omap_vp_instance_data *vp_data;
+ struct omap_vp_runtime_data vp_rt_data;
+- const struct omap_vfsm_instance_data *vfsm;
+ struct dentry *debug_dir;
+ u32 curr_volt;
+ bool vp_enabled;
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 1d66749..4ea9a7b 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -31,7 +31,7 @@
+ * VDD data
+ */
+
+-static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
++static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
+ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+ .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT,
+ .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
+@@ -39,10 +39,9 @@ static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
+
+ static struct omap_vdd_info omap3_vdd1_info = {
+ .vp_data = &omap3_vp1_data,
+- .vfsm = &omap3_vdd1_vfsm_data,
+ };
+
+-static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
++static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
+ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+ .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
+ .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
+@@ -50,7 +49,6 @@ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
+
+ static struct omap_vdd_info omap3_vdd2_info = {
+ .vp_data = &omap3_vp2_data,
+- .vfsm = &omap3_vdd2_vfsm_data,
+ };
+
+ static struct voltagedomain omap3_voltdm_mpu = {
+@@ -60,6 +58,7 @@ static struct voltagedomain omap3_voltdm_mpu = {
+ .write = omap3_prm_vcvp_write,
+ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_mpu,
++ .vfsm = &omap3_vdd1_vfsm,
+ .vdd = &omap3_vdd1_info,
+ };
+
+@@ -70,6 +69,7 @@ static struct voltagedomain omap3_voltdm_core = {
+ .write = omap3_prm_vcvp_write,
+ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_core,
++ .vfsm = &omap3_vdd2_vfsm,
+ .vdd = &omap3_vdd2_info,
+ };
+
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index e435795..dd4bd22 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -32,31 +32,28 @@
+ #include "vc.h"
+ #include "vp.h"
+
+-static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
++static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+ };
+
+ static struct omap_vdd_info omap4_vdd_mpu_info = {
+ .vp_data = &omap4_vp_mpu_data,
+- .vfsm = &omap4_vdd_mpu_vfsm_data,
+ };
+
+-static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
++static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+ };
+
+ static struct omap_vdd_info omap4_vdd_iva_info = {
+ .vp_data = &omap4_vp_iva_data,
+- .vfsm = &omap4_vdd_iva_vfsm_data,
+ };
+
+-static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
++static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+ };
+
+ static struct omap_vdd_info omap4_vdd_core_info = {
+ .vp_data = &omap4_vp_core_data,
+- .vfsm = &omap4_vdd_core_vfsm_data,
+ };
+
+ static struct voltagedomain omap4_voltdm_mpu = {
+@@ -66,6 +63,7 @@ static struct voltagedomain omap4_voltdm_mpu = {
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_mpu,
++ .vfsm = &omap4_vdd_mpu_vfsm,
+ .vdd = &omap4_vdd_mpu_info,
+ };
+
+@@ -76,6 +74,7 @@ static struct voltagedomain omap4_voltdm_iva = {
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_iva,
++ .vfsm = &omap4_vdd_iva_vfsm,
+ .vdd = &omap4_vdd_iva_info,
+ };
+
+@@ -86,6 +85,7 @@ static struct voltagedomain omap4_voltdm_core = {
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_core,
++ .vfsm = &omap4_vdd_core_vfsm,
+ .vdd = &omap4_vdd_core_info,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0122-OMAP3-VC-move-on-onlp-ret-off-command-configuration-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0122-OMAP3-VC-move-on-onlp-ret-off-command-configuration-.patch
--- /dev/null
@@ -0,0 +1,83 @@
+From 2249fbc45176b89440f05663afedc6a3da9bf515 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 29 Mar 2011 15:14:38 -0700
+Subject: [PATCH 122/149] OMAP3+: VC: move on/onlp/ret/off command configuration into common init
+
+Configuring the on/onlp/ret/off command values is common to OMAP3 & 4.
+Move from OMAP3-only init into common VC init.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 30 +++++++++++++-----------------
+ 1 files changed, 13 insertions(+), 17 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index d7415ea..7df4438 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -148,26 +148,11 @@ static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+
+ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ {
+- struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ static bool is_initialized;
+- u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+- u32 vc_val;
+
+ if (is_initialized)
+ return;
+
+- /* Set up the on, inactive, retention and off voltage */
+- on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+- onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+- ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+- off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+- vc_val = ((on_vsel << vc->common->cmd_on_shift) |
+- (onlp_vsel << vc->common->cmd_onlp_shift) |
+- (ret_vsel << vc->common->cmd_ret_shift) |
+- (off_vsel << vc->common->cmd_off_shift));
+- voltdm->write(vc_val, vc->cmdval_reg);
+-
+ /*
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+@@ -192,8 +177,6 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ if (is_initialized)
+ return;
+
+- /* TODO: Configure setup times and CMD_VAL values*/
+-
+ /*
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+@@ -214,6 +197,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
++ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
++ u32 val;
+
+ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+ pr_err("%s: PMIC info requried to configure vc for"
+@@ -250,6 +235,17 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
+ vc->common->smps_cmdra_reg);
+
++ /* Set up the on, inactive, retention and off voltage */
++ on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
++ onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
++ ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
++ off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
++ val = ((on_vsel << vc->common->cmd_on_shift) |
++ (onlp_vsel << vc->common->cmd_onlp_shift) |
++ (ret_vsel << vc->common->cmd_ret_shift) |
++ (off_vsel << vc->common->cmd_off_shift));
++ voltdm->write(val, vc->cmdval_reg);
++
+ /* Configure the setup times */
+ voltdm->rmw(voltdm->vfsm->voltsetup_mask,
+ vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0123-OMAP3-VC-abstract-out-channel-configuration.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0123-OMAP3-VC-abstract-out-channel-configuration.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0123-OMAP3-VC-abstract-out-channel-configuration.patch
@@ -0,0 +1,267 @@
+From 9573101a96ff70b5fbd4c5c8827b562e562c85dd Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 29 Mar 2011 15:57:16 -0700
+Subject: [PATCH 123/149] OMAP3+: VC: abstract out channel configuration
+
+VC channel configuration is programmed based on settings coming from
+the PMIC configuration.
+
+Currently, the VC channel to PMIC mapping is a simple one-to-one
+mapping. Whenever a VC channel parameter is configured (i2c slave
+addres, PMIC register address, on/ret/off command), the corresponding
+bits are enabled in the VC channel configuration register.
+
+If necessary, the programmability of channel configuration settings
+could be extended to board/PMIC files, however, because this patch
+changes the channel configuration to be programmed based on existing
+values from the PMIC settings, it may not be required.
+
+Also note that starting with OMAP4, where there are more than 2
+channels, one channel is identified as the "default" channel. When
+any of the bits in the channel config for the other channels are zero,
+it means to use the default channel. The OMAP4 TRM (at least through
+NDA version Q) is wrong in describing which is the default channel.
+The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 70 ++++++++++++++++++++++++++++++------
+ arch/arm/mach-omap2/vc.h | 9 +++++
+ arch/arm/mach-omap2/vc3xxx_data.c | 3 ++
+ arch/arm/mach-omap2/vc44xx_data.c | 5 +++
+ 4 files changed, 75 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 7df4438..e413b97 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -10,6 +10,52 @@
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+
++/*
++ * Channel configuration bits, common for OMAP3 & 4
++ * OMAP3 register: PRM_VC_CH_CONF
++ * OMAP4 register: PRM_VC_CFG_CHANNEL
++ */
++#define CFG_CHANNEL_SA BIT(0)
++#define CFG_CHANNEL_RAV BIT(1)
++#define CFG_CHANNEL_RAC BIT(2)
++#define CFG_CHANNEL_RACEN BIT(3)
++#define CFG_CHANNEL_CMD BIT(4)
++#define CFG_CHANNEL_MASK 0x3f
++
++/**
++ * omap_vc_config_channel - configure VC channel to PMIC mappings
++ * @voltdm: pointer to voltagdomain defining the desired VC channel
++ *
++ * Configures the VC channel to PMIC mappings for the following
++ * PMIC settings
++ * - i2c slave address (SA)
++ * - voltage configuration address (RAV)
++ * - command configuration address (RAC) and enable bit (RACEN)
++ * - command values for ON, ONLP, RET and OFF (CMD)
++ *
++ * This function currently only allows flexible configuration of the
++ * non-default channel. Starting with OMAP4, there are more than 2
++ * channels, with one defined as the default (on OMAP4, it's MPU.)
++ * Only the non-default channel can be configured.
++ */
++static int omap_vc_config_channel(struct voltagedomain *voltdm)
++{
++ struct omap_vc_channel *vc = voltdm->vc;
++
++ /*
++ * For default channel, the only configurable bit is RACEN.
++ * All others must stay at zero (see function comment above.)
++ */
++ if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
++ vc->cfg_channel &= CFG_CHANNEL_RACEN;
++
++ voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
++ vc->cfg_channel << vc->cfg_channel_sa_shift,
++ vc->common->cfg_channel_reg);
++
++ return 0;
++}
++
+ /* Voltage scale and accessory APIs */
+ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt,
+@@ -157,8 +203,6 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ * Generic VC parameters init
+ * XXX This data should be abstracted out
+ */
+- voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
+- OMAP3_PRM_VC_CH_CONF_OFFSET);
+ voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+@@ -177,15 +221,6 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ if (is_initialized)
+ return;
+
+- /*
+- * Generic VC parameters init
+- * XXX This data should be abstracted out
+- */
+- vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+- OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+- OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+-
+ /* XXX These are magic numbers and do not belong! */
+ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+ voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+@@ -213,6 +248,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ return;
+ }
+
++ vc->cfg_channel = 0;
++
+ /* get PMIC/board specific settings */
+ vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
+ vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
+@@ -223,6 +260,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ voltdm->rmw(vc->smps_sa_mask,
+ vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
+ vc->common->smps_sa_reg);
++ vc->cfg_channel |= CFG_CHANNEL_SA;
+
+ /*
+ * Configure the PMIC register addresses.
+@@ -230,10 +268,14 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ voltdm->rmw(vc->smps_volra_mask,
+ vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
+ vc->common->smps_volra_reg);
+- if (vc->cmd_reg_addr)
++ vc->cfg_channel |= CFG_CHANNEL_RAV;
++
++ if (vc->cmd_reg_addr) {
+ voltdm->rmw(vc->smps_cmdra_mask,
+ vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
+ vc->common->smps_cmdra_reg);
++ vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
++ }
+
+ /* Set up the on, inactive, retention and off voltage */
+ on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+@@ -245,6 +287,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ (ret_vsel << vc->common->cmd_ret_shift) |
+ (off_vsel << vc->common->cmd_off_shift));
+ voltdm->write(val, vc->cmdval_reg);
++ vc->cfg_channel |= CFG_CHANNEL_CMD;
++
++ /* Channel configuration */
++ omap_vc_config_channel(voltdm);
+
+ /* Configure the setup times */
+ voltdm->rmw(voltdm->vfsm->voltsetup_mask,
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index 45e63cf..604f5b6 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -53,20 +53,28 @@ struct omap_vc_common {
+ u8 cmd_onlp_shift;
+ u8 cmd_ret_shift;
+ u8 cmd_off_shift;
++ u8 cfg_channel_reg;
+ };
+
++/* omap_vc_channel.flags values */
++#define OMAP_VC_CHANNEL_DEFAULT BIT(0)
++
+ /**
+ * struct omap_vc_channel - VC per-instance data
++ * @flags: VC channel-specific flags (optional)
+ * @common: pointer to VC common data for this platform
+ * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
+ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ */
+ struct omap_vc_channel {
++ u8 flags;
++
+ /* channel state */
+ u16 i2c_slave_addr;
+ u16 volt_reg_addr;
+ u16 cmd_reg_addr;
+ u16 setup_time;
++ u8 cfg_channel;
+
+ /* register access data */
+ const struct omap_vc_common *common;
+@@ -74,6 +82,7 @@ struct omap_vc_channel {
+ u32 smps_volra_mask;
+ u32 smps_cmdra_mask;
+ u8 cmdval_reg;
++ u8 cfg_channel_sa_shift;
+ };
+
+ extern struct omap_vc_channel omap3_vc_mpu;
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index df8bd5e..f4449eb 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -43,6 +43,7 @@ static struct omap_vc_common omap3_vc_common = {
+ .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
+ .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
+ .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
++ .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
+ };
+
+ struct omap_vc_channel omap3_vc_mpu = {
+@@ -51,6 +52,7 @@ struct omap_vc_channel omap3_vc_mpu = {
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+ .smps_volra_mask = OMAP3430_VOLRA0_MASK,
+ .smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
++ .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
+ };
+
+ struct omap_vc_channel omap3_vc_core = {
+@@ -59,4 +61,5 @@ struct omap_vc_channel omap3_vc_core = {
+ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+ .smps_volra_mask = OMAP3430_VOLRA1_MASK,
+ .smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
++ .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
+ };
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index 5d104ff..1610bde 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -44,15 +44,18 @@ static const struct omap_vc_common omap4_vc_common = {
+ .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
+ .cmd_ret_shift = OMAP4430_RET_SHIFT,
+ .cmd_off_shift = OMAP4430_OFF_SHIFT,
++ .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
+ };
+
+ /* VC instance data for each controllable voltage line */
+ struct omap_vc_channel omap4_vc_mpu = {
++ .flags = OMAP_VC_CHANNEL_DEFAULT,
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
+ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
++ .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
+ };
+
+ struct omap_vc_channel omap4_vc_iva = {
+@@ -61,6 +64,7 @@ struct omap_vc_channel omap4_vc_iva = {
+ .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
+ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
++ .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
+ };
+
+ struct omap_vc_channel omap4_vc_core = {
+@@ -69,5 +73,6 @@ struct omap_vc_channel omap4_vc_core = {
+ .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+ .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
+ .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
++ .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0124-OMAP3-voltage-domain-move-PMIC-struct-from-vdd_info-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0124-OMAP3-voltage-domain-move-PMIC-struct-from-vdd_info-.patch
--- /dev/null
@@ -0,0 +1,394 @@
+From 6f3800731e92de02088fb0203dc9afa47c188f5e Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 30 Mar 2011 11:01:10 -0700
+Subject: [PATCH 124/149] OMAP3+: voltage domain: move PMIC struct from vdd_info into struct voltagedomain
+
+Move structure containing PMIC configurable settings into struct
+voltagedomain. In the process, rename from omap_volt_pmic_info to
+omap_voltdm_pmic (_info suffix is not helpful.)
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 28 ++++++++++++++--------------
+ arch/arm/mach-omap2/vc.c | 29 ++++++++++++++---------------
+ arch/arm/mach-omap2/voltage.c | 29 ++++++++++++-----------------
+ arch/arm/mach-omap2/voltage.h | 12 +++++-------
+ arch/arm/mach-omap2/vp.c | 13 ++++++-------
+ 5 files changed, 51 insertions(+), 60 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 3249fe3..e467d45 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -143,7 +143,7 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
+ return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+ }
+
+-static struct omap_volt_pmic_info omap3_mpu_volt_info = {
++static struct omap_voltdm_pmic omap3_mpu_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt = 1200000,
+@@ -163,7 +163,7 @@ static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+
+-static struct omap_volt_pmic_info omap3_core_volt_info = {
++static struct omap_voltdm_pmic omap3_core_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt = 1200000,
+@@ -183,7 +183,7 @@ static struct omap_volt_pmic_info omap3_core_volt_info = {
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+
+-static struct omap_volt_pmic_info omap4_mpu_volt_info = {
++static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt = 1350000,
+@@ -203,7 +203,7 @@ static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+
+-static struct omap_volt_pmic_info omap4_iva_volt_info = {
++static struct omap_voltdm_pmic omap4_iva_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt = 1100000,
+@@ -223,7 +223,7 @@ static struct omap_volt_pmic_info omap4_iva_volt_info = {
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+
+-static struct omap_volt_pmic_info omap4_core_volt_info = {
++static struct omap_voltdm_pmic omap4_core_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt = 1100000,
+@@ -251,13 +251,13 @@ int __init omap4_twl_init(void)
+ return -ENODEV;
+
+ voltdm = voltdm_lookup("mpu");
+- omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
++ omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
+
+ voltdm = voltdm_lookup("iva");
+- omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
++ omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
+
+ voltdm = voltdm_lookup("core");
+- omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
++ omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
+
+ return 0;
+ }
+@@ -270,10 +270,10 @@ int __init omap3_twl_init(void)
+ return -ENODEV;
+
+ if (cpu_is_omap3630()) {
+- omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
+- omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
+- omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
+- omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
++ omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
++ omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
++ omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
++ omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
+ }
+
+ /*
+@@ -289,10 +289,10 @@ int __init omap3_twl_init(void)
+ omap3_twl_set_sr_bit(true);
+
+ voltdm = voltdm_lookup("mpu_iva");
+- omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
++ omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
+
+ voltdm = voltdm_lookup("core");
+- omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
++ omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index e413b97..c431ca2 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -70,13 +70,13 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ vp_common = vdd->vp_data->vp_common;
+
+ /* Check if sufficient pmic info is available for this vdd */
+- if (!vdd->pmic_info) {
++ if (!voltdm->pmic) {
+ pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+ __func__, voltdm->name);
+ return -EINVAL;
+ }
+
+- if (!vdd->pmic_info->uv_to_vsel) {
++ if (!voltdm->pmic->uv_to_vsel) {
+ pr_err("%s: PMIC function to convert voltage in uV to"
+ "vsel not registered. Hence unable to scale voltage"
+ "for vdd_%s\n", __func__, voltdm->name);
+@@ -94,7 +94,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ if (IS_ERR(volt_data))
+ volt_data = NULL;
+
+- *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
++ *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+ *current_vsel = voltdm->read(vdd->vp_data->voltage);
+
+ /* Setting the ON voltage to the new target voltage */
+@@ -125,8 +125,8 @@ void omap_vc_post_scale(struct voltagedomain *voltdm,
+
+ smps_steps = abs(target_vsel - current_vsel);
+ /* SMPS slew rate / step size. 2us added as buffer. */
+- smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
+- vdd->pmic_info->slew_rate) + 2;
++ smps_delay = ((smps_steps * voltdm->pmic->step_size) /
++ voltdm->pmic->slew_rate) + 2;
+ udelay(smps_delay);
+
+ vdd->curr_volt = target_volt;
+@@ -231,11 +231,10 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+ u32 val;
+
+- if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
++ if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+ pr_err("%s: PMIC info requried to configure vc for"
+ "vdd_%s not populated.Hence cannot initialize vc\n",
+ __func__, voltdm->name);
+@@ -251,10 +250,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc->cfg_channel = 0;
+
+ /* get PMIC/board specific settings */
+- vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
+- vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
+- vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
+- vc->setup_time = vdd->pmic_info->volt_setup_time;
++ vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
++ vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
++ vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
++ vc->setup_time = voltdm->pmic->volt_setup_time;
+
+ /* Configure the i2c slave address for this VC */
+ voltdm->rmw(vc->smps_sa_mask,
+@@ -278,10 +277,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ }
+
+ /* Set up the on, inactive, retention and off voltage */
+- on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+- onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+- ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+- off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
++ on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
++ onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
++ ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
++ off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
+ val = ((on_vsel << vc->common->cmd_on_shift) |
+ (onlp_vsel << vc->common->cmd_onlp_shift) |
+ (ret_vsel << vc->common->cmd_ret_shift) |
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 9f9f014..94f7fc4 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -84,20 +84,20 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ vdd->vp_enabled = false;
+
+ vdd->vp_rt_data.vpconfig_erroroffset =
+- (vdd->pmic_info->vp_erroroffset <<
++ (voltdm->pmic->vp_erroroffset <<
+ vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
+
+- timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
++ timeout_val = (sys_clk_speed * voltdm->pmic->vp_timeout_us) / 1000;
+ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+- vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+- vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
++ vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
++ vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
+
+- waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
++ waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+ sys_clk_speed) / 1000;
+ vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
+ vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
+- vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+- vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
++ vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
++ vdd->vp_rt_data.vstepmax_stepmax = voltdm->pmic->vp_vstepmax;
+
+ return 0;
+ }
+@@ -149,10 +149,9 @@ static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+
+ static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ {
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ int ret = -EINVAL;
+
+- if (!vdd->pmic_info) {
++ if (!voltdm->pmic) {
+ pr_err("%s: PMIC info requried to configure vdd_%s not"
+ "populated.Hence cannot initialize vdd_%s\n",
+ __func__, voltdm->name, voltdm->name);
+@@ -324,24 +323,20 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ * omap_voltage_register_pmic() - API to register PMIC specific data
+ * @voltdm: pointer to the VDD for which the PMIC specific data is
+ * to be registered
+- * @pmic_info: the structure containing pmic info
++ * @pmic: the structure containing pmic info
+ *
+ * This API is to be called by the SOC/PMIC file to specify the
+- * pmic specific info as present in omap_volt_pmic_info structure.
++ * pmic specific info as present in omap_voltdm_pmic structure.
+ */
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+- struct omap_volt_pmic_info *pmic_info)
++ struct omap_voltdm_pmic *pmic)
+ {
+- struct omap_vdd_info *vdd;
+-
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return -EINVAL;
+ }
+
+- vdd = voltdm->vdd;
+-
+- vdd->pmic_info = pmic_info;
++ voltdm->pmic = pmic;
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 2b2ab56..72a0255 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -68,6 +68,7 @@ struct voltagedomain {
+ struct list_head pwrdm_list;
+ struct omap_vc_channel *vc;
+ const struct omap_vfsm_instance *vfsm;
++ struct omap_voltdm_pmic *pmic;
+
+ /* VC/VP register access functions: SoC specific */
+ u32 (*read) (u8 offset);
+@@ -97,13 +98,13 @@ struct omap_volt_data {
+ };
+
+ /**
+- * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
++ * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
+ * @slew_rate: PMIC slew rate (in uv/us)
+ * @step_size: PMIC voltage step size (in uv)
+ * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
+ * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
+ */
+-struct omap_volt_pmic_info {
++struct omap_voltdm_pmic {
+ int slew_rate;
+ int step_size;
+ u32 on_volt;
+@@ -129,8 +130,6 @@ struct omap_volt_pmic_info {
+ *
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+- * @pmic_info : pmic specific parameters which should be populted by
+- * the pmic drivers.
+ * @vp_data : the register values, shifts, masks for various
+ * vp registers
+ * @vp_rt_data : VP data derived at runtime, not predefined
+@@ -141,7 +140,6 @@ struct omap_volt_pmic_info {
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+- struct omap_volt_pmic_info *pmic_info;
+ struct omap_vp_instance_data *vp_data;
+ struct omap_vp_runtime_data vp_rt_data;
+ struct dentry *debug_dir;
+@@ -163,13 +161,13 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+- struct omap_volt_pmic_info *pmic_info);
++ struct omap_voltdm_pmic *pmic);
+ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ int voltscale_method);
+ int omap_voltage_late_init(void);
+ #else
+ static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+- struct omap_volt_pmic_info *pmic_info)
++ struct omap_voltdm_pmic *pmic)
+ {
+ return -EINVAL;
+ }
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 88ac742..a3afcbe 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -18,7 +18,6 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ u32 vpconfig;
+ unsigned long uvdc;
+ char vsel;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+
+ uvdc = omap_voltage_get_nom_volt(voltdm);
+ if (!uvdc) {
+@@ -27,13 +26,13 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ return;
+ }
+
+- if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
++ if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+ pr_warning("%s: PMIC function to convert voltage in uV to"
+ " vsel not registered\n", __func__);
+ return;
+ }
+
+- vsel = vdd->pmic_info->uv_to_vsel(uvdc);
++ vsel = voltdm->pmic->uv_to_vsel(uvdc);
+
+ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~(vp->vp_common->vpconfig_initvoltage_mask |
+@@ -206,13 +205,13 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+
+ curr_vsel = voltdm->read(vp->voltage);
+
+- if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
++ if (!voltdm->pmic || !voltdm->pmic->vsel_to_uv) {
+ pr_warning("%s: PMIC function to convert vsel to voltage"
+ "in uV not registerd\n", __func__);
+ return 0;
+ }
+
+- return vdd->pmic_info->vsel_to_uv(curr_vsel);
++ return voltdm->pmic->vsel_to_uv(curr_vsel);
+ }
+
+ /**
+@@ -323,13 +322,13 @@ static int vp_volt_debug_get(void *data, u64 *val)
+
+ vsel = voltdm->read(vp->voltage);
+
+- if (!vdd->pmic_info->vsel_to_uv) {
++ if (!voltdm->pmic->vsel_to_uv) {
+ pr_warning("PMIC function to convert vsel to voltage"
+ "in uV not registerd\n");
+ return -EINVAL;
+ }
+
+- *val = vdd->pmic_info->vsel_to_uv(vsel);
++ *val = voltdm->pmic->vsel_to_uv(vsel);
+ return 0;
+ }
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0125-OMAP3-VC-make-I2C-config-programmable-with-PMIC-spec.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0125-OMAP3-VC-make-I2C-config-programmable-with-PMIC-spec.patch
--- /dev/null
@@ -0,0 +1,221 @@
+From 1b324ddbae1ae703264e7cd81a5636f4d789f977 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Wed, 30 Mar 2011 16:36:30 -0700
+Subject: [PATCH 125/149] OMAP3+: VC: make I2C config programmable with PMIC-specific settings
+
+Remove hard-coded I2C configuration in favor of settings that can be
+configured from PMIC-specific values. Currently only high-speed mode
+and the master-code value are supported, since they were the only
+fields currently used, but extending this is now trivial.
+
+Thanks to Nishanth Menon <nm@ti.com> for reporting/fixing a sparse
+problem and making omap_vc_i2c_init() static, as well as finding and
+fixing a problem with the shift/mask of mcode.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 4 +++
+ arch/arm/mach-omap2/vc.c | 51 +++++++++++++++++++++++++++++++-----
+ arch/arm/mach-omap2/vc.h | 7 +++++
+ arch/arm/mach-omap2/vc3xxx_data.c | 3 ++
+ arch/arm/mach-omap2/vc44xx_data.c | 3 ++
+ arch/arm/mach-omap2/voltage.h | 4 +++
+ 6 files changed, 65 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index e467d45..6b247d1 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -159,6 +159,7 @@ static struct omap_voltdm_pmic omap3_mpu_pmic = {
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
++ .i2c_high_speed = true,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+@@ -179,6 +180,7 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
++ .i2c_high_speed = true,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+ };
+@@ -199,6 +201,7 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
++ .i2c_high_speed = true,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+@@ -219,6 +222,7 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
++ .i2c_high_speed = true,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index c431ca2..97a4c6c 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -199,13 +199,6 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ if (is_initialized)
+ return;
+
+- /*
+- * Generic VC parameters init
+- * XXX This data should be abstracted out
+- */
+- voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
+- OMAP3_PRM_VC_I2C_CFG_OFFSET);
+-
+ omap3_vfsm_init(voltdm);
+
+ is_initialized = true;
+@@ -228,6 +221,48 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
+ is_initialized = true;
+ }
+
++/**
++ * omap_vc_i2c_init - initialize I2C interface to PMIC
++ * @voltdm: voltage domain containing VC data
++ *
++ * Use PMIC supplied seetings for I2C high-speed mode and
++ * master code (if set) and program the VC I2C configuration
++ * register.
++ *
++ * The VC I2C configuration is common to all VC channels,
++ * so this function only configures I2C for the first VC
++ * channel registers. All other VC channels will use the
++ * same configuration.
++ */
++static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
++{
++ struct omap_vc_channel *vc = voltdm->vc;
++ static bool initialized;
++ static bool i2c_high_speed;
++ u8 mcode;
++
++ if (initialized) {
++ if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
++ pr_warn("%s: I2C config for all channels must match.",
++ __func__);
++ return;
++ }
++
++ i2c_high_speed = voltdm->pmic->i2c_high_speed;
++ if (i2c_high_speed)
++ voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
++ vc->common->i2c_cfg_hsen_mask,
++ vc->common->i2c_cfg_reg);
++
++ mcode = voltdm->pmic->i2c_mcode;
++ if (mcode)
++ voltdm->rmw(vc->common->i2c_mcode_mask,
++ mcode << __ffs(vc->common->i2c_mcode_mask),
++ vc->common->i2c_cfg_reg);
++
++ initialized = true;
++}
++
+ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+@@ -296,6 +331,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
+ voltdm->vfsm->voltsetup_reg);
+
++ omap_vc_i2c_init(voltdm);
++
+ if (cpu_is_omap34xx())
+ omap3_vc_init_channel(voltdm);
+ else if (cpu_is_omap44xx())
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index 604f5b6..c577f28 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -35,6 +35,9 @@ struct voltagedomain;
+ * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
+ * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
+ * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
++ * @i2c_cfg_reg: I2C configuration register offset
++ * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
++ * @i2c_mcode_mask: MCODE field mask for I2C config register
+ *
+ * XXX One of cmd_on_mask and cmd_on_shift are not needed
+ * XXX VALID should probably be a shift, not a mask
+@@ -54,6 +57,9 @@ struct omap_vc_common {
+ u8 cmd_ret_shift;
+ u8 cmd_off_shift;
+ u8 cfg_channel_reg;
++ u8 i2c_cfg_reg;
++ u8 i2c_cfg_hsen_mask;
++ u8 i2c_mcode_mask;
+ };
+
+ /* omap_vc_channel.flags values */
+@@ -75,6 +81,7 @@ struct omap_vc_channel {
+ u16 cmd_reg_addr;
+ u16 setup_time;
+ u8 cfg_channel;
++ bool i2c_high_speed;
+
+ /* register access data */
+ const struct omap_vc_common *common;
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+index f4449eb..95d7701 100644
+--- a/arch/arm/mach-omap2/vc3xxx_data.c
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -44,6 +44,9 @@ static struct omap_vc_common omap3_vc_common = {
+ .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
+ .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
+ .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
++ .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
++ .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET,
++ .i2c_mcode_mask = OMAP3430_MCODE_MASK,
+ };
+
+ struct omap_vc_channel omap3_vc_mpu = {
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index 1610bde..148be18 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -45,6 +45,9 @@ static const struct omap_vc_common omap4_vc_common = {
+ .cmd_ret_shift = OMAP4430_RET_SHIFT,
+ .cmd_off_shift = OMAP4430_OFF_SHIFT,
+ .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
++ .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
++ .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
++ .i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
+ };
+
+ /* VC instance data for each controllable voltage line */
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 72a0255..a0ae5c6 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -101,6 +101,8 @@ struct omap_volt_data {
+ * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
+ * @slew_rate: PMIC slew rate (in uv/us)
+ * @step_size: PMIC voltage step size (in uv)
++ * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
++ * @i2c_mcode: master code value for I2C high-speed preamble transmission
+ * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
+ * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
+ */
+@@ -121,6 +123,8 @@ struct omap_voltdm_pmic {
+ u8 vp_vddmin;
+ u8 vp_vddmax;
+ u8 vp_timeout_us;
++ bool i2c_high_speed;
++ u8 i2c_mcode;
+ unsigned long (*vsel_to_uv) (const u8 vsel);
+ u8 (*uv_to_vsel) (unsigned long uV);
+ };
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0126-OMAP3-PM-VC-handle-mutant-channel-config-for-OMAP4-M.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0126-OMAP3-PM-VC-handle-mutant-channel-config-for-OMAP4-M.patch
--- /dev/null
@@ -0,0 +1,168 @@
+From 0fe5ac0063ae6a4a59848a050e2f0d2ae41eb374 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Thu, 2 Jun 2011 17:28:13 -0700
+Subject: [PATCH 126/149] OMAP3+: PM: VC: handle mutant channel config for OMAP4 MPU channel
+
+On OMAP3+, all VC channels have the the same bitfield ordering for all
+VC channels, except the OMAP4 MPU channel. This appears to be a freak
+accident as all other VC channel (including OMAP5) have the standard
+configuration. Handle the mutant case by adding a per-channel flag
+to signal the deformity and handle it during VC init.
+
+Special thanks to Nishanth Menon <nm@ti.com> for finding this problem
+and for proposing the initial solution.
+
+Cc: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 64 +++++++++++++++++++++++++++++-------
+ arch/arm/mach-omap2/vc.h | 1 +
+ arch/arm/mach-omap2/vc44xx_data.c | 2 +-
+ 3 files changed, 53 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 97a4c6c..9e51782 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -10,17 +10,51 @@
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+
+-/*
+- * Channel configuration bits, common for OMAP3 & 4
++/**
++ * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
++ * @sa: bit for slave address
++ * @rav: bit for voltage configuration register
++ * @rac: bit for command configuration register
++ * @racen: enable bit for RAC
++ * @cmd: bit for command value set selection
++ *
++ * Channel configuration bits, common for OMAP3+
+ * OMAP3 register: PRM_VC_CH_CONF
+ * OMAP4 register: PRM_VC_CFG_CHANNEL
++ * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
+ */
+-#define CFG_CHANNEL_SA BIT(0)
+-#define CFG_CHANNEL_RAV BIT(1)
+-#define CFG_CHANNEL_RAC BIT(2)
+-#define CFG_CHANNEL_RACEN BIT(3)
+-#define CFG_CHANNEL_CMD BIT(4)
+-#define CFG_CHANNEL_MASK 0x3f
++struct omap_vc_channel_cfg {
++ u8 sa;
++ u8 rav;
++ u8 rac;
++ u8 racen;
++ u8 cmd;
++};
++
++static struct omap_vc_channel_cfg vc_default_channel_cfg = {
++ .sa = BIT(0),
++ .rav = BIT(1),
++ .rac = BIT(2),
++ .racen = BIT(3),
++ .cmd = BIT(4),
++};
++
++/*
++ * On OMAP3+, all VC channels have the above default bitfield
++ * configuration, except the OMAP4 MPU channel. This appears
++ * to be a freak accident as every other VC channel has the
++ * default configuration, thus creating a mutant channel config.
++ */
++static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
++ .sa = BIT(0),
++ .rav = BIT(2),
++ .rac = BIT(3),
++ .racen = BIT(4),
++ .cmd = BIT(1),
++};
++
++static struct omap_vc_channel_cfg *vc_cfg_bits;
++#define CFG_CHANNEL_MASK 0x1f
+
+ /**
+ * omap_vc_config_channel - configure VC channel to PMIC mappings
+@@ -47,7 +81,7 @@ static int omap_vc_config_channel(struct voltagedomain *voltdm)
+ * All others must stay at zero (see function comment above.)
+ */
+ if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
+- vc->cfg_channel &= CFG_CHANNEL_RACEN;
++ vc->cfg_channel &= vc_cfg_bits->racen;
+
+ voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
+ vc->cfg_channel << vc->cfg_channel_sa_shift,
+@@ -283,6 +317,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ }
+
+ vc->cfg_channel = 0;
++ if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
++ vc_cfg_bits = &vc_mutant_channel_cfg;
++ else
++ vc_cfg_bits = &vc_default_channel_cfg;
+
+ /* get PMIC/board specific settings */
+ vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
+@@ -294,7 +332,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ voltdm->rmw(vc->smps_sa_mask,
+ vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
+ vc->common->smps_sa_reg);
+- vc->cfg_channel |= CFG_CHANNEL_SA;
++ vc->cfg_channel |= vc_cfg_bits->sa;
+
+ /*
+ * Configure the PMIC register addresses.
+@@ -302,13 +340,13 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ voltdm->rmw(vc->smps_volra_mask,
+ vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
+ vc->common->smps_volra_reg);
+- vc->cfg_channel |= CFG_CHANNEL_RAV;
++ vc->cfg_channel |= vc_cfg_bits->rav;
+
+ if (vc->cmd_reg_addr) {
+ voltdm->rmw(vc->smps_cmdra_mask,
+ vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
+ vc->common->smps_cmdra_reg);
+- vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
++ vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
+ }
+
+ /* Set up the on, inactive, retention and off voltage */
+@@ -321,7 +359,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ (ret_vsel << vc->common->cmd_ret_shift) |
+ (off_vsel << vc->common->cmd_off_shift));
+ voltdm->write(val, vc->cmdval_reg);
+- vc->cfg_channel |= CFG_CHANNEL_CMD;
++ vc->cfg_channel |= vc_cfg_bits->cmd;
+
+ /* Channel configuration */
+ omap_vc_config_channel(voltdm);
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+index c577f28..ec50643 100644
+--- a/arch/arm/mach-omap2/vc.h
++++ b/arch/arm/mach-omap2/vc.h
+@@ -64,6 +64,7 @@ struct omap_vc_common {
+
+ /* omap_vc_channel.flags values */
+ #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
++#define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
+
+ /**
+ * struct omap_vc_channel - VC per-instance data
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+index 148be18..0a4fc37 100644
+--- a/arch/arm/mach-omap2/vc44xx_data.c
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -52,7 +52,7 @@ static const struct omap_vc_common omap4_vc_common = {
+
+ /* VC instance data for each controllable voltage line */
+ struct omap_vc_channel omap4_vc_mpu = {
+- .flags = OMAP_VC_CHANNEL_DEFAULT,
++ .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
+ .common = &omap4_vc_common,
+ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
+ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0127-OMAP3-VC-use-last-nominal-voltage-setting-to-get-cur.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0127-OMAP3-VC-use-last-nominal-voltage-setting-to-get-cur.patch
--- /dev/null
@@ -0,0 +1,31 @@
+From 3b45948294a7607c40825f1a4c603bfa249deb0a Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 18 Jul 2011 15:31:00 -0700
+Subject: [PATCH 127/149] OMAP3+: VC: use last nominal voltage setting to get current_vsel
+
+Instead of reading current vsel value from the VP's voltage register,
+just use current nominal voltage translated into vsel via the PMIC.
+
+Doing this allows VC bypass scaling to work even without a VP configured.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 9e51782..cee8fba 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -129,7 +129,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ volt_data = NULL;
+
+ *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+- *current_vsel = voltdm->read(vdd->vp_data->voltage);
++ *current_vsel = voltdm->pmic->uv_to_vsel(vdd->curr_volt);
+
+ /* Setting the ON voltage to the new target voltage */
+ vc_cmdval = voltdm->read(vc->cmdval_reg);
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0128-OMAP3-VP-cleanup-move-VP-instance-into-voltdm-misc.-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0128-OMAP3-VP-cleanup-move-VP-instance-into-voltdm-misc.-.patch
--- /dev/null
@@ -0,0 +1,643 @@
+From 5390da5519736e33eaf3d64b65fec8771b412b69 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 4 Apr 2011 15:25:07 -0700
+Subject: [PATCH 128/149] OMAP3+: VP: cleanup: move VP instance into voltdm, misc. renames
+
+- move VP instance struct from vdd_info into struct voltage domain
+- remove _data suffix from structure name
+- rename vp_ prefix from vp_common field: accesses are now vp->common
+- move vp_enabled bool from vdd_info into VP instance
+- remove remaining references to omap_vdd_info
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 11 +--
+ arch/arm/mach-omap2/voltage.c | 4 +-
+ arch/arm/mach-omap2/voltage.h | 6 +--
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 10 +--
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 15 ++---
+ arch/arm/mach-omap2/vp.c | 88 ++++++++++++-------------
+ arch/arm/mach-omap2/vp.h | 24 ++++---
+ arch/arm/mach-omap2/vp3xxx_data.c | 10 ++--
+ arch/arm/mach-omap2/vp44xx_data.c | 14 ++--
+ 9 files changed, 83 insertions(+), 99 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index cee8fba..7058585 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -98,11 +98,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ struct omap_vc_channel *vc = voltdm->vc;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ struct omap_volt_data *volt_data;
+- const struct omap_vp_common_data *vp_common;
+ u32 vc_cmdval, vp_errgain_val;
+
+- vp_common = vdd->vp_data->vp_common;
+-
+ /* Check if sufficient pmic info is available for this vdd */
+ if (!voltdm->pmic) {
+ pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+@@ -139,12 +136,12 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+
+ /* Setting vp errorgain based on the voltage */
+ if (volt_data) {
+- vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
++ vp_errgain_val = voltdm->read(voltdm->vp->vpconfig);
+ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+- vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
++ vp_errgain_val &= voltdm->vp->common->vpconfig_errorgain_mask;
+ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+- vp_common->vpconfig_errorgain_shift;
+- voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
++ voltdm->vp->common->vpconfig_errorgain_shift;
++ voltdm->write(vp_errgain_val, voltdm->vp->vpconfig);
+ }
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 94f7fc4..c22b53c 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -81,11 +81,11 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+
+ /* Generic voltage parameters */
+ vdd->volt_scale = omap_vp_forceupdate_scale;
+- vdd->vp_enabled = false;
++ voltdm->vp->enabled = false;
+
+ vdd->vp_rt_data.vpconfig_erroroffset =
+ (voltdm->pmic->vp_erroroffset <<
+- vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
++ voltdm->vp->common->vpconfig_erroroffset_shift);
+
+ timeout_val = (sys_clk_speed * voltdm->pmic->vp_timeout_us) / 1000;
+ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index a0ae5c6..65f94c7 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -68,6 +68,7 @@ struct voltagedomain {
+ struct list_head pwrdm_list;
+ struct omap_vc_channel *vc;
+ const struct omap_vfsm_instance *vfsm;
++ struct omap_vp_instance *vp;
+ struct omap_voltdm_pmic *pmic;
+
+ /* VC/VP register access functions: SoC specific */
+@@ -134,21 +135,16 @@ struct omap_voltdm_pmic {
+ *
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+- * @vp_data : the register values, shifts, masks for various
+- * vp registers
+ * @vp_rt_data : VP data derived at runtime, not predefined
+ * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+- * @vp_enabled : flag to keep track of whether vp is enabled or not
+ * @volt_scale : API to scale the voltage of the vdd.
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+- struct omap_vp_instance_data *vp_data;
+ struct omap_vp_runtime_data vp_rt_data;
+ struct dentry *debug_dir;
+ u32 curr_volt;
+- bool vp_enabled;
+
+ int (*volt_scale) (struct voltagedomain *voltdm,
+ unsigned long target_volt);
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 4ea9a7b..4db2c6c 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -37,9 +37,7 @@ static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
+ .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
+ };
+
+-static struct omap_vdd_info omap3_vdd1_info = {
+- .vp_data = &omap3_vp1_data,
+-};
++static struct omap_vdd_info omap3_vdd1_info;
+
+ static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
+ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+@@ -47,9 +45,7 @@ static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
+ .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
+ };
+
+-static struct omap_vdd_info omap3_vdd2_info = {
+- .vp_data = &omap3_vp2_data,
+-};
++static struct omap_vdd_info omap3_vdd2_info;
+
+ static struct voltagedomain omap3_voltdm_mpu = {
+ .name = "mpu_iva",
+@@ -59,6 +55,7 @@ static struct voltagedomain omap3_voltdm_mpu = {
+ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_mpu,
+ .vfsm = &omap3_vdd1_vfsm,
++ .vp = &omap3_vp_mpu,
+ .vdd = &omap3_vdd1_info,
+ };
+
+@@ -70,6 +67,7 @@ static struct voltagedomain omap3_voltdm_core = {
+ .rmw = omap3_prm_vcvp_rmw,
+ .vc = &omap3_vc_core,
+ .vfsm = &omap3_vdd2_vfsm,
++ .vp = &omap3_vp_core,
+ .vdd = &omap3_vdd2_info,
+ };
+
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index dd4bd22..3e7cb4e 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -36,25 +36,19 @@ static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_mpu_info = {
+- .vp_data = &omap4_vp_mpu_data,
+-};
++static struct omap_vdd_info omap4_vdd_mpu_info;
+
+ static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_iva_info = {
+- .vp_data = &omap4_vp_iva_data,
+-};
++static struct omap_vdd_info omap4_vdd_iva_info;
+
+ static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_core_info = {
+- .vp_data = &omap4_vp_core_data,
+-};
++static struct omap_vdd_info omap4_vdd_core_info;
+
+ static struct voltagedomain omap4_voltdm_mpu = {
+ .name = "mpu",
+@@ -64,6 +58,7 @@ static struct voltagedomain omap4_voltdm_mpu = {
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_mpu,
+ .vfsm = &omap4_vdd_mpu_vfsm,
++ .vp = &omap4_vp_mpu,
+ .vdd = &omap4_vdd_mpu_info,
+ };
+
+@@ -75,6 +70,7 @@ static struct voltagedomain omap4_voltdm_iva = {
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_iva,
+ .vfsm = &omap4_vdd_iva_vfsm,
++ .vp = &omap4_vp_iva,
+ .vdd = &omap4_vdd_iva_info,
+ };
+
+@@ -86,6 +82,7 @@ static struct voltagedomain omap4_voltdm_core = {
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_core,
+ .vfsm = &omap4_vdd_core_vfsm,
++ .vp = &omap4_vp_core,
+ .vdd = &omap4_vdd_core_info,
+ };
+
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index a3afcbe..53d6018 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -14,7 +14,7 @@ static void __init vp_debugfs_init(struct voltagedomain *voltdm);
+
+ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ {
+- struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vp_instance *vp = voltdm->vp;
+ u32 vpconfig;
+ unsigned long uvdc;
+ char vsel;
+@@ -35,14 +35,14 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ vsel = voltdm->pmic->uv_to_vsel(uvdc);
+
+ vpconfig = voltdm->read(vp->vpconfig);
+- vpconfig &= ~(vp->vp_common->vpconfig_initvoltage_mask |
+- vp->vp_common->vpconfig_initvdd);
+- vpconfig |= vsel << vp->vp_common->vpconfig_initvoltage_shift;
++ vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
++ vp->common->vpconfig_initvdd);
++ vpconfig |= vsel << vp->common->vpconfig_initvoltage_shift;
+
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+- voltdm->write((vpconfig | vp->vp_common->vpconfig_initvdd),
++ voltdm->write((vpconfig | vp->common->vpconfig_initvdd),
+ vp->vpconfig);
+
+ /* Clear initVDD copy trigger bit */
+@@ -52,7 +52,7 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ /* Generic voltage init functions */
+ void __init omap_vp_init(struct voltagedomain *voltdm)
+ {
+- struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vp_instance *vp = voltdm->vp;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 vp_val;
+
+@@ -64,28 +64,28 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+
+ vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+ (vdd->vp_rt_data.vpconfig_errorgain <<
+- vp->vp_common->vpconfig_errorgain_shift) |
+- vp->vp_common->vpconfig_timeouten;
++ vp->common->vpconfig_errorgain_shift) |
++ vp->common->vpconfig_timeouten;
+ voltdm->write(vp_val, vp->vpconfig);
+
+ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+- vp->vp_common->vstepmin_smpswaittimemin_shift) |
++ vp->common->vstepmin_smpswaittimemin_shift) |
+ (vdd->vp_rt_data.vstepmin_stepmin <<
+- vp->vp_common->vstepmin_stepmin_shift));
++ vp->common->vstepmin_stepmin_shift));
+ voltdm->write(vp_val, vp->vstepmin);
+
+ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+- vp->vp_common->vstepmax_smpswaittimemax_shift) |
++ vp->common->vstepmax_smpswaittimemax_shift) |
+ (vdd->vp_rt_data.vstepmax_stepmax <<
+- vp->vp_common->vstepmax_stepmax_shift));
++ vp->common->vstepmax_stepmax_shift));
+ voltdm->write(vp_val, vp->vstepmax);
+
+ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+- vp->vp_common->vlimitto_vddmax_shift) |
++ vp->common->vlimitto_vddmax_shift) |
+ (vdd->vp_rt_data.vlimitto_vddmin <<
+- vp->vp_common->vlimitto_vddmin_shift) |
++ vp->common->vlimitto_vddmin_shift) |
+ (vdd->vp_rt_data.vlimitto_timeout <<
+- vp->vp_common->vlimitto_timeout_shift));
++ vp->common->vlimitto_timeout_shift));
+ voltdm->write(vp_val, vp->vlimitto);
+
+ vp_debugfs_init(voltdm);
+@@ -95,7 +95,7 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
+- struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vp_instance *vp = voltdm->vp;
+ u32 vpconfig;
+ u8 target_vsel, current_vsel;
+ int ret, timeout = 0;
+@@ -109,8 +109,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ * is <3us
+ */
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vp->vp_common->ops->clear_txdone(vp->id);
+- if (!vp->vp_common->ops->check_txdone(vp->id))
++ vp->common->ops->clear_txdone(vp->id);
++ if (!vp->common->ops->check_txdone(vp->id))
+ break;
+ udelay(1);
+ }
+@@ -122,19 +122,19 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+
+ /* Configure for VP-Force Update */
+ vpconfig = voltdm->read(vp->vpconfig);
+- vpconfig &= ~(vp->vp_common->vpconfig_initvdd |
+- vp->vp_common->vpconfig_forceupdate |
+- vp->vp_common->vpconfig_initvoltage_mask);
++ vpconfig &= ~(vp->common->vpconfig_initvdd |
++ vp->common->vpconfig_forceupdate |
++ vp->common->vpconfig_initvoltage_mask);
+ vpconfig |= ((target_vsel <<
+- vp->vp_common->vpconfig_initvoltage_shift));
++ vp->common->vpconfig_initvoltage_shift));
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+- vpconfig |= vp->vp_common->vpconfig_initvdd;
++ vpconfig |= vp->common->vpconfig_initvdd;
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Force update of voltage */
+- vpconfig |= vp->vp_common->vpconfig_forceupdate;
++ vpconfig |= vp->common->vpconfig_forceupdate;
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /*
+@@ -142,7 +142,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ */
+ timeout = 0;
+- omap_test_timeout(vp->vp_common->ops->check_txdone(vp->id),
++ omap_test_timeout(vp->common->ops->check_txdone(vp->id),
+ VP_TRANXDONE_TIMEOUT, timeout);
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+@@ -157,8 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ */
+ timeout = 0;
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vp->vp_common->ops->clear_txdone(vp->id);
+- if (!vp->vp_common->ops->check_txdone(vp->id))
++ vp->common->ops->clear_txdone(vp->id);
++ if (!vp->common->ops->check_txdone(vp->id))
+ break;
+ udelay(1);
+ }
+@@ -170,10 +170,10 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+
+ vpconfig = voltdm->read(vp->vpconfig);
+ /* Clear initVDD copy trigger bit */
+- vpconfig &= ~vp->vp_common->vpconfig_initvdd;
++ vpconfig &= ~vp->common->vpconfig_initvdd;
+ voltdm->write(vpconfig, vp->vpconfig);
+ /* Clear force bit */
+- vpconfig &= ~vp->vp_common->vpconfig_forceupdate;
++ vpconfig &= ~vp->common->vpconfig_forceupdate;
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ return 0;
+@@ -187,8 +187,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ */
+ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ {
+- struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
+- struct omap_vdd_info *vdd;
++ struct omap_vp_instance *vp = voltdm->vp;
+ u8 curr_vsel;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+@@ -196,7 +195,6 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- vdd = voltdm->vdd;
+ if (!voltdm->read) {
+ pr_err("%s: No read API for reading vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -223,8 +221,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ */
+ void omap_vp_enable(struct voltagedomain *voltdm)
+ {
+- struct omap_vp_instance_data *vp;
+- struct omap_vdd_info *vdd;
++ struct omap_vp_instance *vp;
+ u32 vpconfig;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+@@ -232,8 +229,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- vdd = voltdm->vdd;
+- vp = voltdm->vdd->vp_data;
++ vp = voltdm->vp;
+ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -241,16 +237,16 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ }
+
+ /* If VP is already enabled, do nothing. Return */
+- if (vdd->vp_enabled)
++ if (vp->enabled)
+ return;
+
+ vp_latch_vsel(voltdm);
+
+ /* Enable VP */
+ vpconfig = voltdm->read(vp->vpconfig);
+- vpconfig |= vp->vp_common->vpconfig_vpenable;
++ vpconfig |= vp->common->vpconfig_vpenable;
+ voltdm->write(vpconfig, vp->vpconfig);
+- vdd->vp_enabled = true;
++ vp->enabled = true;
+ }
+
+ /**
+@@ -262,8 +258,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ */
+ void omap_vp_disable(struct voltagedomain *voltdm)
+ {
+- struct omap_vp_instance_data *vp;
+- struct omap_vdd_info *vdd;
++ struct omap_vp_instance *vp;
+ u32 vpconfig;
+ int timeout;
+
+@@ -272,8 +267,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- vdd = voltdm->vdd;
+- vp = voltdm->vdd->vp_data;
++ vp = voltdm->vp;
+ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ __func__, voltdm->name);
+@@ -281,7 +275,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ }
+
+ /* If VP is already disabled, do nothing. Return */
+- if (!vdd->vp_enabled) {
++ if (!vp->enabled) {
+ pr_warning("%s: Trying to disable VP for vdd_%s when"
+ "it is already disabled\n", __func__, voltdm->name);
+ return;
+@@ -289,7 +283,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+
+ /* Disable VP */
+ vpconfig = voltdm->read(vp->vpconfig);
+- vpconfig &= ~vp->vp_common->vpconfig_vpenable;
++ vpconfig &= ~vp->common->vpconfig_vpenable;
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /*
+@@ -302,7 +296,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ pr_warning("%s: vdd_%s idle timedout\n",
+ __func__, voltdm->name);
+
+- vdd->vp_enabled = false;
++ vp->enabled = false;
+
+ return;
+ }
+@@ -311,7 +305,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ static int vp_volt_debug_get(void *data, u64 *val)
+ {
+ struct voltagedomain *voltdm = (struct voltagedomain *)data;
+- struct omap_vp_instance_data *vp = voltdm->vdd->vp_data;
++ struct omap_vp_instance *vp = voltdm->vp;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+ u8 vsel;
+
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 79aa8d3..1d63960 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -45,7 +45,7 @@ struct omap_vp_ops {
+ };
+
+ /**
+- * struct omap_vp_common_data - register data common to all VDDs
++ * struct omap_vp_common - register data common to all VDDs
+ * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
+@@ -67,7 +67,7 @@ struct omap_vp_ops {
+ * bitfield - remove one
+ * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
+ */
+-struct omap_vp_common_data {
++struct omap_vp_common {
+ u32 vpconfig_errorgain_mask;
+ u32 vpconfig_initvoltage_mask;
+ u32 vpconfig_timeouten;
+@@ -89,18 +89,19 @@ struct omap_vp_common_data {
+ };
+
+ /**
+- * struct omap_vp_instance_data - VP register offsets (per-VDD)
+- * @vp_common: pointer to struct omap_vp_common_data * for this SoC
++ * struct omap_vp_instance - VP register offsets (per-VDD)
++ * @common: pointer to struct omap_vp_common * for this SoC
+ * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
+ * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
+ * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
+ * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
+ * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
++ * @enabled: flag to keep track of whether vp is enabled or not
+ *
+ * XXX vp_common is probably not needed since it is per-SoC
+ */
+-struct omap_vp_instance_data {
+- const struct omap_vp_common_data *vp_common;
++struct omap_vp_instance {
++ const struct omap_vp_common *common;
+ u8 vpconfig;
+ u8 vstepmin;
+ u8 vstepmax;
+@@ -108,6 +109,7 @@ struct omap_vp_instance_data {
+ u8 vstatus;
+ u8 voltage;
+ u8 id;
++ bool enabled;
+ };
+
+ /**
+@@ -139,12 +141,12 @@ struct omap_vp_runtime_data {
+ u8 vlimitto_vddmax;
+ };
+
+-extern struct omap_vp_instance_data omap3_vp1_data;
+-extern struct omap_vp_instance_data omap3_vp2_data;
++extern struct omap_vp_instance omap3_vp_mpu;
++extern struct omap_vp_instance omap3_vp_core;
+
+-extern struct omap_vp_instance_data omap4_vp_mpu_data;
+-extern struct omap_vp_instance_data omap4_vp_iva_data;
+-extern struct omap_vp_instance_data omap4_vp_core_data;
++extern struct omap_vp_instance omap4_vp_mpu;
++extern struct omap_vp_instance omap4_vp_iva;
++extern struct omap_vp_instance omap4_vp_core;
+
+ void omap_vp_init(struct voltagedomain *voltdm);
+ void omap_vp_enable(struct voltagedomain *voltdm);
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index b01d333..79c3df9 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -36,7 +36,7 @@ static const struct omap_vp_ops omap3_vp_ops = {
+ * VP data common to 34xx/36xx chips
+ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ */
+-static const struct omap_vp_common_data omap3_vp_common = {
++static const struct omap_vp_common omap3_vp_common = {
+ .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
+@@ -56,9 +56,9 @@ static const struct omap_vp_common_data omap3_vp_common = {
+ .ops = &omap3_vp_ops,
+ };
+
+-struct omap_vp_instance_data omap3_vp1_data = {
++struct omap_vp_instance omap3_vp_mpu = {
+ .id = OMAP3_VP_VDD_MPU_ID,
+- .vp_common = &omap3_vp_common,
++ .common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+ .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
+@@ -67,9 +67,9 @@ struct omap_vp_instance_data omap3_vp1_data = {
+ .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+ };
+
+-struct omap_vp_instance_data omap3_vp2_data = {
++struct omap_vp_instance omap3_vp_core = {
+ .id = OMAP3_VP_VDD_CORE_ID,
+- .vp_common = &omap3_vp_common,
++ .common = &omap3_vp_common,
+ .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+ .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+ .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 9704c7b..8f75cd9 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -36,7 +36,7 @@ static const struct omap_vp_ops omap4_vp_ops = {
+ * VP data common to 44xx chips
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+ */
+-static const struct omap_vp_common_data omap4_vp_common = {
++static const struct omap_vp_common omap4_vp_common = {
+ .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
+ .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
+ .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
+@@ -56,9 +56,9 @@ static const struct omap_vp_common_data omap4_vp_common = {
+ .ops = &omap4_vp_ops,
+ };
+
+-struct omap_vp_instance_data omap4_vp_mpu_data = {
++struct omap_vp_instance omap4_vp_mpu = {
+ .id = OMAP4_VP_VDD_MPU_ID,
+- .vp_common = &omap4_vp_common,
++ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+ .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+@@ -67,9 +67,9 @@ struct omap_vp_instance_data omap4_vp_mpu_data = {
+ .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+ };
+
+-struct omap_vp_instance_data omap4_vp_iva_data = {
++struct omap_vp_instance omap4_vp_iva = {
+ .id = OMAP4_VP_VDD_IVA_ID,
+- .vp_common = &omap4_vp_common,
++ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+ .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+@@ -78,9 +78,9 @@ struct omap_vp_instance_data omap4_vp_iva_data = {
+ .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+ };
+
+-struct omap_vp_instance_data omap4_vp_core_data = {
++struct omap_vp_instance omap4_vp_core = {
+ .id = OMAP4_VP_VDD_CORE_ID,
+- .vp_common = &omap4_vp_common,
++ .common = &omap4_vp_common,
+ .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+ .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+ .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0129-OMAP3-voltage-remove-unneeded-debugfs-interface.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0129-OMAP3-voltage-remove-unneeded-debugfs-interface.patch
--- /dev/null
@@ -0,0 +1,317 @@
+From e5c58a35cfeae3070aa92cdeb9c7e108d391f602 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 5 Apr 2011 14:39:11 -0700
+Subject: [PATCH 129/149] OMAP3+: voltage: remove unneeded debugfs interface
+
+Remove read-only debugfs interface to VP values. Most of the values
+are init-time only and never change. Current voltage value should be
+retreived from the (eventual) regulator framework interface to the
+voltage domain.
+
+Fixes to original version provided by Nishanth Menon <nm@ti.com>
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/smartreflex.c | 29 +++++++++-----
+ arch/arm/mach-omap2/voltage.c | 78 -------------------------------------
+ arch/arm/mach-omap2/voltage.h | 3 -
+ arch/arm/mach-omap2/vp.c | 63 -----------------------------
+ 4 files changed, 19 insertions(+), 154 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index 2ce2fb7..f8c6305 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -62,6 +62,7 @@ static LIST_HEAD(sr_list);
+
+ static struct omap_sr_class_data *sr_class;
+ static struct omap_sr_pmic_data *sr_pmic_data;
++static struct dentry *sr_dbg_dir;
+
+ static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+ {
+@@ -826,9 +827,10 @@ static int __init omap_sr_probe(struct platform_device *pdev)
+ struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+ struct omap_sr_data *pdata = pdev->dev.platform_data;
+ struct resource *mem, *irq;
+- struct dentry *vdd_dbg_dir, *nvalue_dir;
++ struct dentry *nvalue_dir;
+ struct omap_volt_data *volt_data;
+ int i, ret = 0;
++ char *name;
+
+ if (!sr_info) {
+ dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+@@ -898,18 +900,25 @@ static int __init omap_sr_probe(struct platform_device *pdev)
+ }
+
+ dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
++ if (!sr_dbg_dir) {
++ sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
++ if (!sr_dbg_dir) {
++ ret = PTR_ERR(sr_dbg_dir);
++ pr_err("%s:sr debugfs dir creation failed(%d)\n",
++ __func__, ret);
++ goto err_iounmap;
++ }
++ }
+
+- /*
+- * If the voltage domain debugfs directory is not created, do
+- * not try to create rest of the debugfs entries.
+- */
+- vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
+- if (!vdd_dbg_dir) {
+- ret = -EINVAL;
++ name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
++ if (!name) {
++ dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
++ __func__);
++ ret = -ENOMEM;
+ goto err_iounmap;
+ }
+-
+- sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
++ sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
++ kfree(name);
+ if (IS_ERR(sr_info->dbg_dir)) {
+ dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+ __func__);
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index c22b53c..eaa5f93 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -43,9 +43,6 @@
+
+ static LIST_HEAD(voltdm_list);
+
+-#define VOLTAGE_DIR_SIZE 16
+-static struct dentry *voltage_dir;
+-
+ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+ char *sys_ck_name;
+@@ -102,51 +99,6 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+-static int nom_volt_debug_get(void *data, u64 *val)
+-{
+- struct voltagedomain *voltdm = (struct voltagedomain *)data;
+-
+- if (!voltdm) {
+- pr_warning("Wrong paramater passed\n");
+- return -EINVAL;
+- }
+-
+- *val = omap_voltage_get_nom_volt(voltdm);
+-
+- return 0;
+-}
+-
+-DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+- "%llu\n");
+-static void __init vdd_debugfs_init(struct voltagedomain *voltdm)
+-{
+- char *name;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+-
+- name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL);
+- if (!name) {
+- pr_warning("%s: Unable to allocate memory for debugfs"
+- " directory name for vdd_%s",
+- __func__, voltdm->name);
+- return;
+- }
+- strcpy(name, "vdd_");
+- strcat(name, voltdm->name);
+-
+- vdd->debug_dir = debugfs_create_dir(name, voltage_dir);
+- kfree(name);
+- if (IS_ERR(vdd->debug_dir)) {
+- pr_warning("%s: Unable to create debugfs directory for"
+- " vdd_%s\n", __func__, voltdm->name);
+- vdd->debug_dir = NULL;
+- return;
+- }
+-
+- (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+- vdd->debug_dir, (void *) voltdm,
+- &nom_volt_debug_fops);
+-}
+-
+ static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+ {
+ int ret = -EINVAL;
+@@ -342,31 +294,6 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ }
+
+ /**
+- * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory
+- * corresponding to a voltage domain.
+- *
+- * @voltdm: pointer to the VDD whose debug directory is required.
+- *
+- * This API returns pointer to the debugfs directory corresponding
+- * to the voltage domain. Should be used by drivers requiring to
+- * add any debug entry for a particular voltage domain. Returns NULL
+- * in case of error.
+- */
+-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd;
+-
+- if (!voltdm || IS_ERR(voltdm)) {
+- pr_warning("%s: VDD specified does not exist!\n", __func__);
+- return NULL;
+- }
+-
+- vdd = voltdm->vdd;
+-
+- return vdd->debug_dir;
+-}
+-
+-/**
+ * omap_change_voltscale_method() - API to change the voltage scaling method.
+ * @voltdm: pointer to the VDD whose voltage scaling method
+ * has to be changed.
+@@ -418,10 +345,6 @@ int __init omap_voltage_late_init(void)
+ return -EINVAL;
+ }
+
+- voltage_dir = debugfs_create_dir("voltage", NULL);
+- if (IS_ERR(voltage_dir))
+- pr_err("%s: Unable to create voltage debugfs main dir\n",
+- __func__);
+ list_for_each_entry(voltdm, &voltdm_list, node) {
+ if (!voltdm->scalable)
+ continue;
+@@ -434,7 +357,6 @@ int __init omap_voltage_late_init(void)
+ if (voltdm->vdd) {
+ if (omap_vdd_data_configure(voltdm))
+ continue;
+- vdd_debugfs_init(voltdm);
+ omap_vp_init(voltdm);
+ }
+ }
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 65f94c7..5261703 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -136,14 +136,12 @@ struct omap_voltdm_pmic {
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+ * @vp_rt_data : VP data derived at runtime, not predefined
+- * @debug_dir : debug directory for this voltage domain.
+ * @curr_volt : current voltage for this vdd.
+ * @volt_scale : API to scale the voltage of the vdd.
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+ struct omap_vp_runtime_data vp_rt_data;
+- struct dentry *debug_dir;
+ u32 curr_volt;
+
+ int (*volt_scale) (struct voltagedomain *voltdm,
+@@ -158,7 +156,6 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ unsigned long volt);
+ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ struct omap_voltdm_pmic *pmic);
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 53d6018..c9a315f 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -1,6 +1,5 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+-#include <linux/debugfs.h>
+
+ #include <plat/common.h>
+
+@@ -10,8 +9,6 @@
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+
+-static void __init vp_debugfs_init(struct voltagedomain *voltdm);
+-
+ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ {
+ struct omap_vp_instance *vp = voltdm->vp;
+@@ -87,8 +84,6 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ (vdd->vp_rt_data.vlimitto_timeout <<
+ vp->common->vlimitto_timeout_shift));
+ voltdm->write(vp_val, vp->vlimitto);
+-
+- vp_debugfs_init(voltdm);
+ }
+
+ /* VP force update method of voltage scaling */
+@@ -300,61 +295,3 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+
+ return;
+ }
+-
+-/* Voltage debugfs support */
+-static int vp_volt_debug_get(void *data, u64 *val)
+-{
+- struct voltagedomain *voltdm = (struct voltagedomain *)data;
+- struct omap_vp_instance *vp = voltdm->vp;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u8 vsel;
+-
+- if (!vdd) {
+- pr_warning("Wrong paramater passed\n");
+- return -EINVAL;
+- }
+-
+- vsel = voltdm->read(vp->voltage);
+-
+- if (!voltdm->pmic->vsel_to_uv) {
+- pr_warning("PMIC function to convert vsel to voltage"
+- "in uV not registerd\n");
+- return -EINVAL;
+- }
+-
+- *val = voltdm->pmic->vsel_to_uv(vsel);
+- return 0;
+-}
+-
+-DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
+-
+-static void __init vp_debugfs_init(struct voltagedomain *voltdm)
+-{
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- struct dentry *debug_dir;
+-
+- debug_dir = debugfs_create_dir("vp", vdd->debug_dir);
+- if (IS_ERR(debug_dir))
+- pr_err("%s: Unable to create VP debugfs dir dir\n", __func__);
+-
+- (void) debugfs_create_x16("errorgain", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vpconfig_errorgain));
+- (void) debugfs_create_x16("smpswaittimemin", S_IRUGO,
+- debug_dir,
+- &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
+- (void) debugfs_create_x8("stepmin", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vstepmin_stepmin));
+- (void) debugfs_create_x16("smpswaittimemax", S_IRUGO,
+- debug_dir,
+- &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
+- (void) debugfs_create_x8("stepmax", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vstepmax_stepmax));
+- (void) debugfs_create_x8("vddmax", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vlimitto_vddmax));
+- (void) debugfs_create_x8("vddmin", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vlimitto_vddmin));
+- (void) debugfs_create_x16("timeout", S_IRUGO, debug_dir,
+- &(vdd->vp_rt_data.vlimitto_timeout));
+- (void) debugfs_create_file("curr_volt", S_IRUGO, debug_dir,
+- (void *) voltdm, &vp_volt_debug_fops);
+-}
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0130-OMAP3-VP-struct-omap_vp_common-replace-shift-with-__.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0130-OMAP3-VP-struct-omap_vp_common-replace-shift-with-__.patch
--- /dev/null
@@ -0,0 +1,214 @@
+From c727fd3a2d5ff8bff64537bf270791615cdf6847 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 4 Apr 2011 16:02:28 -0700
+Subject: [PATCH 130/149] OMAP3+: VP: struct omap_vp_common: replace shift with __ffs(mask)
+
+In struct omap_vp_common, the shift value can be derived from the mask
+value by using __ffs(), so remove the shift value for the various
+VPCONFIG bitfields, and use __ffs() in the code for the shift value.
+
+While here, rename field names in kerneldoc comment to match actual
+field names in structure. Also, cleanup indendentaion for other VP
+register accesses in omap_vp_init().
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 2 +-
+ arch/arm/mach-omap2/voltage.c | 2 +-
+ arch/arm/mach-omap2/vp.c | 29 ++++++++++++++---------------
+ arch/arm/mach-omap2/vp.h | 34 ++++++++++++++--------------------
+ arch/arm/mach-omap2/vp3xxx_data.c | 4 +---
+ arch/arm/mach-omap2/vp44xx_data.c | 4 +---
+ 6 files changed, 32 insertions(+), 43 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 7058585..f64c826 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -140,7 +140,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+ vp_errgain_val &= voltdm->vp->common->vpconfig_errorgain_mask;
+ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+- voltdm->vp->common->vpconfig_errorgain_shift;
++ __ffs(voltdm->vp->common->vpconfig_errorgain_mask);
+ voltdm->write(vp_errgain_val, voltdm->vp->vpconfig);
+ }
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index eaa5f93..5b16fd1 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -82,7 +82,7 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+
+ vdd->vp_rt_data.vpconfig_erroroffset =
+ (voltdm->pmic->vp_erroroffset <<
+- voltdm->vp->common->vpconfig_erroroffset_shift);
++ __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
+
+ timeout_val = (sys_clk_speed * voltdm->pmic->vp_timeout_us) / 1000;
+ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index c9a315f..297d094 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -34,8 +34,7 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
+ vp->common->vpconfig_initvdd);
+- vpconfig |= vsel << vp->common->vpconfig_initvoltage_shift;
+-
++ vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask);
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+@@ -61,28 +60,28 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+
+ vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+ (vdd->vp_rt_data.vpconfig_errorgain <<
+- vp->common->vpconfig_errorgain_shift) |
++ __ffs(vp->common->vpconfig_errorgain_mask)) |
+ vp->common->vpconfig_timeouten;
+ voltdm->write(vp_val, vp->vpconfig);
+
+ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+- vp->common->vstepmin_smpswaittimemin_shift) |
+- (vdd->vp_rt_data.vstepmin_stepmin <<
+- vp->common->vstepmin_stepmin_shift));
++ vp->common->vstepmin_smpswaittimemin_shift) |
++ (vdd->vp_rt_data.vstepmin_stepmin <<
++ vp->common->vstepmin_stepmin_shift));
+ voltdm->write(vp_val, vp->vstepmin);
+
+ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+- vp->common->vstepmax_smpswaittimemax_shift) |
+- (vdd->vp_rt_data.vstepmax_stepmax <<
+- vp->common->vstepmax_stepmax_shift));
++ vp->common->vstepmax_smpswaittimemax_shift) |
++ (vdd->vp_rt_data.vstepmax_stepmax <<
++ vp->common->vstepmax_stepmax_shift));
+ voltdm->write(vp_val, vp->vstepmax);
+
+ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+- vp->common->vlimitto_vddmax_shift) |
+- (vdd->vp_rt_data.vlimitto_vddmin <<
+- vp->common->vlimitto_vddmin_shift) |
+- (vdd->vp_rt_data.vlimitto_timeout <<
+- vp->common->vlimitto_timeout_shift));
++ vp->common->vlimitto_vddmax_shift) |
++ (vdd->vp_rt_data.vlimitto_vddmin <<
++ vp->common->vlimitto_vddmin_shift) |
++ (vdd->vp_rt_data.vlimitto_timeout <<
++ vp->common->vlimitto_timeout_shift));
+ voltdm->write(vp_val, vp->vlimitto);
+ }
+
+@@ -121,7 +120,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ vp->common->vpconfig_forceupdate |
+ vp->common->vpconfig_initvoltage_mask);
+ vpconfig |= ((target_vsel <<
+- vp->common->vpconfig_initvoltage_shift));
++ __ffs(vp->common->vpconfig_initvoltage_mask)));
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 1d63960..2afe11d 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -46,37 +46,32 @@ struct omap_vp_ops {
+
+ /**
+ * struct omap_vp_common - register data common to all VDDs
++ * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
+- * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
+ * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
+ * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
+ * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
+- * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
+- * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
+- * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
+- * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
+- * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+- * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+- * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+- *
+- * XXX It it not necessary to have both a mask and a shift for the same
+- * bitfield - remove one
+- * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
++ * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
++ * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
++ * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
++ * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
++ * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
++ * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
++ * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+ */
+ struct omap_vp_common {
++ u32 vpconfig_erroroffset_mask;
+ u32 vpconfig_errorgain_mask;
+ u32 vpconfig_initvoltage_mask;
+- u32 vpconfig_timeouten;
+- u32 vpconfig_initvdd;
+- u32 vpconfig_forceupdate;
+- u32 vpconfig_vpenable;
+- u8 vpconfig_erroroffset_shift;
+- u8 vpconfig_errorgain_shift;
+- u8 vpconfig_initvoltage_shift;
++ u8 vpconfig_timeouten;
++ u8 vpconfig_initvdd;
++ u8 vpconfig_forceupdate;
++ u8 vpconfig_vpenable;
+ u8 vstepmin_stepmin_shift;
+ u8 vstepmin_smpswaittimemin_shift;
+ u8 vstepmax_stepmax_shift;
+@@ -127,7 +122,6 @@ struct omap_vp_instance {
+ * XXX Is this structure really needed? Why not just program the
+ * device directly? They are in PRM space, therefore in the WKUP
+ * powerdomain, so register contents should not be lost in off-mode.
+- * XXX Some of these fields are incorrectly named, e.g., vstep*
+ */
+ struct omap_vp_runtime_data {
+ u32 vpconfig_erroroffset;
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index 79c3df9..d429c44 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -37,10 +37,8 @@ static const struct omap_vp_ops omap3_vp_ops = {
+ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ */
+ static const struct omap_vp_common omap3_vp_common = {
+- .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
++ .vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK,
+ .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+- .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
+- .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT,
+ .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
+ .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
+ .vpconfig_initvdd = OMAP3430_INITVDD_MASK,
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 8f75cd9..0daf2a4 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -37,10 +37,8 @@ static const struct omap_vp_ops omap4_vp_ops = {
+ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
+ */
+ static const struct omap_vp_common omap4_vp_common = {
+- .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
++ .vpconfig_erroroffset_mask = OMAP4430_ERROROFFSET_MASK,
+ .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
+- .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
+- .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT,
+ .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK,
+ .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK,
+ .vpconfig_initvdd = OMAP4430_INITVDD_MASK,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0131-OMAP3-VP-move-SoC-specific-sys-clock-rate-retreival-.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0131-OMAP3-VP-move-SoC-specific-sys-clock-rate-retreival-.patch
--- /dev/null
@@ -0,0 +1,184 @@
+From 91f25e4b8af672077efbd1de8139ef724fdb1ffe Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 4 Apr 2011 17:22:28 -0700
+Subject: [PATCH 131/149] OMAP3+: VP: move SoC-specific sys clock rate retreival late init
+
+Add sys clock name and rate to struct voltage domain. SoC specific
+voltagedomain init code initializes sys clock name. After clock
+framework is initialized, voltage late init will then use use the
+sys_clk rate to calculate the various timing that depend on that rate.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 47 +++++++++----------------
+ arch/arm/mach-omap2/voltage.h | 5 +++
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 8 ++++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 8 ++++
+ 4 files changed, 38 insertions(+), 30 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 5b16fd1..533ea38 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -21,10 +21,10 @@
+
+ #include <linux/delay.h>
+ #include <linux/io.h>
+-#include <linux/clk.h>
+ #include <linux/err.h>
+ #include <linux/debugfs.h>
+ #include <linux/slab.h>
++#include <linux/clk.h>
+
+ #include <plat/common.h>
+
+@@ -45,36 +45,12 @@ static LIST_HEAD(voltdm_list);
+
+ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+- char *sys_ck_name;
+- struct clk *sys_ck;
+- u32 sys_clk_speed, timeout_val, waittime;
+ struct omap_vdd_info *vdd = voltdm->vdd;
++ u32 sys_clk_rate, timeout_val, waittime;
+
+- /*
+- * XXX Clockfw should handle this, or this should be in a
+- * struct record
+- */
+- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+- sys_ck_name = "sys_ck";
+- else if (cpu_is_omap44xx())
+- sys_ck_name = "sys_clkin_ck";
+- else
+- return -EINVAL;
+-
+- /*
+- * Sys clk rate is require to calculate vp timeout value and
+- * smpswaittimemin and smpswaittimemax.
+- */
+- sys_ck = clk_get(NULL, sys_ck_name);
+- if (IS_ERR(sys_ck)) {
+- pr_warning("%s: Could not get the sys clk to calculate"
+- "various vdd_%s params\n", __func__, voltdm->name);
+- return -EINVAL;
+- }
+- sys_clk_speed = clk_get_rate(sys_ck);
+- clk_put(sys_ck);
+ /* Divide to avoid overflow */
+- sys_clk_speed /= 1000;
++ sys_clk_rate = voltdm->sys_clk.rate / 1000;
++ WARN_ON(!sys_clk_rate);
+
+ /* Generic voltage parameters */
+ vdd->volt_scale = omap_vp_forceupdate_scale;
+@@ -84,13 +60,13 @@ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ (voltdm->pmic->vp_erroroffset <<
+ __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
+
+- timeout_val = (sys_clk_speed * voltdm->pmic->vp_timeout_us) / 1000;
++ timeout_val = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
+ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+ vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
+ vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
+
+ waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+- sys_clk_speed) / 1000;
++ sys_clk_rate) / 1000;
+ vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
+ vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
+ vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
+@@ -346,9 +322,20 @@ int __init omap_voltage_late_init(void)
+ }
+
+ list_for_each_entry(voltdm, &voltdm_list, node) {
++ struct clk *sys_ck;
++
+ if (!voltdm->scalable)
+ continue;
+
++ sys_ck = clk_get(NULL, voltdm->sys_clk.name);
++ if (IS_ERR(sys_ck)) {
++ pr_warning("%s: Could not get sys clk.\n", __func__);
++ return -EINVAL;
++ }
++ voltdm->sys_clk.rate = clk_get_rate(sys_ck);
++ WARN_ON(!voltdm->sys_clk.rate);
++ clk_put(sys_ck);
++
+ if (voltdm->vc) {
+ voltdm->vdd->volt_scale = omap_vc_bypass_scale;
+ omap_vc_init_channel(voltdm);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 5261703..d73c956 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -76,6 +76,11 @@ struct voltagedomain {
+ void (*write) (u32 val, u8 offset);
+ u32 (*rmw)(u32 mask, u32 bits, u8 offset);
+
++ union {
++ const char *name;
++ u32 rate;
++ } sys_clk;
++
+ struct omap_vdd_info *vdd;
+ };
+
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index 4db2c6c..e7a0be1 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -82,8 +82,13 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = {
+ NULL,
+ };
+
++static const char *sys_clk_name __initdata = "sys_ck";
++
+ void __init omap3xxx_voltagedomains_init(void)
+ {
++ struct voltagedomain *voltdm;
++ int i;
++
+ /*
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC
+@@ -96,5 +101,8 @@ void __init omap3xxx_voltagedomains_init(void)
+ omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
+ }
+
++ for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
++ voltdm->sys_clk.name = sys_clk_name;
++
+ voltdm_init(voltagedomains_omap3);
+ };
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 3e7cb4e..9c20fbb 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -98,8 +98,13 @@ static struct voltagedomain *voltagedomains_omap4[] __initdata = {
+ NULL,
+ };
+
++static const char *sys_clk_name __initdata = "sys_clkin_ck";
++
+ void __init omap44xx_voltagedomains_init(void)
+ {
++ struct voltagedomain *voltdm;
++ int i;
++
+ /*
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC
+@@ -108,5 +113,8 @@ void __init omap44xx_voltagedomains_init(void)
+ omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+ omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
+
++ for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
++ voltdm->sys_clk.name = sys_clk_name;
++
+ voltdm_init(voltagedomains_omap4);
+ };
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0132-OMAP3-VP-move-timing-calculation-config-into-VP-init.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0132-OMAP3-VP-move-timing-calculation-config-into-VP-init.patch
--- /dev/null
@@ -0,0 +1,94 @@
+From 2d8b759e4227eb14bcb64fc007ea839a65d6fce6 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Thu, 14 Jul 2011 11:10:27 -0700
+Subject: [PATCH 132/149] OMAP3+: VP: move timing calculation/config into VP init
+
+Move VP timing calcluation (based on sys clock) and register programming
+into VP init.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 22 ----------------------
+ arch/arm/mach-omap2/vp.c | 23 ++++++++++++++++++++++-
+ 2 files changed, 22 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 533ea38..4a15668 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -46,31 +46,9 @@ static LIST_HEAD(voltdm_list);
+ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+ struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 sys_clk_rate, timeout_val, waittime;
+-
+- /* Divide to avoid overflow */
+- sys_clk_rate = voltdm->sys_clk.rate / 1000;
+- WARN_ON(!sys_clk_rate);
+
+ /* Generic voltage parameters */
+ vdd->volt_scale = omap_vp_forceupdate_scale;
+- voltdm->vp->enabled = false;
+-
+- vdd->vp_rt_data.vpconfig_erroroffset =
+- (voltdm->pmic->vp_erroroffset <<
+- __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
+-
+- timeout_val = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
+- vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+- vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
+- vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
+-
+- waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+- sys_clk_rate) / 1000;
+- vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
+- vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
+- vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
+- vdd->vp_rt_data.vstepmax_stepmax = voltdm->pmic->vp_vstepmax;
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 297d094..ea61a47 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -50,7 +50,7 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ {
+ struct omap_vp_instance *vp = voltdm->vp;
+ struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vp_val;
++ u32 vp_val, sys_clk_rate, timeout_val, waittime;
+
+ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+@@ -58,6 +58,27 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ return;
+ }
+
++ vp->enabled = false;
++
++ /* Divide to avoid overflow */
++ sys_clk_rate = voltdm->sys_clk.rate / 1000;
++
++ vdd->vp_rt_data.vpconfig_erroroffset =
++ (voltdm->pmic->vp_erroroffset <<
++ __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
++
++ timeout_val = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
++ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
++ vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
++ vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
++
++ waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
++ sys_clk_rate) / 1000;
++ vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
++ vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
++ vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
++ vdd->vp_rt_data.vstepmax_stepmax = voltdm->pmic->vp_vstepmax;
++
+ vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+ (vdd->vp_rt_data.vpconfig_errorgain <<
+ __ffs(vp->common->vpconfig_errorgain_mask)) |
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0133-OMAP3-VP-create-VP-helper-function-for-updating-erro.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0133-OMAP3-VP-create-VP-helper-function-for-updating-erro.patch
--- /dev/null
@@ -0,0 +1,107 @@
+From 9e164a895c4fe22bc673c07ff159bcc183baed6b Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 5 Apr 2011 15:15:31 -0700
+Subject: [PATCH 133/149] OMAP3+: VP: create VP helper function for updating error gain
+
+Create new helper function in VP layer for updating VP error gain.
+Currently used during pre-scale for VP force update and VC bypass.
+
+TODO: determine if this can be removed from the pre-scale path and
+moved to VP enable path.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 19 ++-----------------
+ arch/arm/mach-omap2/vp.c | 19 +++++++++++++++++++
+ arch/arm/mach-omap2/vp.h | 2 ++
+ 3 files changed, 23 insertions(+), 17 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index f64c826..e855559 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -96,9 +96,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ u8 *target_vsel, u8 *current_vsel)
+ {
+ struct omap_vc_channel *vc = voltdm->vc;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- struct omap_volt_data *volt_data;
+- u32 vc_cmdval, vp_errgain_val;
++ u32 vc_cmdval;
+
+ /* Check if sufficient pmic info is available for this vdd */
+ if (!voltdm->pmic) {
+@@ -120,11 +118,6 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ return -EINVAL;
+ }
+
+- /* Get volt_data corresponding to target_volt */
+- volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+- if (IS_ERR(volt_data))
+- volt_data = NULL;
+-
+ *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+ *current_vsel = voltdm->pmic->uv_to_vsel(vdd->curr_volt);
+
+@@ -134,15 +127,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
+ voltdm->write(vc_cmdval, vc->cmdval_reg);
+
+- /* Setting vp errorgain based on the voltage */
+- if (volt_data) {
+- vp_errgain_val = voltdm->read(voltdm->vp->vpconfig);
+- vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
+- vp_errgain_val &= voltdm->vp->common->vpconfig_errorgain_mask;
+- vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
+- __ffs(voltdm->vp->common->vpconfig_errorgain_mask);
+- voltdm->write(vp_errgain_val, voltdm->vp->vpconfig);
+- }
++ omap_vp_update_errorgain(voltdm, target_volt);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index ea61a47..f68a6db 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -106,6 +106,25 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ voltdm->write(vp_val, vp->vlimitto);
+ }
+
++int omap_vp_update_errorgain(struct voltagedomain *voltdm,
++ unsigned long target_volt)
++{
++ struct omap_volt_data *volt_data;
++
++ /* Get volt_data corresponding to target_volt */
++ volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
++ if (IS_ERR(volt_data))
++ return -EINVAL;
++
++ /* Setting vp errorgain based on the voltage */
++ voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask,
++ volt_data->vp_errgain <<
++ __ffs(voltdm->vp->common->vpconfig_errorgain_mask),
++ voltdm->vp->vpconfig);
++
++ return 0;
++}
++
+ /* VP force update method of voltage scaling */
+ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 2afe11d..71ac738 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -148,5 +148,7 @@ void omap_vp_disable(struct voltagedomain *voltdm);
+ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt);
++int omap_vp_update_errorgain(struct voltagedomain *voltdm,
++ unsigned long target_volt);
+
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0134-OMAP3-VP-remove-omap_vp_runtime_data.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0134-OMAP3-VP-remove-omap_vp_runtime_data.patch
--- /dev/null
@@ -0,0 +1,170 @@
+From fbcfff727913c1cb9b608194f420d84b05b31b8f Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 4 Apr 2011 17:58:21 -0700
+Subject: [PATCH 134/149] OMAP3+: VP: remove omap_vp_runtime_data
+
+Remove the "runtime" VP data in favor of direct programming of VP registers.
+The VP is in the PRM, which is in the wakeup powerdomain, so there is no
+need to keep the state dynamically.
+
+Fixes to original version from Nishanth Menon <nm@ti.com>
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.h | 2 -
+ arch/arm/mach-omap2/vp.c | 70 ++++++++++++++++++-----------------------
+ arch/arm/mach-omap2/vp.h | 28 ----------------
+ 3 files changed, 31 insertions(+), 69 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index d73c956..5235eec 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -140,13 +140,11 @@ struct omap_voltdm_pmic {
+ *
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+- * @vp_rt_data : VP data derived at runtime, not predefined
+ * @curr_volt : current voltage for this vdd.
+ * @volt_scale : API to scale the voltage of the vdd.
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+- struct omap_vp_runtime_data vp_rt_data;
+ u32 curr_volt;
+
+ int (*volt_scale) (struct voltagedomain *voltdm,
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index f68a6db..e7d38f6 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -49,8 +49,8 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+ void __init omap_vp_init(struct voltagedomain *voltdm)
+ {
+ struct omap_vp_instance *vp = voltdm->vp;
+- struct omap_vdd_info *vdd = voltdm->vdd;
+- u32 vp_val, sys_clk_rate, timeout_val, waittime;
++ u32 val, sys_clk_rate, timeout, waittime;
++ u32 vddmin, vddmax, vstepmin, vstepmax;
+
+ if (!voltdm->read || !voltdm->write) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+@@ -63,47 +63,39 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
+ /* Divide to avoid overflow */
+ sys_clk_rate = voltdm->sys_clk.rate / 1000;
+
+- vdd->vp_rt_data.vpconfig_erroroffset =
+- (voltdm->pmic->vp_erroroffset <<
+- __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
+-
+- timeout_val = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
+- vdd->vp_rt_data.vlimitto_timeout = timeout_val;
+- vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
+- vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
++ timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
++ vddmin = voltdm->pmic->vp_vddmin;
++ vddmax = voltdm->pmic->vp_vddmax;
+
+ waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+ sys_clk_rate) / 1000;
+- vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
+- vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
+- vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
+- vdd->vp_rt_data.vstepmax_stepmax = voltdm->pmic->vp_vstepmax;
+-
+- vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
+- (vdd->vp_rt_data.vpconfig_errorgain <<
+- __ffs(vp->common->vpconfig_errorgain_mask)) |
++ vstepmin = voltdm->pmic->vp_vstepmin;
++ vstepmax = voltdm->pmic->vp_vstepmax;
++
++ /*
++ * VP_CONFIG: error gain is not set here, it will be updated
++ * on each scale, based on OPP.
++ */
++ val = (voltdm->pmic->vp_erroroffset <<
++ __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) |
+ vp->common->vpconfig_timeouten;
+- voltdm->write(vp_val, vp->vpconfig);
+-
+- vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
+- vp->common->vstepmin_smpswaittimemin_shift) |
+- (vdd->vp_rt_data.vstepmin_stepmin <<
+- vp->common->vstepmin_stepmin_shift));
+- voltdm->write(vp_val, vp->vstepmin);
+-
+- vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
+- vp->common->vstepmax_smpswaittimemax_shift) |
+- (vdd->vp_rt_data.vstepmax_stepmax <<
+- vp->common->vstepmax_stepmax_shift));
+- voltdm->write(vp_val, vp->vstepmax);
+-
+- vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
+- vp->common->vlimitto_vddmax_shift) |
+- (vdd->vp_rt_data.vlimitto_vddmin <<
+- vp->common->vlimitto_vddmin_shift) |
+- (vdd->vp_rt_data.vlimitto_timeout <<
+- vp->common->vlimitto_timeout_shift));
+- voltdm->write(vp_val, vp->vlimitto);
++ voltdm->write(val, vp->vpconfig);
++
++ /* VSTEPMIN */
++ val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) |
++ (vstepmin << vp->common->vstepmin_stepmin_shift);
++ voltdm->write(val, vp->vstepmin);
++
++ /* VSTEPMAX */
++ val = (vstepmax << vp->common->vstepmax_stepmax_shift) |
++ (waittime << vp->common->vstepmax_smpswaittimemax_shift);
++ voltdm->write(val, vp->vstepmax);
++
++ /* VLIMITTO */
++ val = (vddmax << vp->common->vlimitto_vddmax_shift) |
++ (vddmin << vp->common->vlimitto_vddmin_shift) |
++ (timeout << vp->common->vlimitto_timeout_shift);
++ voltdm->write(val, vp->vlimitto);
+ }
+
+ int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 71ac738..0d63267 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -107,34 +107,6 @@ struct omap_vp_instance {
+ bool enabled;
+ };
+
+-/**
+- * struct omap_vp_runtime_data - VP data populated at runtime by code
+- * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG
+- * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG
+- * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN
+- * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX
+- * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO
+- * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN
+- * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX
+- * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO
+- * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO
+- *
+- * XXX Is this structure really needed? Why not just program the
+- * device directly? They are in PRM space, therefore in the WKUP
+- * powerdomain, so register contents should not be lost in off-mode.
+- */
+-struct omap_vp_runtime_data {
+- u32 vpconfig_erroroffset;
+- u16 vpconfig_errorgain;
+- u16 vstepmin_smpswaittimemin;
+- u16 vstepmax_smpswaittimemax;
+- u16 vlimitto_timeout;
+- u8 vstepmin_stepmin;
+- u8 vstepmax_stepmax;
+- u8 vlimitto_vddmin;
+- u8 vlimitto_vddmax;
+-};
+-
+ extern struct omap_vp_instance omap3_vp_mpu;
+ extern struct omap_vp_instance omap3_vp_core;
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0135-OMAP3-VP-move-voltage-scale-function-pointer-into-st.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0135-OMAP3-VP-move-voltage-scale-function-pointer-into-st.patch
--- /dev/null
@@ -0,0 +1,134 @@
+From b91ae2bfe2177464968d9d976008738fff308468 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Thu, 14 Jul 2011 11:12:32 -0700
+Subject: [PATCH 135/149] OMAP3+: VP: move voltage scale function pointer into struct voltagedomain
+
+Function pointer used for actual voltage scaling (e.g. VP force update
+or VC bypass) is moved from omap_vdd_info into struct voltagedomain,
+resulting in renames s/vdd->volt_scale/voltdm->scale/
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 24 +++++++-----------------
+ arch/arm/mach-omap2/voltage.h | 8 ++++----
+ 2 files changed, 11 insertions(+), 21 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 4a15668..32f0873 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -45,10 +45,8 @@ static LIST_HEAD(voltdm_list);
+
+ static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+ {
+- struct omap_vdd_info *vdd = voltdm->vdd;
+-
+ /* Generic voltage parameters */
+- vdd->volt_scale = omap_vp_forceupdate_scale;
++ voltdm->scale = omap_vp_forceupdate_scale;
+
+ return 0;
+ }
+@@ -107,22 +105,18 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
+- struct omap_vdd_info *vdd;
+-
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return -EINVAL;
+ }
+
+- vdd = voltdm->vdd;
+-
+- if (!vdd->volt_scale) {
++ if (!voltdm->scale) {
+ pr_err("%s: No voltage scale API registered for vdd_%s\n",
+ __func__, voltdm->name);
+ return -ENODATA;
+ }
+
+- return vdd->volt_scale(voltdm, target_volt);
++ return voltdm->scale(voltdm, target_volt);
+ }
+
+ /**
+@@ -258,23 +252,19 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ * defined in voltage.h
+ */
+ void omap_change_voltscale_method(struct voltagedomain *voltdm,
+- int voltscale_method)
++ int voltscale_method)
+ {
+- struct omap_vdd_info *vdd;
+-
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return;
+ }
+
+- vdd = voltdm->vdd;
+-
+ switch (voltscale_method) {
+ case VOLTSCALE_VPFORCEUPDATE:
+- vdd->volt_scale = omap_vp_forceupdate_scale;
++ voltdm->scale = omap_vp_forceupdate_scale;
+ return;
+ case VOLTSCALE_VCBYPASS:
+- vdd->volt_scale = omap_vc_bypass_scale;
++ voltdm->scale = omap_vc_bypass_scale;
+ return;
+ default:
+ pr_warning("%s: Trying to change the method of voltage scaling"
+@@ -315,7 +305,7 @@ int __init omap_voltage_late_init(void)
+ clk_put(sys_ck);
+
+ if (voltdm->vc) {
+- voltdm->vdd->volt_scale = omap_vc_bypass_scale;
++ voltdm->scale = omap_vc_bypass_scale;
+ omap_vc_init_channel(voltdm);
+ }
+
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 5235eec..d2a0c24 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -60,6 +60,7 @@ struct omap_vfsm_instance {
+ * @pwrdm_node: list_head linking all powerdomains in this voltagedomain
+ * @vdd: to be removed
+ * @pwrdms: powerdomains in this voltagedomain
++ * @scale: function used to scale the voltage of the voltagedomain
+ */
+ struct voltagedomain {
+ char *name;
+@@ -81,6 +82,9 @@ struct voltagedomain {
+ u32 rate;
+ } sys_clk;
+
++ int (*scale) (struct voltagedomain *voltdm,
++ unsigned long target_volt);
++
+ struct omap_vdd_info *vdd;
+ };
+
+@@ -141,14 +145,10 @@ struct omap_voltdm_pmic {
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+ * @curr_volt : current voltage for this vdd.
+- * @volt_scale : API to scale the voltage of the vdd.
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+ u32 curr_volt;
+-
+- int (*volt_scale) (struct voltagedomain *voltdm,
+- unsigned long target_volt);
+ };
+
+ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0136-OMAP-VP-Explicitly-mask-VPVOLTAGE-field.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0136-OMAP-VP-Explicitly-mask-VPVOLTAGE-field.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0136-OMAP-VP-Explicitly-mask-VPVOLTAGE-field.patch
@@ -0,0 +1,81 @@
+From 47267ed5c167cb77aa518cfef0d4e9d5664e62b0 Mon Sep 17 00:00:00 2001
+From: Todd Poynor <toddpoynor@google.com>
+Date: Fri, 27 May 2011 19:15:59 -0700
+Subject: [PATCH 136/149] OMAP: VP: Explicitly mask VPVOLTAGE field
+
+Reading the VPVOLTAGE field of PRM_VP_*_VOLTAGE registers currently
+relies on a u32 -> u8 conversion to mask off the FORCEUPDATEWAIT field
+in the upper bits. Make this explicit using the mask symbol
+already defined, added as a new field in struct omap_vp_common.
+
+Signed-off-by: Todd Poynor <toddpoynor@google.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vp.c | 3 ++-
+ arch/arm/mach-omap2/vp.h | 2 ++
+ arch/arm/mach-omap2/vp3xxx_data.c | 2 ++
+ arch/arm/mach-omap2/vp44xx_data.c | 1 +
+ 4 files changed, 7 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index e7d38f6..3807620 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -227,7 +227,8 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- curr_vsel = voltdm->read(vp->voltage);
++ curr_vsel = (voltdm->read(vp->voltage) & vp->common->vpvoltage_mask)
++ >> __ffs(vp->common->vpvoltage_mask);
+
+ if (!voltdm->pmic || !voltdm->pmic->vsel_to_uv) {
+ pr_warning("%s: PMIC function to convert vsel to voltage"
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index 0d63267..f78752b 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -63,6 +63,7 @@ struct omap_vp_ops {
+ * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
++ * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg
+ */
+ struct omap_vp_common {
+ u32 vpconfig_erroroffset_mask;
+@@ -79,6 +80,7 @@ struct omap_vp_common {
+ u8 vlimitto_vddmin_shift;
+ u8 vlimitto_vddmax_shift;
+ u8 vlimitto_timeout_shift;
++ u8 vpvoltage_mask;
+
+ const struct omap_vp_ops *ops;
+ };
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+index d429c44..260c554 100644
+--- a/arch/arm/mach-omap2/vp3xxx_data.c
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -51,6 +51,8 @@ static const struct omap_vp_common omap3_vp_common = {
+ .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
+ .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
+ .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
++ .vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK,
++
+ .ops = &omap3_vp_ops,
+ };
+
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+index 0daf2a4..b4e7704 100644
+--- a/arch/arm/mach-omap2/vp44xx_data.c
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -51,6 +51,7 @@ static const struct omap_vp_common omap4_vp_common = {
+ .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
+ .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
+ .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
++ .vpvoltage_mask = OMAP4430_VPVOLTAGE_MASK,
+ .ops = &omap4_vp_ops,
+ };
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0137-OMAP3-VP-update_errorgain-return-error-if-VP.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0137-OMAP3-VP-update_errorgain-return-error-if-VP.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0137-OMAP3-VP-update_errorgain-return-error-if-VP.patch
@@ -0,0 +1,29 @@
+From 66f119ca57948dd32bd7695cbbdb00e27843fccf Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 18 Jul 2011 15:31:43 -0700
+Subject: [PATCH 137/149] OMAP3+: VP: update_errorgain(): return error if VP
+
+Add check for valid VP in omap_vp_update_errorgain()
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vp.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 3807620..29698ac 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -103,6 +103,9 @@ int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+ {
+ struct omap_volt_data *volt_data;
+
++ if (!voltdm->vp)
++ return -EINVAL;
++
+ /* Get volt_data corresponding to target_volt */
+ volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+ if (IS_ERR(volt_data))
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0138-OMAP3-VP-remove-unused-omap_vp_get_curr_volt.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0138-OMAP3-VP-remove-unused-omap_vp_get_curr_volt.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0138-OMAP3-VP-remove-unused-omap_vp_get_curr_volt.patch
@@ -0,0 +1,70 @@
+From fcafc153449076c385deb5c90ea47396b8bd6499 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Fri, 15 Jul 2011 16:38:10 -0700
+Subject: [PATCH 138/149] OMAP3+: VP: remove unused omap_vp_get_curr_volt()
+
+---
+ arch/arm/mach-omap2/vp.c | 34 ----------------------------------
+ arch/arm/mach-omap2/vp.h | 1 -
+ 2 files changed, 0 insertions(+), 35 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 29698ac..24020ea 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -209,40 +209,6 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ }
+
+ /**
+- * omap_vp_get_curr_volt() - API to get the current vp voltage.
+- * @voltdm: pointer to the VDD.
+- *
+- * This API returns the current voltage for the specified voltage processor
+- */
+-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+-{
+- struct omap_vp_instance *vp = voltdm->vp;
+- u8 curr_vsel;
+-
+- if (!voltdm || IS_ERR(voltdm)) {
+- pr_warning("%s: VDD specified does not exist!\n", __func__);
+- return 0;
+- }
+-
+- if (!voltdm->read) {
+- pr_err("%s: No read API for reading vdd_%s regs\n",
+- __func__, voltdm->name);
+- return 0;
+- }
+-
+- curr_vsel = (voltdm->read(vp->voltage) & vp->common->vpvoltage_mask)
+- >> __ffs(vp->common->vpvoltage_mask);
+-
+- if (!voltdm->pmic || !voltdm->pmic->vsel_to_uv) {
+- pr_warning("%s: PMIC function to convert vsel to voltage"
+- "in uV not registerd\n", __func__);
+- return 0;
+- }
+-
+- return voltdm->pmic->vsel_to_uv(curr_vsel);
+-}
+-
+-/**
+ * omap_vp_enable() - API to enable a particular VP
+ * @voltdm: pointer to the VDD whose VP is to be enabled.
+ *
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+index f78752b..d9bc4f1 100644
+--- a/arch/arm/mach-omap2/vp.h
++++ b/arch/arm/mach-omap2/vp.h
+@@ -119,7 +119,6 @@ extern struct omap_vp_instance omap4_vp_core;
+ void omap_vp_init(struct voltagedomain *voltdm);
+ void omap_vp_enable(struct voltagedomain *voltdm);
+ void omap_vp_disable(struct voltagedomain *voltdm);
+-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt);
+ int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0139-OMAP3-VP-combine-setting-init-voltage-into-common-fu.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0139-OMAP3-VP-combine-setting-init-voltage-into-common-fu.patch
--- /dev/null
@@ -0,0 +1,141 @@
+From e5dfd3df7ec0e820767b65dd730c85b4c86dac10 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Fri, 15 Jul 2011 17:05:48 -0700
+Subject: [PATCH 139/149] OMAP3+: VP: combine setting init voltage into common function
+
+combine VPCONFIG init voltage setup into common function and use from
+both vp_enable and from vp_forceupdate_scale().
+
+NOTE: this patch changes the sequence of when the initVDD bit is
+cleared. The bit is now cleared immediately after it was written.
+Since only the rising edge of this bit has any affect according to the
+TRM, the exact timing of clearing of this bit should not have any
+effect.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vp.c | 58 +++++++++++++++-------------------------------
+ 1 files changed, 19 insertions(+), 39 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
+index 24020ea..66bd700 100644
+--- a/arch/arm/mach-omap2/vp.c
++++ b/arch/arm/mach-omap2/vp.c
+@@ -9,31 +9,18 @@
+ #include "prm-regbits-44xx.h"
+ #include "prm44xx.h"
+
+-static void vp_latch_vsel(struct voltagedomain *voltdm)
++static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt)
+ {
+ struct omap_vp_instance *vp = voltdm->vp;
+ u32 vpconfig;
+- unsigned long uvdc;
+ char vsel;
+
+- uvdc = omap_voltage_get_nom_volt(voltdm);
+- if (!uvdc) {
+- pr_warning("%s: unable to find current voltage for vdd_%s\n",
+- __func__, voltdm->name);
+- return;
+- }
+-
+- if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+- pr_warning("%s: PMIC function to convert voltage in uV to"
+- " vsel not registered\n", __func__);
+- return;
+- }
+-
+- vsel = voltdm->pmic->uv_to_vsel(uvdc);
++ vsel = voltdm->pmic->uv_to_vsel(volt);
+
+ vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
+- vp->common->vpconfig_initvdd);
++ vp->common->vpconfig_forceupdate |
++ vp->common->vpconfig_initvdd);
+ vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask);
+ voltdm->write(vpconfig, vp->vpconfig);
+
+@@ -43,6 +30,8 @@ static void vp_latch_vsel(struct voltagedomain *voltdm)
+
+ /* Clear initVDD copy trigger bit */
+ voltdm->write(vpconfig, vp->vpconfig);
++
++ return vpconfig;
+ }
+
+ /* Generic voltage init functions */
+@@ -149,22 +138,11 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ return -ETIMEDOUT;
+ }
+
+- /* Configure for VP-Force Update */
+- vpconfig = voltdm->read(vp->vpconfig);
+- vpconfig &= ~(vp->common->vpconfig_initvdd |
+- vp->common->vpconfig_forceupdate |
+- vp->common->vpconfig_initvoltage_mask);
+- vpconfig |= ((target_vsel <<
+- __ffs(vp->common->vpconfig_initvoltage_mask)));
+- voltdm->write(vpconfig, vp->vpconfig);
+-
+- /* Trigger initVDD value copy to voltage processor */
+- vpconfig |= vp->common->vpconfig_initvdd;
+- voltdm->write(vpconfig, vp->vpconfig);
++ vpconfig = _vp_set_init_voltage(voltdm, target_volt);
+
+ /* Force update of voltage */
+- vpconfig |= vp->common->vpconfig_forceupdate;
+- voltdm->write(vpconfig, vp->vpconfig);
++ voltdm->write(vpconfig | vp->common->vpconfig_forceupdate,
++ voltdm->vp->vpconfig);
+
+ /*
+ * Wait for TransactionDone. Typical latency is <200us.
+@@ -197,12 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ "to clear the TRANXDONE status\n",
+ __func__, voltdm->name);
+
+- vpconfig = voltdm->read(vp->vpconfig);
+- /* Clear initVDD copy trigger bit */
+- vpconfig &= ~vp->common->vpconfig_initvdd;
+- voltdm->write(vpconfig, vp->vpconfig);
+ /* Clear force bit */
+- vpconfig &= ~vp->common->vpconfig_forceupdate;
+ voltdm->write(vpconfig, vp->vpconfig);
+
+ return 0;
+@@ -218,7 +191,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ void omap_vp_enable(struct voltagedomain *voltdm)
+ {
+ struct omap_vp_instance *vp;
+- u32 vpconfig;
++ u32 vpconfig, volt;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+@@ -236,12 +209,19 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ if (vp->enabled)
+ return;
+
+- vp_latch_vsel(voltdm);
++ volt = voltdm_get_voltage(voltdm);
++ if (!volt) {
++ pr_warning("%s: unable to find current voltage for %s\n",
++ __func__, voltdm->name);
++ return;
++ }
++
++ vpconfig = _vp_set_init_voltage(voltdm, volt);
+
+ /* Enable VP */
+- vpconfig = voltdm->read(vp->vpconfig);
+ vpconfig |= vp->common->vpconfig_vpenable;
+ voltdm->write(vpconfig, vp->vpconfig);
++
+ vp->enabled = true;
+ }
+
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0140-OMAP3-voltage-rename-scale-and-reset-functions-using.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0140-OMAP3-voltage-rename-scale-and-reset-functions-using.patch
--- /dev/null
@@ -0,0 +1,141 @@
+From 587c1fd832e3827f63ad03c18506c6024b148caa Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 5 Apr 2011 16:27:21 -0700
+Subject: [PATCH 140/149] OMAP3+: voltage: rename scale and reset functions using voltdm_ prefix
+
+Rename voltage scaling related functions to use voltdm_ prefix intead
+of omap_voltage_, and cleanup kerneldoc comments in the process.
+
+s/omap_voltage_scale_vdd/voltdm_scale/
+s/omap_voltage_reset/voltdm_reset/
+
+Also, in voltdm_reset() s/target_uvdc/target_volt/ to be consistent with
+naming throughout the file.
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/pm.c | 2 +-
+ arch/arm/mach-omap2/smartreflex-class3.c | 2 +-
+ arch/arm/mach-omap2/voltage.c | 29 ++++++++++++++---------------
+ arch/arm/mach-omap2/voltage.h | 5 ++---
+ 4 files changed, 18 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index f81340e..659e400 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -214,7 +214,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+ goto exit;
+ }
+
+- omap_voltage_scale_vdd(voltdm, bootup_volt);
++ voltdm_scale(voltdm, bootup_volt);
+ return 0;
+
+ exit:
+diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
+index f438cf4..4eac1bc 100644
+--- a/arch/arm/mach-omap2/smartreflex-class3.c
++++ b/arch/arm/mach-omap2/smartreflex-class3.c
+@@ -32,7 +32,7 @@ static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+ omap_vp_disable(voltdm);
+ sr_disable(voltdm);
+ if (is_volt_reset)
+- omap_voltage_reset(voltdm);
++ voltdm_reset(voltdm);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 32f0873..7588480 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -94,16 +94,15 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ }
+
+ /**
+- * omap_voltage_scale_vdd() - API to scale voltage of a particular
+- * voltage domain.
+- * @voltdm: pointer to the VDD which is to be scaled.
+- * @target_volt: The target voltage of the voltage domain
++ * voltdm_scale() - API to scale voltage of a particular voltage domain.
++ * @voltdm: pointer to the voltage domain which is to be scaled.
++ * @target_volt: The target voltage of the voltage domain
+ *
+ * This API should be called by the kernel to do the voltage scaling
+- * for a particular voltage domain during dvfs or any other situation.
++ * for a particular voltage domain during DVFS.
+ */
+-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+- unsigned long target_volt)
++int voltdm_scale(struct voltagedomain *voltdm,
++ unsigned long target_volt)
+ {
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+@@ -120,31 +119,31 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+ }
+
+ /**
+- * omap_voltage_reset() - Resets the voltage of a particular voltage domain
+- * to that of the current OPP.
+- * @voltdm: pointer to the VDD whose voltage is to be reset.
++ * voltdm_reset() - Resets the voltage of a particular voltage domain
++ * to that of the current OPP.
++ * @voltdm: pointer to the voltage domain whose voltage is to be reset.
+ *
+ * This API finds out the correct voltage the voltage domain is supposed
+ * to be at and resets the voltage to that level. Should be used especially
+ * while disabling any voltage compensation modules.
+ */
+-void omap_voltage_reset(struct voltagedomain *voltdm)
++void voltdm_reset(struct voltagedomain *voltdm)
+ {
+- unsigned long target_uvdc;
++ unsigned long target_volt;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return;
+ }
+
+- target_uvdc = omap_voltage_get_nom_volt(voltdm);
+- if (!target_uvdc) {
++ target_volt = omap_voltage_get_nom_volt(voltdm);
++ if (!target_volt) {
+ pr_err("%s: unable to find current voltage for vdd_%s\n",
+ __func__, voltdm->name);
+ return;
+ }
+
+- omap_voltage_scale_vdd(voltdm, target_uvdc);
++ voltdm_scale(voltdm, target_volt);
+ }
+
+ /**
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index d2a0c24..e3efbf9 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -151,9 +151,6 @@ struct omap_vdd_info {
+ u32 curr_volt;
+ };
+
+-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+- unsigned long target_volt);
+-void omap_voltage_reset(struct voltagedomain *voltdm);
+ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ struct omap_volt_data **volt_data);
+ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+@@ -191,4 +188,6 @@ int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
+ int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+ int (*fn)(struct voltagedomain *voltdm,
+ struct powerdomain *pwrdm));
++int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
++void voltdm_reset(struct voltagedomain *voltdm);
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0141-OMAP3-voltage-move-rename-curr_volt-from-vdd_info-in.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0141-OMAP3-voltage-move-rename-curr_volt-from-vdd_info-in.patch
--- /dev/null
@@ -0,0 +1,106 @@
+From 5e460dc12ee76039228f86aa9e23d8603fd909f1 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Tue, 5 Apr 2011 16:55:22 -0700
+Subject: [PATCH 141/149] OMAP3+: voltage: move/rename curr_volt from vdd_info into struct voltagedomain
+
+Track current nominal voltage as part of struct voltagedomain instead
+of omap_vdd_info, which will soon be removed.
+
+Also renames field from curr_volt to nominal_volt.
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 5 ++---
+ arch/arm/mach-omap2/voltage.c | 6 +-----
+ arch/arm/mach-omap2/voltage.h | 4 ++--
+ 3 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index e855559..3233c69 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -119,7 +119,7 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ }
+
+ *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+- *current_vsel = voltdm->pmic->uv_to_vsel(vdd->curr_volt);
++ *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
+
+ /* Setting the ON voltage to the new target voltage */
+ vc_cmdval = voltdm->read(vc->cmdval_reg);
+@@ -136,7 +136,6 @@ void omap_vc_post_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt,
+ u8 target_vsel, u8 current_vsel)
+ {
+- struct omap_vdd_info *vdd = voltdm->vdd;
+ u32 smps_steps = 0, smps_delay = 0;
+
+ smps_steps = abs(target_vsel - current_vsel);
+@@ -145,7 +144,7 @@ void omap_vc_post_scale(struct voltagedomain *voltdm,
+ voltdm->pmic->slew_rate) + 2;
+ udelay(smps_delay);
+
+- vdd->curr_volt = target_volt;
++ voltdm->nominal_volt = target_volt;
+ }
+
+ /* vc_bypass_scale - VC bypass method of voltage scaling */
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 7588480..29ab389 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -81,16 +81,12 @@ ovdc_out:
+ */
+ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ {
+- struct omap_vdd_info *vdd;
+-
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return 0;
+ }
+
+- vdd = voltdm->vdd;
+-
+- return vdd->curr_volt;
++ return voltdm->nominal_volt;
+ }
+
+ /**
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index e3efbf9..3e32eda 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -61,6 +61,7 @@ struct omap_vfsm_instance {
+ * @vdd: to be removed
+ * @pwrdms: powerdomains in this voltagedomain
+ * @scale: function used to scale the voltage of the voltagedomain
++ * @nominal_volt: current nominal voltage for this voltage domain
+ */
+ struct voltagedomain {
+ char *name;
+@@ -84,6 +85,7 @@ struct voltagedomain {
+
+ int (*scale) (struct voltagedomain *voltdm,
+ unsigned long target_volt);
++ u32 nominal_volt;
+
+ struct omap_vdd_info *vdd;
+ };
+@@ -144,11 +146,9 @@ struct omap_voltdm_pmic {
+ *
+ * @volt_data : voltage table having the distinct voltages supported
+ * by the domain and other associated per voltage data.
+- * @curr_volt : current voltage for this vdd.
+ */
+ struct omap_vdd_info {
+ struct omap_volt_data *volt_data;
+- u32 curr_volt;
+ };
+
+ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0142-OMAP3-voltdm-final-removal-of-omap_vdd_info.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0142-OMAP3-voltdm-final-removal-of-omap_vdd_info.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0142-OMAP3-voltdm-final-removal-of-omap_vdd_info.patch
@@ -0,0 +1,282 @@
+From ca11f6a6b48b393eb816f89fed73add7d5e228bf Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Thu, 14 Jul 2011 11:29:06 -0700
+Subject: [PATCH 142/149] OMAP3+: voltdm: final removal of omap_vdd_info
+
+Remove last remaining member (volt_data) from omap_vdd_info into
+struct voltagedomain and removal remaining usage and reference to
+omap_vdd_info.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/voltage.c | 54 ++++--------------------
+ arch/arm/mach-omap2/voltage.h | 16 +------
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 14 ++-----
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 15 +-----
+ 4 files changed, 18 insertions(+), 81 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 29ab389..2e5528f 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -43,34 +43,6 @@
+
+ static LIST_HEAD(voltdm_list);
+
+-static int __init _config_common_vdd_data(struct voltagedomain *voltdm)
+-{
+- /* Generic voltage parameters */
+- voltdm->scale = omap_vp_forceupdate_scale;
+-
+- return 0;
+-}
+-
+-static int __init omap_vdd_data_configure(struct voltagedomain *voltdm)
+-{
+- int ret = -EINVAL;
+-
+- if (!voltdm->pmic) {
+- pr_err("%s: PMIC info requried to configure vdd_%s not"
+- "populated.Hence cannot initialize vdd_%s\n",
+- __func__, voltdm->name, voltdm->name);
+- goto ovdc_out;
+- }
+-
+- if (IS_ERR_VALUE(_config_common_vdd_data(voltdm)))
+- goto ovdc_out;
+-
+- ret = 0;
+-
+-ovdc_out:
+- return ret;
+-}
+-
+ /* Public functions */
+ /**
+ * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
+@@ -155,18 +127,14 @@ void voltdm_reset(struct voltagedomain *voltdm)
+ *
+ */
+ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+- struct omap_volt_data **volt_data)
++ struct omap_volt_data **volt_data)
+ {
+- struct omap_vdd_info *vdd;
+-
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return;
+ }
+
+- vdd = voltdm->vdd;
+-
+- *volt_data = vdd->volt_data;
++ *volt_data = voltdm->volt_data;
+ }
+
+ /**
+@@ -185,9 +153,8 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ * domain or if there is no matching entry.
+ */
+ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+- unsigned long volt)
++ unsigned long volt)
+ {
+- struct omap_vdd_info *vdd;
+ int i;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+@@ -195,17 +162,15 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ return ERR_PTR(-EINVAL);
+ }
+
+- vdd = voltdm->vdd;
+-
+- if (!vdd->volt_data) {
++ if (!voltdm->volt_data) {
+ pr_warning("%s: voltage table does not exist for vdd_%s\n",
+ __func__, voltdm->name);
+ return ERR_PTR(-ENODATA);
+ }
+
+- for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) {
+- if (vdd->volt_data[i].volt_nominal == volt)
+- return &vdd->volt_data[i];
++ for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
++ if (voltdm->volt_data[i].volt_nominal == volt)
++ return &voltdm->volt_data[i];
+ }
+
+ pr_notice("%s: Unable to match the current voltage with the voltage"
+@@ -304,9 +269,8 @@ int __init omap_voltage_late_init(void)
+ omap_vc_init_channel(voltdm);
+ }
+
+- if (voltdm->vdd) {
+- if (omap_vdd_data_configure(voltdm))
+- continue;
++ if (voltdm->vp) {
++ voltdm->scale = omap_vp_forceupdate_scale;
+ omap_vp_init(voltdm);
+ }
+ }
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 3e32eda..68b1ed5 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -33,8 +33,6 @@ struct powerdomain;
+ #define OMAP3_VOLTOFFSET 0xff
+ #define OMAP3_VOLTSETUP2 0xff
+
+-struct omap_vdd_info;
+-
+ /**
+ * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
+ * data
+@@ -85,9 +83,9 @@ struct voltagedomain {
+
+ int (*scale) (struct voltagedomain *voltdm,
+ unsigned long target_volt);
+- u32 nominal_volt;
+
+- struct omap_vdd_info *vdd;
++ u32 nominal_volt;
++ struct omap_volt_data *volt_data;
+ };
+
+ /**
+@@ -141,16 +139,6 @@ struct omap_voltdm_pmic {
+ u8 (*uv_to_vsel) (unsigned long uV);
+ };
+
+-/**
+- * omap_vdd_info - Per Voltage Domain info
+- *
+- * @volt_data : voltage table having the distinct voltages supported
+- * by the domain and other associated per voltage data.
+- */
+-struct omap_vdd_info {
+- struct omap_volt_data *volt_data;
+-};
+-
+ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ struct omap_volt_data **volt_data);
+ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+index e7a0be1..b0d0ae1 100644
+--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -37,16 +37,12 @@ static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
+ .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
+ };
+
+-static struct omap_vdd_info omap3_vdd1_info;
+-
+ static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
+ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
+ .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
+ .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
+ };
+
+-static struct omap_vdd_info omap3_vdd2_info;
+-
+ static struct voltagedomain omap3_voltdm_mpu = {
+ .name = "mpu_iva",
+ .scalable = true,
+@@ -56,7 +52,6 @@ static struct voltagedomain omap3_voltdm_mpu = {
+ .vc = &omap3_vc_mpu,
+ .vfsm = &omap3_vdd1_vfsm,
+ .vp = &omap3_vp_mpu,
+- .vdd = &omap3_vdd1_info,
+ };
+
+ static struct voltagedomain omap3_voltdm_core = {
+@@ -68,7 +63,6 @@ static struct voltagedomain omap3_voltdm_core = {
+ .vc = &omap3_vc_core,
+ .vfsm = &omap3_vdd2_vfsm,
+ .vp = &omap3_vp_core,
+- .vdd = &omap3_vdd2_info,
+ };
+
+ static struct voltagedomain omap3_voltdm_wkup = {
+@@ -94,11 +88,11 @@ void __init omap3xxx_voltagedomains_init(void)
+ * for the currently-running IC
+ */
+ if (cpu_is_omap3630()) {
+- omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
+- omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
++ omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
++ omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
+ } else {
+- omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data;
+- omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
++ omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
++ omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
+ }
+
+ for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+index 9c20fbb..c4584e9 100644
+--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -36,20 +36,14 @@ static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_mpu_info;
+-
+ static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_iva_info;
+-
+ static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
+ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+ };
+
+-static struct omap_vdd_info omap4_vdd_core_info;
+-
+ static struct voltagedomain omap4_voltdm_mpu = {
+ .name = "mpu",
+ .scalable = true,
+@@ -59,7 +53,6 @@ static struct voltagedomain omap4_voltdm_mpu = {
+ .vc = &omap4_vc_mpu,
+ .vfsm = &omap4_vdd_mpu_vfsm,
+ .vp = &omap4_vp_mpu,
+- .vdd = &omap4_vdd_mpu_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_iva = {
+@@ -71,7 +64,6 @@ static struct voltagedomain omap4_voltdm_iva = {
+ .vc = &omap4_vc_iva,
+ .vfsm = &omap4_vdd_iva_vfsm,
+ .vp = &omap4_vp_iva,
+- .vdd = &omap4_vdd_iva_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_core = {
+@@ -83,7 +75,6 @@ static struct voltagedomain omap4_voltdm_core = {
+ .vc = &omap4_vc_core,
+ .vfsm = &omap4_vdd_core_vfsm,
+ .vp = &omap4_vp_core,
+- .vdd = &omap4_vdd_core_info,
+ };
+
+ static struct voltagedomain omap4_voltdm_wkup = {
+@@ -109,9 +100,9 @@ void __init omap44xx_voltagedomains_init(void)
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC
+ */
+- omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data;
+- omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
+- omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
++ omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
++ omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
++ omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
+
+ for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
+ voltdm->sys_clk.name = sys_clk_name;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0143-OMAP3-voltage-rename-omap_voltage_get_nom_volt-voltd.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0143-OMAP3-voltage-rename-omap_voltage_get_nom_volt-voltd.patch
--- /dev/null
@@ -0,0 +1,91 @@
+From c5a7ac2c13e2fc8d3e55213c288f5688fa8394d0 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Fri, 15 Jul 2011 16:05:12 -0700
+Subject: [PATCH 143/149] OMAP3+: voltage: rename omap_voltage_get_nom_volt -> voltdm_get_voltage
+
+Use preferred voltdm_ naming for getting current nominal voltage.
+
+No functional changes.
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/smartreflex-class3.c | 2 +-
+ arch/arm/mach-omap2/voltage.c | 14 ++++++++------
+ arch/arm/mach-omap2/voltage.h | 2 +-
+ 3 files changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
+index 4eac1bc..53d9d0a 100644
+--- a/arch/arm/mach-omap2/smartreflex-class3.c
++++ b/arch/arm/mach-omap2/smartreflex-class3.c
+@@ -15,7 +15,7 @@
+
+ static int sr_class3_enable(struct voltagedomain *voltdm)
+ {
+- unsigned long volt = omap_voltage_get_nom_volt(voltdm);
++ unsigned long volt = voltdm_get_voltage(voltdm);
+
+ if (!volt) {
+ pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 2e5528f..031f6bf 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -45,13 +45,13 @@ static LIST_HEAD(voltdm_list);
+
+ /* Public functions */
+ /**
+- * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
+- * @voltdm: pointer to the VDD for which current voltage info is needed
++ * voltdm_get_voltage() - Gets the current non-auto-compensated voltage
++ * @voltdm: pointer to the voltdm for which current voltage info is needed
+ *
+- * API to get the current non-auto-compensated voltage for a VDD.
+- * Returns 0 in case of error else returns the current voltage for the VDD.
++ * API to get the current non-auto-compensated voltage for a voltage domain.
++ * Returns 0 in case of error else returns the current voltage.
+ */
+-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
++unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
+ {
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+@@ -72,6 +72,8 @@ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+ int voltdm_scale(struct voltagedomain *voltdm,
+ unsigned long target_volt)
+ {
++ int ret;
++
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return -EINVAL;
+@@ -104,7 +106,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
+ return;
+ }
+
+- target_volt = omap_voltage_get_nom_volt(voltdm);
++ target_volt = voltdm_get_voltage(voltdm);
+ if (!target_volt) {
+ pr_err("%s: unable to find current voltage for vdd_%s\n",
+ __func__, voltdm->name);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 68b1ed5..b4c6259 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -143,7 +143,6 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ struct omap_volt_data **volt_data);
+ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ unsigned long volt);
+-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ struct omap_voltdm_pmic *pmic);
+@@ -178,4 +177,5 @@ int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+ struct powerdomain *pwrdm));
+ int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+ void voltdm_reset(struct voltagedomain *voltdm);
++unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+ #endif
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0144-OMAP3-voltage-update-nominal-voltage-in-voltdm_scale.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0144-OMAP3-voltage-update-nominal-voltage-in-voltdm_scale.patch
--- /dev/null
@@ -0,0 +1,49 @@
+From b0f944b9fde42db8d1712cdafe4f7720adab19a6 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@ti.com>
+Date: Mon, 18 Jul 2011 16:24:17 -0700
+Subject: [PATCH 144/149] OMAP3+: voltage: update nominal voltage in voltdm_scale() not VC post-scale
+
+Currently, the nominal voltage is updated in the VC post-scale function
+which is common to both scaling methods. However, this has readabiliy
+problems as this update is not where it might be expected. Instead, move
+the updated into voltdm_scale() upon a successful return of voltdm->scale()
+
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/vc.c | 2 --
+ arch/arm/mach-omap2/voltage.c | 6 +++++-
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
+index 3233c69..16fa912 100644
+--- a/arch/arm/mach-omap2/vc.c
++++ b/arch/arm/mach-omap2/vc.c
+@@ -143,8 +143,6 @@ void omap_vc_post_scale(struct voltagedomain *voltdm,
+ smps_delay = ((smps_steps * voltdm->pmic->step_size) /
+ voltdm->pmic->slew_rate) + 2;
+ udelay(smps_delay);
+-
+- voltdm->nominal_volt = target_volt;
+ }
+
+ /* vc_bypass_scale - VC bypass method of voltage scaling */
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 031f6bf..cebc8b1 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -85,7 +85,11 @@ int voltdm_scale(struct voltagedomain *voltdm,
+ return -ENODATA;
+ }
+
+- return voltdm->scale(voltdm, target_volt);
++ ret = voltdm->scale(voltdm, target_volt);
++ if (!ret)
++ voltdm->nominal_volt = target_volt;
++
++ return ret;
+ }
+
+ /**
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0145-OMAP4-PM-TWL6030-fix-voltage-conversion-formula.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0145-OMAP4-PM-TWL6030-fix-voltage-conversion-formula.patch
--- /dev/null
@@ -0,0 +1,85 @@
+From 1b4e22ed2ce91be68e16977d26ae2d49674137fe Mon Sep 17 00:00:00 2001
+From: Patrick Titiano <p-titiano@ti.com>
+Date: Wed, 18 May 2011 00:17:30 -0500
+Subject: [PATCH 145/149] OMAP4: PM: TWL6030: fix voltage conversion formula
+
+omap_twl_vsel_to_uv() and omap_twl_uv_to_vsel() functions used to convert
+voltages to TWL6030 SMPS commands (a.k.a "vsel") implement incorrect conversion
+formula.
+It uses legacy OMAP3 formula, but OMAP4 Power IC has different offset and
+voltage step:
+ - Voltage Step is now 12.66mV (instead of 12.5mV)
+ - Offset is either 607.7mV or 709mV depending on TWL6030 chip revision
+ (instead of 600mV)
+This leads to setting voltages potentially higher than expected, and so
+potentially some (limited) power overconsumption.
+
+For reference, see formula and tables in section 8.5.2.3
+"Output Voltage Selection (Standard Mode / Extended Mode with or without offset)"
+ in TWL6030 functional specifications document.
+
+[nm@ti.com: ported to voltdm_c]
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Patrick Titiano <p-titiano@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 14 +++++++-------
+ 1 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 6b247d1..a66bf6b 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -106,9 +106,9 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
+ return 1350000;
+
+ if (smps_offset & 0x8)
+- return ((((vsel - 1) * 125) + 7000)) * 100;
++ return ((((vsel - 1) * 1266) + 70900)) * 10;
+ else
+- return ((((vsel - 1) * 125) + 6000)) * 100;
++ return ((((vsel - 1) * 1266) + 60770)) * 10;
+ }
+
+ static u8 twl6030_uv_to_vsel(unsigned long uv)
+@@ -138,9 +138,9 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
+ return 0x3A;
+
+ if (smps_offset & 0x8)
+- return DIV_ROUND_UP(uv - 700000, 12500) + 1;
++ return DIV_ROUND_UP(uv - 709000, 12660) + 1;
+ else
+- return DIV_ROUND_UP(uv - 600000, 12500) + 1;
++ return DIV_ROUND_UP(uv - 607700, 12660) + 1;
+ }
+
+ static struct omap_voltdm_pmic omap3_mpu_pmic = {
+@@ -187,7 +187,7 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
+
+ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ .slew_rate = 4000,
+- .step_size = 12500,
++ .step_size = 12660,
+ .on_volt = 1350000,
+ .onlp_volt = 1350000,
+ .ret_volt = 837500,
+@@ -208,7 +208,7 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+
+ static struct omap_voltdm_pmic omap4_iva_pmic = {
+ .slew_rate = 4000,
+- .step_size = 12500,
++ .step_size = 12660,
+ .on_volt = 1100000,
+ .onlp_volt = 1100000,
+ .ret_volt = 837500,
+@@ -229,7 +229,7 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
+
+ static struct omap_voltdm_pmic omap4_core_pmic = {
+ .slew_rate = 4000,
+- .step_size = 12500,
++ .step_size = 12660,
+ .on_volt = 1100000,
+ .onlp_volt = 1100000,
+ .ret_volt = 837500,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0146-OMAP4-PM-TWL6030-fix-uv-to-voltage-for-0x39.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0146-OMAP4-PM-TWL6030-fix-uv-to-voltage-for-0x39.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0146-OMAP4-PM-TWL6030-fix-uv-to-voltage-for-0x39.patch
@@ -0,0 +1,37 @@
+From ff7ef48e169e0bba98135d834f5c7cdf9cb65965 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Wed, 18 May 2011 00:17:31 -0500
+Subject: [PATCH 146/149] OMAP4: PM: TWL6030: fix uv to voltage for >0x39
+
+using 1.35V as a check is not correct, we know that beyond 0x39,
+voltages are non linear - hence use the conversion iff uV greater
+than that for 0x39. For example, with 709mV as the smps offset,
+the max linear is actually 1.41V(0x39vsel)!
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 7 ++++++-
+ 1 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index a66bf6b..5def7c2 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -134,8 +134,13 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
+ * hardcoding only for 1.35 V which is used for 1GH OPP for
+ * OMAP4430.
+ */
+- if (uv == 1350000)
++ if (uv > twl6030_vsel_to_uv(0x39)) {
++ if (uv == 1350000)
++ return 0x3A;
++ pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
++ __func__, uv, twl6030_vsel_to_uv(0x39));
+ return 0x3A;
++ }
+
+ if (smps_offset & 0x8)
+ return DIV_ROUND_UP(uv - 709000, 12660) + 1;
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0147-OMAP4-PM-TWL6030-address-0V-conversions.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0147-OMAP4-PM-TWL6030-address-0V-conversions.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0147-OMAP4-PM-TWL6030-address-0V-conversions.patch
@@ -0,0 +1,38 @@
+From c36cd6579c43481193cc5b833622f01618f7408c Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Wed, 18 May 2011 00:17:32 -0500
+Subject: [PATCH 147/149] OMAP4: PM: TWL6030: address 0V conversions
+
+0V conversions should be mapped to 0 as it is meant to denote
+off voltages.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 5def7c2..b30adf3 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -95,6 +95,8 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
+ is_offset_valid = true;
+ }
+
++ if (!vsel)
++ return 0;
+ /*
+ * There is no specific formula for voltage to vsel
+ * conversion above 1.3V. There are special hardcoded
+@@ -127,6 +129,8 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
+ is_offset_valid = true;
+ }
+
++ if (!uv)
++ return 0x00;
+ /*
+ * There is no specific formula for voltage to vsel
+ * conversion above 1.3V. There are special hardcoded
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0148-OMAP4-PM-TWL6030-fix-ON-RET-OFF-voltages.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0148-OMAP4-PM-TWL6030-fix-ON-RET-OFF-voltages.patch
--- /dev/null
+++ b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0148-OMAP4-PM-TWL6030-fix-ON-RET-OFF-voltages.patch
@@ -0,0 +1,71 @@
+From c2e24e859ee7b9942a9075db480462f7b3d080ed Mon Sep 17 00:00:00 2001
+From: Patrick Titiano <p-titiano@ti.com>
+Date: Wed, 18 May 2011 00:17:33 -0500
+Subject: [PATCH 148/149] OMAP4: PM: TWL6030: fix ON/RET/OFF voltages
+
+According to latest OMAP4430 Data Manual v0.4 dated March 2011:
+ - Retention voltage shall be set to 0.83V. See tables 2.2, 2.4 and 2.6 in DM.
+ This allows saving a little more power in retention states.
+ - OPP100 IVA nominal voltage is 1.188V. See table 2.4 in DM.
+ This allows saving a little power when CPU wakes up until Smart-Reflex is
+ not yet resumed.
+
+[nm@ti.com: ported to voltdm_c]
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Patrick Titiano <p-titiano@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 24 ++++++++++++------------
+ 1 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index b30adf3..4bc99fb 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -197,10 +197,10 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
+ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12660,
+- .on_volt = 1350000,
+- .onlp_volt = 1350000,
+- .ret_volt = 837500,
+- .off_volt = 600000,
++ .on_volt = 1375000,
++ .onlp_volt = 1375000,
++ .ret_volt = 830000,
++ .off_volt = 0,
+ .volt_setup_time = 0,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+@@ -218,10 +218,10 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ static struct omap_voltdm_pmic omap4_iva_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12660,
+- .on_volt = 1100000,
+- .onlp_volt = 1100000,
+- .ret_volt = 837500,
+- .off_volt = 600000,
++ .on_volt = 1188000,
++ .onlp_volt = 1188000,
++ .ret_volt = 830000,
++ .off_volt = 0,
+ .volt_setup_time = 0,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+@@ -239,10 +239,10 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
+ static struct omap_voltdm_pmic omap4_core_pmic = {
+ .slew_rate = 4000,
+ .step_size = 12660,
+- .on_volt = 1100000,
+- .onlp_volt = 1100000,
+- .ret_volt = 837500,
+- .off_volt = 600000,
++ .on_volt = 1200000,
++ .onlp_volt = 1200000,
++ .ret_volt = 830000,
++ .off_volt = 0,
+ .volt_setup_time = 0,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+--
+1.6.6.1
+
diff --git a/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0149-OMAP4-PM-TWL6030-add-cmd-register.patch b/recipes-kernel/linux/linux-3.0/pm-wip/voltdm/0149-OMAP4-PM-TWL6030-add-cmd-register.patch
--- /dev/null
@@ -0,0 +1,56 @@
+From fd51f94697591a638854bff691c7327eba20ac2e Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Wed, 18 May 2011 00:17:34 -0500
+Subject: [PATCH 149/149] OMAP4: PM: TWL6030: add cmd register
+
+Without the command register, ON/ONLP/RET/OFF voltages are
+useless. and TWL will be unable to use these
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 4bc99fb..f515a1a 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -42,8 +42,11 @@
+
+ #define OMAP4_SRI2C_SLAVE_ADDR 0x12
+ #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
++#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
+ #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
++#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
+ #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
++#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
+
+ #define OMAP4_VP_CONFIG_ERROROFFSET 0x00
+ #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
+@@ -210,6 +213,7 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
++ .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
+ .i2c_high_speed = true,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+@@ -231,6 +235,7 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
++ .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
+ .i2c_high_speed = true,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+@@ -252,6 +257,7 @@ static struct omap_voltdm_pmic omap4_core_pmic = {
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
+ .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
++ .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
+ .vsel_to_uv = twl6030_vsel_to_uv,
+ .uv_to_vsel = twl6030_uv_to_vsel,
+ };
+--
+1.6.6.1
+
index 99b3ddc23cb6adc4de1bbc5968b13e66c41b99e3..88a70b5889d1b7f5579a71a94c65041cd8c4adad 100644 (file)
COMPATIBLE_MACHINE = "(beagleboard)"
# Somewhere after 3.0rc7
-SRCREV_pn-${PN} = "e6625fa48e6580a74b7e700efd7e6463e282810b"
-
+SRCREV_pn-${PN} = "cf6ace16a3cd8b728fb0afa68368fd40bbeae19f"
# The main PR is now using MACHINE_KERNEL_PR, for omap3 see conf/machine/include/omap3.inc
-MACHINE_KERNEL_PR_append = "a"
+MACHINE_KERNEL_PR_append = "b"
FILESPATHPKG_prepend = "linux-3.0:"
SRC_URI += "git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git;protocol=git \
- file://beagle/0001-OMAP3-beagle-add-support-for-beagleboard-xM-revision.patch \
+ file://pm-wip/voltdm/0001-cleanup-regulator-supply-definitions-in-mach-omap2.patch \
+ file://pm-wip/voltdm/0002-Remove-old-style-supply.dev-assignments-common-in-hs.patch \
+ file://pm-wip/voltdm/0003-omap-Use-separate-init_irq-functions-to-avoid-cpu_is.patch \
+ file://pm-wip/voltdm/0004-omap-Set-separate-timer-init-functions-to-avoid-cpu_.patch \
+ file://pm-wip/voltdm/0005-omap-Move-dmtimer-defines-to-dmtimer.h.patch \
+ file://pm-wip/voltdm/0006-omap-Make-a-subset-of-dmtimer-functions-into-inline-.patch \
+ file://pm-wip/voltdm/0007-omap2-Use-dmtimer-macros-for-clockevent.patch \
+ file://pm-wip/voltdm/0008-omap2-Remove-gptimer_wakeup-for-now.patch \
+ file://pm-wip/voltdm/0009-OMAP3-SR-make-notify-independent-of-class.patch \
+ file://pm-wip/voltdm/0010-OMAP3-SR-disable-interrupt-by-default.patch \
+ file://pm-wip/voltdm/0011-OMAP3-SR-enable-disable-SR-only-on-need.patch \
+ file://pm-wip/voltdm/0012-OMAP3-SR-fix-cosmetic-indentation.patch \
+ file://pm-wip/voltdm/0013-omap2-Reserve-clocksource-and-timesource-and-initial.patch \
+ file://pm-wip/voltdm/0014-omap2-Use-dmtimer-macros-for-clocksource.patch \
+ file://pm-wip/voltdm/0015-omap2-Remove-omap2_gp_clockevent_set_gptimer.patch \
+ file://pm-wip/voltdm/0016-omap2-Rename-timer-gp.c-into-timer.c-to-combine-time.patch \
+ file://pm-wip/voltdm/0017-omap-cleanup-NAND-platform-data.patch \
+ file://pm-wip/voltdm/0018-omap-board-omap3evm-Fix-compilation-error.patch \
+ file://pm-wip/voltdm/0019-omap-mcbsp-Drop-SPI-mode-support.patch \
+ file://pm-wip/voltdm/0020-omap-mcbsp-Drop-in-driver-transfer-support.patch \
+ file://pm-wip/voltdm/0021-omap2-fix-build-regression.patch \
+ file://pm-wip/voltdm/0022-OMAP-New-twl-common-for-common-TWL-configuration.patch \
+ file://pm-wip/voltdm/0023-OMAP4-Move-common-twl6030-configuration-to-twl-commo.patch \
+ file://pm-wip/voltdm/0024-OMAP3-Move-common-twl-configuration-to-twl-common.patch \
+ file://pm-wip/voltdm/0025-OMAP3-Move-common-regulator-configuration-to-twl-com.patch \
+ file://pm-wip/voltdm/0026-omap-mcbsp-Remove-rx_-tx_word_length-variables.patch \
+ file://pm-wip/voltdm/0027-omap-mcbsp-Remove-port-number-enums.patch \
+ file://pm-wip/voltdm/0028-OMAP-dmtimer-add-missing-include.patch \
+ file://pm-wip/voltdm/0029-OMAP2-hwmod-Fix-smart-standby-wakeup-support.patch \
+ file://pm-wip/voltdm/0030-OMAP4-hwmod-data-Add-MSTANDBY_SMART_WKUP-flag.patch \
+ file://pm-wip/voltdm/0031-OMAP2-hwmod-Enable-module-in-shutdown-to-access-sysc.patch \
+ file://pm-wip/voltdm/0032-OMAP2-hwmod-Do-not-write-the-enawakeup-bit-if-SYSC_H.patch \
+ file://pm-wip/voltdm/0033-OMAP2-hwmod-Remove-_populate_mpu_rt_base-warning.patch \
+ file://pm-wip/voltdm/0034-OMAP2-hwmod-Fix-the-HW-reset-management.patch \
+ file://pm-wip/voltdm/0035-OMAP-hwmod-Add-warnings-if-enable-failed.patch \
+ file://pm-wip/voltdm/0036-OMAP-hwmod-Move-pr_debug-to-improve-the-readability.patch \
+ file://pm-wip/voltdm/0037-omap_hwmod-use-a-null-structure-record-to-terminate-.patch \
+ file://pm-wip/voltdm/0038-omap_hwmod-share-identical-omap_hwmod_addr_space-arr.patch \
+ file://pm-wip/voltdm/0039-omap_hwmod-use-a-terminator-record-with-omap_hwmod_m.patch \
+ file://pm-wip/voltdm/0040-omap_hwmod-share-identical-omap_hwmod_mpu_irqs-array.patch \
+ file://pm-wip/voltdm/0041-omap_hwmod-use-a-terminator-record-with-omap_hwmod_d.patch \
+ file://pm-wip/voltdm/0042-omap_hwmod-share-identical-omap_hwmod_dma_info-array.patch \
+ file://pm-wip/voltdm/0043-omap_hwmod-share-identical-omap_hwmod_class-omap_hwm.patch \
+ file://pm-wip/voltdm/0044-OMAP4-hwmod-data-Fix-L3-interconnect-data-order-and-.patch \
+ file://pm-wip/voltdm/0045-OMAP4-hwmod-data-Remove-un-needed-parens.patch \
+ file://pm-wip/voltdm/0046-OMAP4-hwmod-data-Fix-bad-alignement.patch \
+ file://pm-wip/voltdm/0047-OMAP4-hwmod-data-Align-interconnect-format-with-regu.patch \
+ file://pm-wip/voltdm/0048-OMAP4-clock-data-Add-sddiv-to-USB-DPLL.patch \
+ file://pm-wip/voltdm/0049-OMAP4-clock-data-Remove-usb_host_fs-clkdev-with-NULL.patch \
+ file://pm-wip/voltdm/0050-OMAP4-clock-data-Re-order-some-clock-nodes-and-struc.patch \
+ file://pm-wip/voltdm/0051-OMAP4-clock-data-Fix-max-mult-and-div-for-USB-DPLL.patch \
+ file://pm-wip/voltdm/0052-OMAP4-prcm-Fix-errors-in-few-defines-name.patch \
+ file://pm-wip/voltdm/0053-OMAP4-prm-Remove-wrong-clockdomain-offsets.patch \
+ file://pm-wip/voltdm/0054-OMAP4-powerdomain-data-Fix-indentation.patch \
+ file://pm-wip/voltdm/0055-OMAP4-cm-Remove-RESTORE-macros-to-avoid-access-from-.patch \
+ file://pm-wip/voltdm/0056-OMAP4-prcm_mpu-Fix-indent-in-few-macros.patch \
+ file://pm-wip/voltdm/0057-OMAP4-clockdomain-data-Fix-data-order-and-wrong-name.patch \
+ file://pm-wip/voltdm/0058-OMAP-omap_device-replace-_find_by_pdev-with-to_omap_.patch \
+ file://pm-wip/voltdm/0059-OMAP-PM-remove-OMAP_PM_NONE-config-option.patch \
+ file://pm-wip/voltdm/0060-OMAP4-clock-data-Remove-McASP2-McASP3-and-MMC6-clock.patch \
+ file://pm-wip/voltdm/0061-OMAP4-clock-data-Remove-UNIPRO-clock-nodes.patch \
+ file://pm-wip/voltdm/0062-OMAP4-hwmod-data-Modify-DSS-opt-clocks.patch \
+ file://pm-wip/voltdm/0063-OMAP2-PM-Initialise-sleep_switch-to-a-non-valid-valu.patch \
+ file://pm-wip/voltdm/0064-OMAP4-powerdomain-data-Fix-core-mem-states-and-missi.patch \
+ file://pm-wip/voltdm/0065-OMAP4-clock-data-Keep-GPMC-clocks-always-enabled-and.patch \
+ file://pm-wip/voltdm/0066-OMAP4-powerdomain-data-Remove-unsupported-MPU-powerd.patch \
+ file://pm-wip/voltdm/0067-OMAP4-hwmod-data-Change-DSS-main_clk-scheme.patch \
+ file://pm-wip/voltdm/0068-I2C-OMAP2-Set-hwmod-flags-to-only-allow-16-bit-acces.patch \
+ file://pm-wip/voltdm/0069-I2C-OMAP2-increase-omap_i2c_dev_attr-flags-from-u8-t.patch \
+ file://pm-wip/voltdm/0070-I2C-OMAP2-Introduce-I2C-IP-versioning-constants.patch \
+ file://pm-wip/voltdm/0071-I2C-OMAP1-OMAP2-create-omap-I2C-functionality-flags-.patch \
+ file://pm-wip/voltdm/0072-I2C-OMAP2-Tag-all-OMAP2-hwmod-defintions-with-I2C-IP.patch \
+ file://pm-wip/voltdm/0073-I2C-OMAP2-add-correct-functionality-flags-to-all-oma.patch \
+ file://pm-wip/voltdm/0074-OMAP-hwmod-fix-the-i2c-reset-timeout-during-bootup.patch \
+ file://pm-wip/voltdm/0075-OMAP-omap_device-Create-clkdev-entry-for-hwmod-main_.patch \
+ file://pm-wip/voltdm/0076-OMAP4-clock-data-Add-missing-divider-selection-for-a.patch \
+ file://pm-wip/voltdm/0077-OMAP4-hwmod-data-Add-clock-domain-attribute.patch \
+ file://pm-wip/voltdm/0078-OMAP2-hwmod-Init-clkdm-field-at-boot-time.patch \
+ file://pm-wip/voltdm/0079-OMAP4-hwmod-Replace-CLKCTRL-absolute-address-with-of.patch \
+ file://pm-wip/voltdm/0080-OMAP-hwmod-Wait-the-idle-status-to-be-disabled.patch \
+ file://pm-wip/voltdm/0081-OMAP4-hwmod-Replace-RSTCTRL-absolute-address-with-of.patch \
+ file://pm-wip/voltdm/0082-OMAP4-prm-Replace-warm-reset-API-with-the-offset-bas.patch \
+ file://pm-wip/voltdm/0083-OMAP4-prm-Remove-deprecated-functions.patch \
+ file://pm-wip/voltdm/0084-OMAP4-hwmod-data-Add-PRM-context-register-offset.patch \
+ file://pm-wip/voltdm/0085-OMAP4-hwmod-data-Add-modulemode-entry-in-omap_hwmod-.patch \
+ file://pm-wip/voltdm/0086-OMAP4-cm-Add-two-new-APIs-for-modulemode-control.patch \
+ file://pm-wip/voltdm/0087-OMAP4-hwmod-Introduce-the-module-control-in-hwmod-co.patch \
+ file://pm-wip/voltdm/0088-OMAP-clockdomain-Remove-redundant-call-to-pwrdm_wait.patch \
+ file://pm-wip/voltdm/0089-OMAP2-clockdomain-Add-2-APIs-to-control-clockdomain-.patch \
+ file://pm-wip/voltdm/0090-OMAP2-clockdomain-add-clkdm_in_hwsup.patch \
+ file://pm-wip/voltdm/0091-OMAP2-PM-idle-clkdms-only-if-already-in-idle.patch \
+ file://pm-wip/voltdm/0092-OMAP2-clockdomain-Add-per-clkdm-lock-to-prevent-conc.patch \
+ file://pm-wip/voltdm/0093-OMAP2-clock-allow-per-SoC-clock-init-code-to-prevent.patch \
+ file://pm-wip/voltdm/0094-OMAP2-hwmod-Follow-the-recommended-PRCM-module-enabl.patch \
+ file://pm-wip/voltdm/0095-OMAP-Add-debugfs-node-to-show-the-summary-of-all-clo.patch \
+ file://pm-wip/voltdm/0096-OMAP2-hwmod-remove-unused-voltagedomain-pointer.patch \
+ file://pm-wip/voltdm/0097-OMAP2-voltage-move-PRCM-mod-offets-into-VC-VP-struct.patch \
+ file://pm-wip/voltdm/0098-OMAP2-voltage-move-prm_irqst_reg-from-VP-into-voltag.patch \
+ file://pm-wip/voltdm/0099-OMAP2-voltage-start-towards-a-new-voltagedomain-laye.patch \
+ file://pm-wip/voltdm/0100-OMAP3-voltage-rename-mpu-voltagedomain-to-mpu_iva.patch \
+ file://pm-wip/voltdm/0101-OMAP3-voltagedomain-data-add-wakeup-domain.patch \
+ file://pm-wip/voltdm/0102-OMAP3-voltage-add-scalable-flag-to-voltagedomain.patch \
+ file://pm-wip/voltdm/0103-OMAP2-powerdomain-add-voltagedomain-to-struct-powerd.patch \
+ file://pm-wip/voltdm/0104-OMAP2-add-voltage-domains-and-connect-to-powerdomain.patch \
+ file://pm-wip/voltdm/0105-OMAP3-powerdomain-data-add-voltage-domains.patch \
+ file://pm-wip/voltdm/0106-OMAP4-powerdomain-data-add-voltage-domains.patch \
+ file://pm-wip/voltdm/0107-OMAP2-powerdomain-add-voltage-domain-lookup-during-r.patch \
+ file://pm-wip/voltdm/0108-OMAP2-voltage-keep-track-of-powerdomains-in-each-vol.patch \
+ file://pm-wip/voltdm/0109-OMAP2-voltage-split-voltage-controller-VC-code-into-.patch \
+ file://pm-wip/voltdm/0110-OMAP2-voltage-move-VC-into-struct-voltagedomain-misc.patch \
+ file://pm-wip/voltdm/0111-OMAP2-voltage-enable-VC-bypass-scale-method-when-VC-.patch \
+ file://pm-wip/voltdm/0112-OMAP2-voltage-split-out-voltage-processor-VP-code-in.patch \
+ file://pm-wip/voltdm/0113-OMAP2-VC-support-PMICs-with-separate-voltage-and-com.patch \
+ file://pm-wip/voltdm/0114-OMAP2-add-PRM-VP-functions-for-checking-clearing-VP-.patch \
+ file://pm-wip/voltdm/0115-OMAP3-VP-replace-transaction-done-check-clear-with-V.patch \
+ file://pm-wip/voltdm/0116-OMAP2-PRM-add-register-access-functions-for-VC-VP.patch \
+ file://pm-wip/voltdm/0117-OMAP3-voltage-convert-to-PRM-register-access-functio.patch \
+ file://pm-wip/voltdm/0118-OMAP3-VC-cleanup-i2c-slave-address-configuration.patch \
+ file://pm-wip/voltdm/0119-OMAP3-VC-cleanup-PMIC-register-address-configuration.patch \
+ file://pm-wip/voltdm/0120-OMAP3-VC-bypass-use-fields-from-VC-struct-instead-of.patch \
+ file://pm-wip/voltdm/0121-OMAP3-VC-cleanup-voltage-setup-time-configuration.patch \
+ file://pm-wip/voltdm/0122-OMAP3-VC-move-on-onlp-ret-off-command-configuration-.patch \
+ file://pm-wip/voltdm/0123-OMAP3-VC-abstract-out-channel-configuration.patch \
+ file://pm-wip/voltdm/0124-OMAP3-voltage-domain-move-PMIC-struct-from-vdd_info-.patch \
+ file://pm-wip/voltdm/0125-OMAP3-VC-make-I2C-config-programmable-with-PMIC-spec.patch \
+ file://pm-wip/voltdm/0126-OMAP3-PM-VC-handle-mutant-channel-config-for-OMAP4-M.patch \
+ file://pm-wip/voltdm/0127-OMAP3-VC-use-last-nominal-voltage-setting-to-get-cur.patch \
+ file://pm-wip/voltdm/0128-OMAP3-VP-cleanup-move-VP-instance-into-voltdm-misc.-.patch \
+ file://pm-wip/voltdm/0129-OMAP3-voltage-remove-unneeded-debugfs-interface.patch \
+ file://pm-wip/voltdm/0130-OMAP3-VP-struct-omap_vp_common-replace-shift-with-__.patch \
+ file://pm-wip/voltdm/0131-OMAP3-VP-move-SoC-specific-sys-clock-rate-retreival-.patch \
+ file://pm-wip/voltdm/0132-OMAP3-VP-move-timing-calculation-config-into-VP-init.patch \
+ file://pm-wip/voltdm/0133-OMAP3-VP-create-VP-helper-function-for-updating-erro.patch \
+ file://pm-wip/voltdm/0134-OMAP3-VP-remove-omap_vp_runtime_data.patch \
+ file://pm-wip/voltdm/0135-OMAP3-VP-move-voltage-scale-function-pointer-into-st.patch \
+ file://pm-wip/voltdm/0136-OMAP-VP-Explicitly-mask-VPVOLTAGE-field.patch \
+ file://pm-wip/voltdm/0137-OMAP3-VP-update_errorgain-return-error-if-VP.patch \
+ file://pm-wip/voltdm/0138-OMAP3-VP-remove-unused-omap_vp_get_curr_volt.patch \
+ file://pm-wip/voltdm/0139-OMAP3-VP-combine-setting-init-voltage-into-common-fu.patch \
+ file://pm-wip/voltdm/0140-OMAP3-voltage-rename-scale-and-reset-functions-using.patch \
+ file://pm-wip/voltdm/0141-OMAP3-voltage-move-rename-curr_volt-from-vdd_info-in.patch \
+ file://pm-wip/voltdm/0142-OMAP3-voltdm-final-removal-of-omap_vdd_info.patch \
+ file://pm-wip/voltdm/0143-OMAP3-voltage-rename-omap_voltage_get_nom_volt-voltd.patch \
+ file://pm-wip/voltdm/0144-OMAP3-voltage-update-nominal-voltage-in-voltdm_scale.patch \
+ file://pm-wip/voltdm/0145-OMAP4-PM-TWL6030-fix-voltage-conversion-formula.patch \
+ file://pm-wip/voltdm/0146-OMAP4-PM-TWL6030-fix-uv-to-voltage-for-0x39.patch \
+ file://pm-wip/voltdm/0147-OMAP4-PM-TWL6030-address-0V-conversions.patch \
+ file://pm-wip/voltdm/0148-OMAP4-PM-TWL6030-fix-ON-RET-OFF-voltages.patch \
+ file://pm-wip/voltdm/0149-OMAP4-PM-TWL6030-add-cmd-register.patch \
file://pm-wip/cpufreq/0001-PM-OPP-introduce-function-to-free-cpufreq-table.patch \
file://pm-wip/cpufreq/0002-OMAP-CPUfreq-ensure-driver-initializes-after-cpufreq.patch \
file://pm-wip/cpufreq/0003-OMAP-CPUfreq-ensure-policy-is-fully-initialized.patch \
@@ -35,13 +182,17 @@ SRC_URI += "git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git;pro
file://pm-wip/cpufreq/0017-OMAP2-cpufreq-notify-even-with-bad-boot-frequency.patch \
file://pm-wip/cpufreq/0018-OMAP2-cpufreq-Enable-all-CPUs-in-shared-policy-mask.patch \
file://pm-wip/cpufreq/0019-OMAP2-CPUfreq-update-lpj-with-reference-value-to-avo.patch \
- file://for_3.1/pm-misc/0001-OMAP3-SR-disable-interrupt-by-default.patch \
- file://for_3.1/pm-misc/0002-OMAP3-SR-enable-disable-SR-only-on-need.patch \
- file://for_3.1/pm-misc/0003-OMAP3-SR-fix-cosmetic-indentation.patch \
- file://for_3.1/pm-misc/0004-OMAP3-PM-debug-remove-sleep_while_idle-feature.patch \
- file://for_3.1/pm-misc/0005-OMAP2-PM-debug-remove-register-dumping.patch \
- file://for_3.1/pm-misc/0006-OMAP3-PM-debug-remove-register-dumping.patch \
- file://for_3.1/pm-misc/0007-OMAP2-PM-fix-section-mismatch-in-pm_dbg_init.patch \
+ file://bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch \
+ file://bias/0002-OMAP3-PM-VP-generalize-PRM-interrupt-helpers.patch \
+ file://bias/0003-OMAP3-PRM-add-tranxdone-IRQ-handlers-for-ABB.patch \
+ file://bias/0004-OMAP3-ABB-Adaptive-Body-Bias-structures-data.patch \
+ file://bias/0005-OMAP3-OPP-add-ABB-data-to-voltage-tables.patch \
+ file://bias/0006-OMAP3-Voltage-add-ABB-data-to-voltage-domains.patch \
+ file://bias/0007-OMAP3-ABB-initialization-transition-functions.patch \
+ file://bias/0008-OMAP3-Voltage-add-ABB-to-voltage-scaling.patch \
+ file://beagle/0001-OMAP3-beagle-add-support-for-beagleboard-xM-revision.patch \
+ file://beagle/0002-UNFINISHED-OMAP3-beagle-add-support-for-expansionboa.patch \
+ file://beagle/0003-HACK-OMAP3-beagle-switch-to-GPTIMER1.patch \
file://defconfig"
SRC_URI_append_beagleboard = " file://logo_linux_clut224.ppm \