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author | Deepak K <deepak.k@ti.com> | |
Wed, 14 Jul 2010 01:30:58 +0000 (20:30 -0500) | ||
committer | Deepak K <deepak.k@ti.com> | |
Wed, 14 Jul 2010 18:55:36 +0000 (13:55 -0500) |
This patch fixes the SDCR Memory Configuration for 1GB memory space.
CAS Width Change has been modified to 6 to accomodate the 1GB memory
space. This corrects columns addressing from A0-A9 and A11.
Signed-off-by: Deepak K <deepak.k@ti.com>
CAS Width Change has been modified to 6 to accomodate the 1GB memory
space. This corrects columns addressing from A0-A9 and A11.
Signed-off-by: Deepak K <deepak.k@ti.com>
include/asm-arm/arch-omap3/mem.h | patch | blob | history |
index 20044cf82421a3f13d506446354226c7e175bf3c..d391463d0345626c78480000354a6c0c4ab46544 100644 (file)
defined(CONFIG_3630ZOOM3) || defined(CONFIG_3630SDP)
#define SDP_SDRC_MDCFG_0_DDR (0x03588099) /* Hynix MCP ddr module */
#elif defined(CONFIG_3630SDP_1G) || defined(CONFIG_3630ZOOM3_1G)
-#define SDP_SDRC_MDCFG_0_DDR (0x03590099) /* Hynix MCP ddr module */
+/*
+ * LOCKSTATUS - Set to 0b0;
+ * RASWIDTH - Set to 0x3 For the row address a0-a13
+ * CASWIDTH - Set to 0x6 For the column address a0-a9,a11
+ * ADDRMUXLEGACY - Set to 0b1; Enabled the Legacy Addresssing
+ * RAMSIZE - Set to 0x100; Set this to 512MB for each CS
+ * BANKALLOCATION - Set to 0x2; Row-bank-column
+ * B32NOT16 - Set to 0b1; External SDRAM device is x32 bit.
+ * DEEPPD - Set to 0b1; The memory supports deep-power-down mode
+ * DDRTYPE - Set to 0b0; Mobile DDR
+ * RAMTYPE - Set to 0x1; DDR-SDRAM (double data rate)
+ */
+#define SDP_SDRC_MDCFG_0_DDR (0x03690099) /* Hynix MCP ddr module */
#else
#define SDP_SDRC_MDCFG_0_DDR (0x02584099) /* Micron MCP ddr module */
#endif