am57xx_evm_defconfig: Add IPU and dependent configs
Enable IPU and dependent configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable IPU and dependent configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
configs: dra7xx_evm_defconfig: Add IPU and dependent configs
Enable IPU and dependent configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable IPU and dependent configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
spl: enable caches on all armv7r platforms
Enabling caches in the SPL for all armv7r platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enabling caches in the SPL for all armv7r platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: caches: Disable mmu only if mmu is available
As part of disabling caches MMU as well gets disabled. But MMU is not
available on all armv7 cores like R5F. So disable MMU only if it is
available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
As part of disabling caches MMU as well gets disabled. But MMU is not
available on all armv7 cores like R5F. So disable MMU only if it is
available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: j721e_evm_a72: Enable UHS modes
Add Configs to enable SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add Configs to enable SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
configs: j721e_evm_a72: Enable Regulator configs
Add Regulator configs to facilitate voltage switching and power
cycle support for SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add Regulator configs to facilitate voltage switching and power
cycle support for SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
arm: dts: k3-j721e-main: Disable UHS SDR104 Support
Add an sdhci-caps-mask property to only enable SDR50 and DDR50 UHS speed
modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add an sdhci-caps-mask property to only enable SDR50 and DDR50 UHS speed
modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
arm: dts: k3-j721-common-proc-board: Add Power Cycle and voltage switch support
Add PMIC ldo support for som1 and gpio regulator support for som2 to
facilitate UHS voltage switching. Also add vmmc-supply to power cycle
the card.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add PMIC ldo support for som1 and gpio regulator support for som2 to
facilitate UHS voltage switching. Also add vmmc-supply to power cycle
the card.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
mmc: am654_sdhci: Use the generic sdhci_set_control_reg function
Use the generic sdhci_set_control_reg() function for switching to UHS
modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Use the generic sdhci_set_control_reg() function for switching to UHS
modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
mmc: sdhci: Add helper functions for UHS modes
Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
mmc: Merge SD_LEGACY and MMC_LEGACY bus modes
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
power: regulator: Add Support for boot-on dts property
Set the GPIOD_IS_OUT_ACTIVE flag when boot-on flag is set in the
regulator dts.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Set the GPIOD_IS_OUT_ACTIVE flag when boot-on flag is set in the
regulator dts.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
usb: dwc3: Check that the request is valid in dwc3_gadget_giveback()
This fixes potential issues reported by klokworks:
Pointer 'req' returned from call to function 'next_request' at line 531 and
538 may be NULL and will be dereferenced in dwc3_gadget_giveback()
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This fixes potential issues reported by klokworks:
Pointer 'req' returned from call to function 'next_request' at line 531 and
538 may be NULL and will be dereferenced in dwc3_gadget_giveback()
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
usb: dwc3: explicitly free the allocated structure if dwc3_alloc_one_event_buffer() fails
This unbalanced allocation problem has been reported by klokwork:
Possible memory leak. Dynamic memory stored in 'evt' allocated through
function 'devm_kzalloc' at line 114 can be lost at line 124
The reason is that devm_kzalloc() behaves like a regular malloc() if
DEVRES is not enabled.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This unbalanced allocation problem has been reported by klokwork:
Possible memory leak. Dynamic memory stored in 'evt' allocated through
function 'devm_kzalloc' at line 114 can be lost at line 124
The reason is that devm_kzalloc() behaves like a regular malloc() if
DEVRES is not enabled.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
gpio: da8xx_gpio: Fix the _gpio_direction_output function
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.
Hence fix it by calling the _gpio_set_value function instead.
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.
Hence fix it by calling the _gpio_set_value function instead.
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
env: omap5_uevm: Use ttySx instead of ttyOx
commit 060705d06cc3 ("env: ti: boot: Use ttySx instead of ttyOx") missed
update for omap5_uevm. So update the same for omap5_uevm.
Fixes: 060705d06cc36 ("env: ti: boot: Use ttySx instead of ttyOx")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
commit 060705d06cc3 ("env: ti: boot: Use ttySx instead of ttyOx") missed
update for omap5_uevm. So update the same for omap5_uevm.
Fixes: 060705d06cc36 ("env: ti: boot: Use ttySx instead of ttyOx")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: j721e_evm_r5_defconfig: Enable ESM modules
Enable ESM modules for both PMIC and SoC side for proper watchdog
handling on the board.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Enable ESM modules for both PMIC and SoC side for proper watchdog
handling on the board.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: mach-k3: j721e_init: initialize ESM support
Initialize both ESM and ESM_PMIC support if available for the board.
If support is not available for either, a warning is printed out.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Initialize both ESM and ESM_PMIC support if available for the board.
If support is not available for either, a warning is printed out.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: dts: k3-j721e: Add ESM PMIC support for tps659413 based board
The ESM handling on J7 processor board requires routing the
MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety
error handling. The PMIC itself should then reset the board based on
receiving it. Enable the support for the board by adding the esm
node in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The ESM handling on J7 processor board requires routing the
MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety
error handling. The PMIC itself should then reset the board based on
receiving it. Enable the support for the board by adding the esm
node in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: dts: k3-k721e: Add Main domain ESM support
Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
misc: pmic_esm: Add support for PMIC ESM driver
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
misc: k3_esm: Add support for Texas Instruments K3 ESM driver
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
power: pmic: tps65941: Add support for probing the child devices
TPS65941 can have child devices under it (like the ESM support), so
probe these once the master pmic node completes probe.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
TPS65941 can have child devices under it (like the ESM support), so
probe these once the master pmic node completes probe.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
configs: am65x_evm: Fix Kernel console argument for UBI boot
When performing UBI boot the Kernel commandline 'console' argument was
not configured correctly, leading to an invalid commandline getting
passed to the Kernel. Then, with the Kernel not explicitly knowing its
initial console it would duplicate the first ~50 lines of the boot log
on the serial port.
Fix this issue by using the proper scheme to compile the Kernel arguments
for booting from UBI.
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
When performing UBI boot the Kernel commandline 'console' argument was
not configured correctly, leading to an invalid commandline getting
passed to the Kernel. Then, with the Kernel not explicitly knowing its
initial console it would duplicate the first ~50 lines of the boot log
on the serial port.
Fix this issue by using the proper scheme to compile the Kernel arguments
for booting from UBI.
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
4 years agoarm: dts: k3-j721e-mcu-wakeup: Increase HBMC bus clock to 125MHz ti2019.04 ti2019.04-rc4 ti2019.04-rc5
arm: dts: k3-j721e-mcu-wakeup: Increase HBMC bus clock to 125MHz
HBMC bus speed can be as high as 125MHz. Therefore set the functional
clock to 250MHz (which runs at twice the bus frequency) so that bus runs
at 125MHz.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
HBMC bus speed can be as high as 125MHz. Therefore set the functional
clock to 250MHz (which runs at twice the bus frequency) so that bus runs
at 125MHz.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm: dts: k3-j721e-tps65917-proc-board: change cpsw2g interface mode to rgmii-rxid
The J721E SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The J721E SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
arm: dts: k3-j721e-common-proc-board: change cpsw2g interface mode to rgmii-rxid
The J721E SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The J721E SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
arm: K3: Clean and invalidate Linux Image before jumping to Linux
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
cmd: booti: Store OS start and end info in images structure
Store the start and end of the OS image that is loaded in images
structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Store the start and end of the OS image that is loaded in images
structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
boot: arm: Enable support for custom board_prep_linux
Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: am57xx_hs_evm: Resync defconfig with non-HS defconfig
Syncing non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Syncing non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
mux: mux-uclass: Don't print error msg if autoprobe is not requested
Its not necessary that mux node needs to be autoprobed. Hence, its not
fatal not have u-boot,mux-autoprobe in DT hence reduce error/printf()
message to dev_info()
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Its not necessary that mux node needs to be autoprobed. Hence, its not
fatal not have u-boot,mux-autoprobe in DT hence reduce error/printf()
message to dev_info()
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm: K3: Increase default SYSFW image size allocation
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 269000 bytes but now needs to be grown to 276000 to make room
for the signatures attached to the board configuration data on High
Security devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 269000 bytes but now needs to be grown to 276000 to make room
for the signatures attached to the board configuration data on High
Security devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
configs: am57xx_evm_defconfig: Enable regmap and syscon in SPL
Commit 6bb2c2567135 ("configs: Enable CONFIG_BLK in am57xx_evm and am57xx_hs_evm")
which is a cherry-pick from upstream unintentionally disabled
CONFIG_SPL_REGMAP and CONFIG_SPL_SYSCON on AM57xx GP and HS defconfigs.
This breaks QSPI boot.
Therefore, re-enable CONFIG_SPL_REGMAP and CONFIG_SPL_SYSCON which are
required for QSPI driver to work in SPL.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Commit 6bb2c2567135 ("configs: Enable CONFIG_BLK in am57xx_evm and am57xx_hs_evm")
which is a cherry-pick from upstream unintentionally disabled
CONFIG_SPL_REGMAP and CONFIG_SPL_SYSCON on AM57xx GP and HS defconfigs.
This breaks QSPI boot.
Therefore, re-enable CONFIG_SPL_REGMAP and CONFIG_SPL_SYSCON which are
required for QSPI driver to work in SPL.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Revert "spl: enable caches on all armv7r platforms"
This reverts commit eda701f54c8535025943203bb070381ade6b817e.
This reverts commit eda701f54c8535025943203bb070381ade6b817e.
arm: dra7xx: Hang on any failure during IOdelay recalibration
If there is any failure during IOdelay recalibration sequence, IOs are
not guaranteed to behave as expected. So hang on any failure during the
sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
If there is any failure during IOdelay recalibration sequence, IOs are
not guaranteed to behave as expected. So hang on any failure during the
sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: dra7xx: Fix error path in iodelay recalibration
When an error is reported in __recalibrate_iodelay_start(), de-isolation
of IO doesn't happen. Because of this, undefined behaviour is observed
on many peripherals without any error. So make sure io is out of isolation
at the end of iodelay recalibration.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When an error is reported in __recalibrate_iodelay_start(), de-isolation
of IO doesn't happen. Because of this, undefined behaviour is observed
on many peripherals without any error. So make sure io is out of isolation
at the end of iodelay recalibration.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
scsi: Fix platdata read for scsi_write()
scsi_write() incorrectly calls dev_get_uclass_priv() instead of
dev_get_uclass_platdata() to read the uclass platdata. This leads to a
wrong value of max_blks being set and UFS writes above 32 MB fail.
Fix this.
Fixes: 9056fcefa5 ("scsi: Add max_bytes_per_req to scsi_platdata")
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
scsi_write() incorrectly calls dev_get_uclass_priv() instead of
dev_get_uclass_platdata() to read the uclass platdata. This leads to a
wrong value of max_blks being set and UFS writes above 32 MB fail.
Fix this.
Fixes: 9056fcefa5 ("scsi: Add max_bytes_per_req to scsi_platdata")
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
spl: enable caches on all armv7r platforms
Enabling caches in the SPL for all armv7r platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enabling caches in the SPL for all armv7r platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: mach-k3: Enable WA for R5F deadlock
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
cacheable write back/write allocate memory region and later
on software execute barrier operation (DSB or DMB). R5F may
hang at the barrier instruction.
2.When software is performing a mix of load and store operations
within a tight loop and store operations are all writing to
cacheable write back/write allocates memory regions, R5F may
hang at one of the load instruction.
To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
cacheable write back/write allocate memory region and later
on software execute barrier operation (DSB or DMB). R5F may
hang at the barrier instruction.
2.When software is performing a mix of load and store operations
within a tight loop and store operations are all writing to
cacheable write back/write allocates memory regions, R5F may
hang at one of the load instruction.
To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: dts: k3-j721e-ddr-evm-lp4-3733.dtsi: Fix file permission
Fix file permission to be rw-rw-r-- (0666)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Fix file permission to be rw-rw-r-- (0666)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm: mach-k3: sysfw-loader: Fix loading of SYSFW during HyperFlash boot
In case of HyperFlash boot on J721E, SYSFW reconfigures HyperFlash
bus clock as soon as PM configuration is sent. Therefore it is necessary
to reconfigure clocks back to boot frequency, which is currently done in
config_pm_done_callback(). But this callback is called after
extracting RM configuration pointer from FIT image and before applying
it. Since, fit_get_data_by_name() (that is used to extract RM
configuration) itself accesses HyperFlash, its necessary that clocks
are reconfigured before that. Therefore move call to
fit_get_data_by_name() after calling config_pm_done_callback().
With this HyperFlash boot works reliably at 83MHz.
Fixes: 1d9fb73cad29 ("arm: mach-k3: sysfw-loader: Call PM config done callback asap")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In case of HyperFlash boot on J721E, SYSFW reconfigures HyperFlash
bus clock as soon as PM configuration is sent. Therefore it is necessary
to reconfigure clocks back to boot frequency, which is currently done in
config_pm_done_callback(). But this callback is called after
extracting RM configuration pointer from FIT image and before applying
it. Since, fit_get_data_by_name() (that is used to extract RM
configuration) itself accesses HyperFlash, its necessary that clocks
are reconfigured before that. Therefore move call to
fit_get_data_by_name() after calling config_pm_done_callback().
With this HyperFlash boot works reliably at 83MHz.
Fixes: 1d9fb73cad29 ("arm: mach-k3: sysfw-loader: Call PM config done callback asap")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
configs: am65x_evm_a53: Enable DISPLAY_CPUINFO
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: j721e_evm_a72: Enable DISPLAY_CPUINFO
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
board: am65x: Print board name and version during boot
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
board: j721e: Print board name and version during boot
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: k3: Add support for printing CPUINFO
Add support for printing CPU info for all K3 devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support for printing CPU info for all K3 devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: dts: am574x-idk-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: dts: am57xx*: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: dts: dra72/71-evm-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: dts: am57xx-idk-common-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: dts: dra76-evm-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: dts: dra7-evm-u-boot: Refactor ipu early boot nodes into a dtsi
Refactor ipu early boot nodes into a common file so that it can
be reused across multiple dts.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Refactor ipu early boot nodes into a common file so that it can
be reused across multiple dts.
Signed-off-by: Keerthy <j-keerthy@ti.com>
ARM: dts: j721e-tps65917-proc: Use USB Port #0 in host mode
USB3 peripheral mode is broken on this board. Switching to host mode.
If peripheral mode is needed, USB3 must disabled. It can be done by
adding "ti,usb2-only" to the usbss0 node.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
USB3 peripheral mode is broken on this board. Switching to host mode.
If peripheral mode is needed, USB3 must disabled. It can be done by
adding "ti,usb2-only" to the usbss0 node.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc: Fix timeout values passed to mmc_wait_dat0()
commit 116cffeca6fe4de701d4cd5e2b5bfe5e0f1597a9 upstream.
mmc_wait_dat0() expects timeout argument to be in usec units. But some
overlying functions operate on timeout in msec units. Convert timeout
from msec to usec when passing it to mmc_wait_dat0().
This fixes 'avb' commands on BeagleBoard X15, because next chain was
failing:
get_partition() -> mmc_switch_part() -> __mmc_switch() ->
mmc_wait_dat0()
when passing incorrect timeout from __mmc_switch() to mmc_wait_dat0().
Fixes: bb98b8c5c06a ("mmc: During a switch, poll on dat0 if available and check the final status")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Tested-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
commit 116cffeca6fe4de701d4cd5e2b5bfe5e0f1597a9 upstream.
mmc_wait_dat0() expects timeout argument to be in usec units. But some
overlying functions operate on timeout in msec units. Convert timeout
from msec to usec when passing it to mmc_wait_dat0().
This fixes 'avb' commands on BeagleBoard X15, because next chain was
failing:
get_partition() -> mmc_switch_part() -> __mmc_switch() ->
mmc_wait_dat0()
when passing incorrect timeout from __mmc_switch() to mmc_wait_dat0().
Fixes: bb98b8c5c06a ("mmc: During a switch, poll on dat0 if available and check the final status")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Tested-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
configs: j721e_evm_a72: Enable the drivers required for the USB3 support
Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra
phy driver. All of them are required for USB3 support
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra
phy driver. All of them are required for USB3 support
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
ARM: dts: Add the entries required for USB3 support on USB0
Partially sync with Linux's dts to add the entries required for USB3
support on USB0.
Note that the default mode is still "peripheral" not "host". USB3 is
supported only for the host mode.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Partially sync with Linux's dts to add the entries required for USB3
support on USB0.
Note that the default mode is still "peripheral" not "host". USB3 is
supported only for the host mode.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
usb: cdns3: Never fail to bind
Ignore the error when binding the host or peripheral child. Otherwise the
board will hang.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Ignore the error when binding the host or peripheral child. Otherwise the
board will hang.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
usb: cdns3: Add PHY management
The phy management had been left out when this driver has been imported
in u-boot from linux. Bringing it back as it is required for USB3 support.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The phy management had been left out when this driver has been imported
in u-boot from linux. Bringing it back as it is required for USB3 support.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.
This is an adaptation of the linux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
wiz (wip)
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.
This is an adaptation of the linux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
wiz (wip)
phy: cadence: sierra: Make the driver more generic
This squashes several changes available in the TI linux tree:
phy: cadence: Sierra: add phy_reset hook
phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz
phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
phy: cadence: Sierra: Check for PLL lock during PHY power on
phy: cadence: Sierra: Get reset control "array" for each link
phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC
phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide
phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers
phy: cadence: Sierra: Make "clock" and "reset" optional resources
One difference with the linux driver is that the PHY is always reset after
it is powered-on. This is because role switching is not supported in u-boot
and the cable orientation is handled by the PHY reset
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This squashes several changes available in the TI linux tree:
phy: cadence: Sierra: add phy_reset hook
phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz
phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
phy: cadence: Sierra: Check for PLL lock during PHY power on
phy: cadence: Sierra: Get reset control "array" for each link
phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC
phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide
phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers
phy: cadence: Sierra: Make "clock" and "reset" optional resources
One difference with the linux driver is that the PHY is always reset after
it is powered-on. This is because role switching is not supported in u-boot
and the cable orientation is handled by the PHY reset
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
phy: cadence: Add driver for Sierra PHY
Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver (v5.2).
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver (v5.2).
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mux: mmio-based syscon mux controller
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
dm: board: complete the initialization of the muxes in initr_dm()
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: Add a new framework for multiplexer devices
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: phy: Handle gracefully NULL pointers
Prepare the way for a managed PHY API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Prepare the way for a managed PHY API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: gpio: Add a managed API to get a GPIO from the device-tree
Add managed functions to get a gpio from the devce-tree, based on a
property name (minus the '-gpios' suffix) and optionally an index.
When the device is unbound, the GPIO is automatically released and the
data structure is freed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add managed functions to get a gpio from the devce-tree, based on a
property name (minus the '-gpios' suffix) and optionally an index.
When the device is unbound, the GPIO is automatically released and the
data structure is freed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: gpio: Handle gracefully NULL pointers
Prepare the way for a managed GPIO API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Prepare the way for a managed GPIO API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: clk: Add a managed API to get reset controllers from the DT
Add managed functions to get a reset_ctl from the device-tree, based on a
name or an index.
Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl)
from the device-tree.
When the device is unbound, the reset controllers are automatically
released and the data structure is freed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add managed functions to get a reset_ctl from the device-tree, based on a
name or an index.
Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl)
from the device-tree.
When the device is unbound, the reset controllers are automatically
released and the data structure is freed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: reset: Handle gracefully NULL pointers
Prepare the way for a managed reset API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Prepare the way for a managed reset API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.
example:
muxed_clock: muxed_clock {
clocks = <&clk_provider 0>, <&clk_provider 1>;
#clock-cells = <0>;
assigned-clocks = <&muxed_clock>;
assigned-clock-parents = <&clk_provider 1>;
};
It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.
example:
muxed_clock: muxed_clock {
clocks = <&clk_provider 0>, <&clk_provider 1>;
#clock-cells = <0>;
assigned-clocks = <&muxed_clock>;
assigned-clock-parents = <&clk_provider 1>;
};
It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: clk: Add a managed API to get clocks from the device-tree
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
drivers: clk: Handle gracefully NULL pointers
Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
regmap: Add support for regmap fields
A regmap field is an abstraction available in Linux. It provides to access
bitfields in a regmap without having to worry about shifts and masks.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
A regmap field is an abstraction available in Linux. It provides to access
bitfields in a regmap without having to worry about shifts and masks.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
regmap: Allow providing read/write callbacks through struct regmap_config
Some linux drivers provide their own read/write functions to access data
from/of the regmap. Adding support for it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Some linux drivers provide their own read/write functions to access data
from/of the regmap. Adding support for it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
regmap: Add devm_regmap_init()
Most of new linux drivers are using managed-API to allocate resources. To
ease porting drivers from linux to u-boot, introduce devm_regmap_init() as
a managed API to get a regmap from the device tree.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Most of new linux drivers are using managed-API to allocate resources. To
ease porting drivers from linux to u-boot, introduce devm_regmap_init() as
a managed API to get a regmap from the device tree.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
dm: device: Fix typo in the non-DEVRES version of devm_kmalloc_array()
When DEVRES is not set, devm_kmalloc_array() is spelled
devm_kmaloc_array() (with one 'l' only).
Fixing it so that the name is the same with and without DEVRES.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
When DEVRES is not set, devm_kmalloc_array() is spelled
devm_kmaloc_array() (with one 'l' only).
Fixing it so that the name is the same with and without DEVRES.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
clk: Fix error check in clk_set_default_parents()
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
usb: cdns3: ep0: Fix flush/invalidate of cache ops
flush_dcache_range() and invalidate_dcache_range() take a address range
(start and stop addr), not start address and size. Fix this in cdns ep0
driver code.
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
flush_dcache_range() and invalidate_dcache_range() take a address range
(start and stop addr), not start address and size. Fix this in cdns ep0
driver code.
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocks
Update the dummy clock names to use unique identifiers. Otherwise the
previous node just gets overwitten by the next one with the same name.
This fixes eMMC boot not working on J721e-evm.
Tested-by: Praneeth Bajjuri <praneeth@ti.com>
Fixes d024b81399 ("arm: dts: k3-j721e-common-proc-board: Enable USB0 in
peripheral mode")
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Update the dummy clock names to use unique identifiers. Otherwise the
previous node just gets overwitten by the next one with the same name.
This fixes eMMC boot not working on J721e-evm.
Tested-by: Praneeth Bajjuri <praneeth@ti.com>
Fixes d024b81399 ("arm: dts: k3-j721e-common-proc-board: Enable USB0 in
peripheral mode")
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
ram: k3-j721e: Update to the latest DDR driver
Create a TI wrapper logic for DDRSS with J721E devices using the
DDR controller and phy driver that is already available. With this
drop the existing hack driver for DDRSS.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Create a TI wrapper logic for DDRSS with J721E devices using the
DDR controller and phy driver that is already available. With this
drop the existing hack driver for DDRSS.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: k3-j721e: Add support for J721E DDR controller
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: dts: k3-j721e: Use the auto generated DDR configuration
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
dt-bindings: memory-controller: Introduce J721E DDRSS bindings
Add DT binding documentation for DDR sub system present on J721E device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add DT binding documentation for DDR sub system present on J721E device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: k3-am654: Do not rely on default values for certain DDR register
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: k3-am654: add support for LPDDR4 and DDR3L DDRs
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR types
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR types
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
armv7r: dts: am654-base-board: Rename 1600MHz to 1600MTs in dtsi filename
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
cmd: ti: ddr3: Move the print statement after test
If the ECC is enabled over the entire memory region, we need to ensure
the printf/put calls do not modify the stack after ECC is disabled.
Moved the printf/put statements after ECC is enabled.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
If the ECC is enabled over the entire memory region, we need to ensure
the printf/put calls do not modify the stack after ECC is disabled.
Moved the printf/put statements after ECC is enabled.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
arm: omap: emif-common: Fix memory priming for ECC
Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
arm: omap: emif-common: Disable interleaving
If ECC is enabled, we need to ensure interleaving is disabled for higher
address space.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
If ECC is enabled, we need to ensure interleaving is disabled for higher
address space.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
cmd: ti: ddr3: Fix ecc address calculation
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr cmd driver is assuming the register
contains the start address and size of the DDR address space. Because
of this some valid ecc addresses are errored out as invalid address.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr cmd driver is assuming the register
contains the start address and size of the DDR address space. Because
of this some valid ecc addresses are errored out as invalid address.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: omap: emif-common: Fix ecc address calculation
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
net: ti: cpsw: fix network fail after adding "max-speed" handling
The struct cpsw_slave_data->max_speed is not cleared after memory
allocation which causes cpsw initialization failure. Hence, clear it.
Tested-by: Suman Anna <s-anna@ti.com>
Reported-by: Suman Anna <s-anna@ti.com>
Fixes: af94b98b7793 ('net: ti: cpsw: add support ... eth "max-speed" dt property')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The struct cpsw_slave_data->max_speed is not cleared after memory
allocation which causes cpsw initialization failure. Hence, clear it.
Tested-by: Suman Anna <s-anna@ti.com>
Reported-by: Suman Anna <s-anna@ti.com>
Fixes: af94b98b7793 ('net: ti: cpsw: add support ... eth "max-speed" dt property')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
remoteproc: ipu_rproc: Use reserved memory for IOMMU page tables
The memory for IPU IOMMU page tables had previously been placed
dynamically at the end of each remoteproc's carveout memory region.
This memory region is typically used for all the firmware image
sections. Use a separate 1 MB reserved carveout memory region and
partition this memory statically for the IOMMU page table memories.
256 KB of memory is currently reserved per remote core providing
support for the L1 page table (16 KB) and upto 240 L2 page tables
(240 KB). A total of 1 MB memory region at 0x95700000 just before
all the current TI DRA7 remoteproc CMA/DMA pools is reserved for
this purpose. This region needs to be added as a reserved-memory
node with a "no-map" property so that the memory is not modified
by the kernel.
TODO:
Reserve these carveouts through dts in the future instead of
hard-coding in the driver.
Signed-off-by: Subash Lakkimsetti <x0091084@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
[s-anna@ti.com: Update comments and patch description]
Signed-off-by: Suman Anna <s-anna@ti.com>
The memory for IPU IOMMU page tables had previously been placed
dynamically at the end of each remoteproc's carveout memory region.
This memory region is typically used for all the firmware image
sections. Use a separate 1 MB reserved carveout memory region and
partition this memory statically for the IOMMU page table memories.
256 KB of memory is currently reserved per remote core providing
support for the L1 page table (16 KB) and upto 240 L2 page tables
(240 KB). A total of 1 MB memory region at 0x95700000 just before
all the current TI DRA7 remoteproc CMA/DMA pools is reserved for
this purpose. This region needs to be added as a reserved-memory
node with a "no-map" property so that the memory is not modified
by the kernel.
TODO:
Reserve these carveouts through dts in the future instead of
hard-coding in the driver.
Signed-off-by: Subash Lakkimsetti <x0091084@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
[s-anna@ti.com: Update comments and patch description]
Signed-off-by: Suman Anna <s-anna@ti.com>
configs: j721e_evm_a72: Enable configs for UFS
Enable SCSI and UFS related configs.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Enable SCSI and UFS related configs.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
env: ti: Add environment variables to boot from UFS
Add environment variables to boot kernel from a filesystem contained in
the 2nd UFS LUN. The user can boot from a ufs filesystem just by
entering the following commands.
=> setenv boot ufs
=> boot
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add environment variables to boot kernel from a filesystem contained in
the 2nd UFS LUN. The user can boot from a ufs filesystem just by
entering the following commands.
=> setenv boot ufs
=> boot
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
cmd: Add Support for UFS commands
Add Support for commands to initialize and configure UFS devices.
TODO: Add Support for commands to resize and reconfigure LUNs
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add Support for commands to initialize and configure UFS devices.
TODO: Add Support for commands to resize and reconfigure LUNs
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
arm: dts: k3-j721e-main: Add UFS nodes
Add TI UFS glue layer and Cadence UFS Host controller DT nodes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add TI UFS glue layer and Cadence UFS Host controller DT nodes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
ufs: Add glue layer driver for TI J721E devices
Add glue layer driver for the controller present on TI's J721E devices.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add glue layer driver for the controller present on TI's J721E devices.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>