dump additional registers
authorVenkateswara Rao Mandela <venkat.mandela@ti.com>
Mon, 3 Apr 2017 13:06:05 +0000 (18:36 +0530)
committerVenkateswara Rao Mandela <venkat.mandela@ti.com>
Mon, 3 Apr 2017 13:06:05 +0000 (18:36 +0530)
debug/dss_clockdumps.sh

index acbeff4c5a4d1e25b493fdcad91d1a6182ae6f15..9c992d982ab81110c98a519ce72cf8a84bfa5e82 100755 (executable)
@@ -225,8 +225,10 @@ dump_dss_clk_mux() {
 dss_clk_print() {
        echo "========================================================"
        echo "Clock O/P of MUXes"
-        dss_clk=$($OMAPCONF show dpll | grep -A3 "H12 Output" | grep Speed | head -1 | cut -d '|' -f6)
+       dss_clk=$($OMAPCONF show dpll | grep -A3 "H12 Output" | grep Speed | head -1 | cut -d '|' -f6)
        dss_clk=$(( $dss_clk * 1000000 ))
+       echo "DPLL PER H12 Output $dss_clk"
+       dump_reg "0x4A00815C" "CM_DIV_H12_DPLL_PER"
 
         dss_pll=0x4a002538
         val=0x$($OMAPCONF read "$dss_pll")
@@ -244,6 +246,9 @@ dss_clk_print() {
                lcd2_clk=`check_field $val 12 1 $dss_clk $dsib_clk`
                lcd3_clk=`check_field $val 19 1 $dss_clk $dsic_clk`
                hdmi_clk=`check_field $val  7 3 $dss_clk $dsia_clk $dsib_clk $hdmi_clk $dsic_clk`
+
+       dump_reg "0x58001804" "DISPC_DIVISOR"
+
        echo " 2: LCD1 clk : "  $lcd1_clk
        echo " 3: LCD2 clk : "  $lcd2_clk
        echo "10: LCD3 clk : "  $lcd3_clk