dump dss power domain control registers
authorVenkateswara Rao Mandela <venkat.mandela@ti.com>
Thu, 30 Mar 2017 08:17:17 +0000 (13:47 +0530)
committerVenkateswara Rao Mandela <venkat.mandela@ti.com>
Thu, 30 Mar 2017 08:36:23 +0000 (14:06 +0530)
debug/dss_clockdumps.sh

index fb1d5bced494ad0da256a2bc1b366393094a5b9a..300b71928bc46117febde712fc26c4279a68a657 100755 (executable)
@@ -183,6 +183,12 @@ inst=$1
        eval "$inst"_m7=0
 }
 
+dump_dss_clk_regs() {
+
+    dump_reg "0x4A009100" "CM_DSS_CLKSTCTRL"
+    dump_reg "0x4A009120" "CM_DSS_DSS_CLKCTRL"
+}
+
 dump_dss_clk_mux() {
        dss_pll=0x4a002538
         val=0x$($OMAPCONF read "$dss_pll")
@@ -274,6 +280,8 @@ dss_pll=0x4a002538
 
 dump_dss_clk_mux
 
+dump_dss_clk_regs
+
 init_dpll_values video1
 init_dpll_values video2
 init_dpll_values hdmi