c168bfa1a1fb5ffeace00d10d9df4259f01925a7
[i3-mote/i3-mote.git] / Basic-Test-Package / MSP432 / Test_MSP432_3wSPI_M25P40 / startup_msp432p401r_ccs.c
1 /*
2  * -------------------------------------------
3  *    MSP432 DriverLib - v3_10_00_09 
4  * -------------------------------------------
5 */
7 #include <stdint.h>
9 /* Forward declaration of the default fault handlers. */
10 static void resetISR(void);
11 static void nmiISR(void);
12 static void faultISR(void);
13 static void defaultISR(void);
16 /* External declaration for the reset handler that is to be called when the */
17 /* processor is started                                                     */
18 extern void _c_int00(void);
20 /* External declaration for system initialization function                  */
21 extern void SystemInit(void);
23 /* Linker variable that marks the top of the stack. */
24 extern unsigned long __STACK_END;
27 /* External declarations for the interrupt handlers used by the application. */
28 // extern void EUSCIB0_IRQHandler (void);
29 extern void EUSCIA2_IRQHandler (void);
30 extern void SysTick_Handler(void);
32 /* Interrupt vector table.  Note that the proper constructs must be placed on this to  */
33 /* ensure that it ends up at physical address 0x0000.0000 or at the start of          */
34 /* the program if located at a start address other than 0.                            */
35 #pragma RETAIN(interruptVectors)
36 #pragma DATA_SECTION(interruptVectors, ".intvecs")
37 void (* const interruptVectors[])(void) =
38 {
39     (void (*)(void))((uint32_t)&__STACK_END),
40                                             /* The initial stack pointer */
41     resetISR,                               /* The reset handler         */
42     nmiISR,                                 /* The NMI handler           */
43     faultISR,                               /* The hard fault handler    */
44     defaultISR,                             /* The MPU fault handler     */
45     defaultISR,                             /* The bus fault handler     */
46     defaultISR,                             /* The usage fault handler   */
47     0,                                      /* Reserved                  */
48     0,                                      /* Reserved                  */
49     0,                                      /* Reserved                  */
50     0,                                      /* Reserved                  */
51     defaultISR,                             /* SVCall handler            */
52     defaultISR,                             /* Debug monitor handler     */
53     0,                                      /* Reserved                  */
54     defaultISR,                             /* The PendSV handler        */
55         SysTick_Handler,                        /* The SysTick handler       */
56     defaultISR,                             /* PSS ISR                   */
57     defaultISR,                             /* CS ISR                    */
58     defaultISR,                             /* PCM ISR                   */
59     defaultISR,                             /* WDT ISR                   */
60     defaultISR,                             /* FPU ISR                   */
61     defaultISR,                             /* FLCTL ISR                 */
62     defaultISR,                             /* COMP0 ISR                 */
63     defaultISR,                             /* COMP1 ISR                 */
64     defaultISR,                             /* TA0_0 ISR                 */
65     defaultISR,                             /* TA0_N ISR                 */
66     defaultISR,                             /* TA1_0 ISR                 */
67     defaultISR,                             /* TA1_N ISR                 */
68     defaultISR,                             /* TA2_0 ISR                 */
69     defaultISR,                             /* TA2_N ISR                 */
70     defaultISR,                             /* TA3_0 ISR                 */
71     defaultISR,                             /* TA3_N ISR                 */
72     defaultISR,                             /* EUSCIA0 ISR               */
73     defaultISR,                             /* EUSCIA1 ISR               */
74         EUSCIA2_IRQHandler,                     /* EUSCIA2 ISR               */
75     defaultISR,                             /* EUSCIA3 ISR               */
76         defaultISR,                             /* EUSCIB0 ISR               */
77     defaultISR,                             /* EUSCIB1 ISR               */
78     defaultISR,                             /* EUSCIB2 ISR               */
79     defaultISR,                             /* EUSCIB3 ISR               */
80     defaultISR,                             /* ADC14 ISR                 */
81     defaultISR,                             /* T32_INT1 ISR              */
82     defaultISR,                             /* T32_INT2 ISR              */
83     defaultISR,                             /* T32_INTC ISR              */
84     defaultISR,                             /* AES ISR                   */
85     defaultISR,                             /* RTC ISR                   */
86     defaultISR,                             /* DMA_ERR ISR               */
87     defaultISR,                             /* DMA_INT3 ISR              */
88     defaultISR,                             /* DMA_INT2 ISR              */
89     defaultISR,                             /* DMA_INT1 ISR              */
90     defaultISR,                             /* DMA_INT0 ISR              */
91     defaultISR,                             /* PORT1 ISR                 */
92     defaultISR,                             /* PORT2 ISR                 */
93     defaultISR,                             /* PORT3 ISR                 */
94     defaultISR,                             /* PORT4 ISR                 */
95     defaultISR,                             /* PORT5 ISR                 */
96     defaultISR,                             /* PORT6 ISR                 */
97     defaultISR,                             /* Reserved 41               */
98     defaultISR,                             /* Reserved 42               */
99     defaultISR,                             /* Reserved 43               */
100     defaultISR,                             /* Reserved 44               */
101     defaultISR,                             /* Reserved 45               */
102     defaultISR,                             /* Reserved 46               */
103     defaultISR,                             /* Reserved 47               */
104     defaultISR,                             /* Reserved 48               */
105     defaultISR,                             /* Reserved 49               */
106     defaultISR,                             /* Reserved 50               */
107     defaultISR,                             /* Reserved 51               */
108     defaultISR,                             /* Reserved 52               */
109     defaultISR,                             /* Reserved 53               */
110     defaultISR,                             /* Reserved 54               */
111     defaultISR,                             /* Reserved 55               */
112     defaultISR,                             /* Reserved 56               */
113     defaultISR,                             /* Reserved 57               */
114     defaultISR,                             /* Reserved 58               */
115     defaultISR,                             /* Reserved 59               */
116     defaultISR,                             /* Reserved 60               */
117     defaultISR,                             /* Reserved 61               */
118     defaultISR,                             /* Reserved 62               */
119     defaultISR                              /* Reserved 63               */
120 };
123 /* This is the code that gets called when the processor first starts execution */
124 /* following a reset event.  Only the absolutely necessary set is performed,   */
125 /* after which the application supplied entry() routine is called.  Any fancy  */
126 /* actions (such as making decisions based on the reset cause register, and    */
127 /* resetting the bits in that register) are left solely in the hands of the    */
128 /* application.                                                                */
129 void resetISR(void)
131     SystemInit();
133     /* Jump to the CCS C Initialization Routine. */
134     __asm("    .global _c_int00\n"
135           "    b.w     _c_int00");
138 /* This is the code that gets called when the processor receives a NMI.  This  */
139 /* simply enters an infinite loop, preserving the system state for examination */
140 /* by a debugger.                                                              */
141 static void nmiISR(void)
143     /* Fault trap exempt from ULP advisor */
144     #pragma diag_push
145     #pragma CHECK_ULP("-2.1")
147     /* Enter an infinite loop. */
148     while(1)
149     {
150     }
152     #pragma diag_pop
156 /* This is the code that gets called when the processor receives a fault        */
157 /* interrupt.  This simply enters an infinite loop, preserving the system state */
158 /* for examination by a debugger.                                               */
159 static void faultISR(void)
161     /* Fault trap exempt from ULP advisor */
162     #pragma diag_push
163     #pragma CHECK_ULP("-2.1")
165     /* Enter an infinite loop. */
166     while(1)
167     {
168     }
170     #pragma diag_pop
174 /* This is the code that gets called when the processor receives an unexpected  */
175 /* interrupt.  This simply enters an infinite loop, preserving the system state */
176 /* for examination by a debugger.                                               */
177 static void defaultISR(void)
179     /* Fault trap exempt from ULP advisor */
180     #pragma diag_push
181     #pragma CHECK_ULP("-2.1")
183     /* Enter an infinite loop. */
184     while(1)
185     {
186     }
188     #pragma diag_pop