[i3-mote/i3-mote.git] / Basic-Test-Package / MSP432 / Test_MSP432_ClockSystem / startup_msp432p401r_ccs.c
1 /*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37 //*****************************************************************************
38 //
39 // Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
40 //
41 // Redistribution and use in source and binary forms, with or without
42 // modification, are permitted provided that the following conditions
43 // are met:
44 //
45 // Redistributions of source code must retain the above copyright
46 // notice, this list of conditions and the following disclaimer.
47 //
48 // Redistributions in binary form must reproduce the above copyright
49 // notice, this list of conditions and the following disclaimer in the
50 // documentation and/or other materials provided with the
51 // distribution.
52 //
53 // Neither the name of Texas Instruments Incorporated nor the names of
54 // its contributors may be used to endorse or promote products derived
55 // from this software without specific prior written permission.
56 //
57 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
60 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
63 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
64 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
67 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68 //
69 // MSP432 Family Interrupt Vector Table for CGT
70 //
71 //****************************************************************************
73 #include <stdint.h>
75 /* Forward declaration of the default fault handlers. */
76 static void resetISR(void);
77 static void nmiISR(void);
78 static void faultISR(void);
79 static void defaultISR(void);
82 /* External declaration for the reset handler that is to be called when the */
83 /* processor is started */
84 extern void _c_int00(void);
86 /* External declaration for system initialization function */
87 extern void SystemInit(void);
89 /* Linker variable that marks the top of the stack. */
90 extern unsigned long __STACK_END;
93 /* External declarations for the interrupt handlers used by the application. */
94 extern void SysTick_Handler(void);
97 /* Interrupt vector table. Note that the proper constructs must be placed on this to */
98 /* ensure that it ends up at physical address 0x0000.0000 or at the start of */
99 /* the program if located at a start address other than 0. */
100 #pragma RETAIN(interruptVectors)
101 #pragma DATA_SECTION(interruptVectors, ".intvecs")
102 void (* const interruptVectors[])(void) =
103 {
104 (void (*)(void))((uint32_t)&__STACK_END),
105 /* The initial stack pointer */
106 resetISR, /* The reset handler */
107 nmiISR, /* The NMI handler */
108 faultISR, /* The hard fault handler */
109 defaultISR, /* The MPU fault handler */
110 defaultISR, /* The bus fault handler */
111 defaultISR, /* The usage fault handler */
112 0, /* Reserved */
113 0, /* Reserved */
114 0, /* Reserved */
115 0, /* Reserved */
116 defaultISR, /* SVCall handler */
117 defaultISR, /* Debug monitor handler */
118 0, /* Reserved */
119 defaultISR, /* The PendSV handler */
120 SysTick_Handler, /* The SysTick handler */
121 defaultISR, /* PSS ISR */
122 defaultISR, /* CS ISR */
123 defaultISR, /* PCM ISR */
124 defaultISR, /* WDT ISR */
125 defaultISR, /* FPU ISR */
126 defaultISR, /* FLCTL ISR */
127 defaultISR, /* COMP0 ISR */
128 defaultISR, /* COMP1 ISR */
129 defaultISR, /* TA0_0 ISR */
130 defaultISR, /* TA0_N ISR */
131 defaultISR, /* TA1_0 ISR */
132 defaultISR, /* TA1_N ISR */
133 defaultISR, /* TA2_0 ISR */
134 defaultISR, /* TA2_N ISR */
135 defaultISR, /* TA3_0 ISR */
136 defaultISR, /* TA3_N ISR */
137 defaultISR, /* EUSCIA0 ISR */
138 defaultISR, /* EUSCIA1 ISR */
139 defaultISR, /* EUSCIA2 ISR */
140 defaultISR, /* EUSCIA3 ISR */
141 defaultISR, /* EUSCIB0 ISR */
142 defaultISR, /* EUSCIB1 ISR */
143 defaultISR, /* EUSCIB2 ISR */
144 defaultISR, /* EUSCIB3 ISR */
145 defaultISR, /* ADC14 ISR */
146 defaultISR, /* T32_INT1 ISR */
147 defaultISR, /* T32_INT2 ISR */
148 defaultISR, /* T32_INTC ISR */
149 defaultISR, /* AES ISR */
150 defaultISR, /* RTC ISR */
151 defaultISR, /* DMA_ERR ISR */
152 defaultISR, /* DMA_INT3 ISR */
153 defaultISR, /* DMA_INT2 ISR */
154 defaultISR, /* DMA_INT1 ISR */
155 defaultISR, /* DMA_INT0 ISR */
156 defaultISR, /* PORT1 ISR */
157 defaultISR, /* PORT2 ISR */
158 defaultISR, /* PORT3 ISR */
159 defaultISR, /* PORT4 ISR */
160 defaultISR, /* PORT5 ISR */
161 defaultISR, /* PORT6 ISR */
162 defaultISR, /* Reserved 41 */
163 defaultISR, /* Reserved 42 */
164 defaultISR, /* Reserved 43 */
165 defaultISR, /* Reserved 44 */
166 defaultISR, /* Reserved 45 */
167 defaultISR, /* Reserved 46 */
168 defaultISR, /* Reserved 47 */
169 defaultISR, /* Reserved 48 */
170 defaultISR, /* Reserved 49 */
171 defaultISR, /* Reserved 50 */
172 defaultISR, /* Reserved 51 */
173 defaultISR, /* Reserved 52 */
174 defaultISR, /* Reserved 53 */
175 defaultISR, /* Reserved 54 */
176 defaultISR, /* Reserved 55 */
177 defaultISR, /* Reserved 56 */
178 defaultISR, /* Reserved 57 */
179 defaultISR, /* Reserved 58 */
180 defaultISR, /* Reserved 59 */
181 defaultISR, /* Reserved 60 */
182 defaultISR, /* Reserved 61 */
183 defaultISR, /* Reserved 62 */
184 defaultISR /* Reserved 63 */
185 };
188 /* This is the code that gets called when the processor first starts execution */
189 /* following a reset event. Only the absolutely necessary set is performed, */
190 /* after which the application supplied entry() routine is called. Any fancy */
191 /* actions (such as making decisions based on the reset cause register, and */
192 /* resetting the bits in that register) are left solely in the hands of the */
193 /* application. */
194 void resetISR(void)
195 {
196 SystemInit();
198 /* Jump to the CCS C Initialization Routine. */
199 __asm(" .global _c_int00\n"
200 " b.w _c_int00");
201 }
203 /* This is the code that gets called when the processor receives a NMI. This */
204 /* simply enters an infinite loop, preserving the system state for examination */
205 /* by a debugger. */
206 static void nmiISR(void)
207 {
208 /* Fault trap exempt from ULP advisor */
209 #pragma diag_push
210 #pragma CHECK_ULP("-2.1")
212 /* Enter an infinite loop. */
213 while(1)
214 {
215 }
217 #pragma diag_pop
218 }
221 /* This is the code that gets called when the processor receives a fault */
222 /* interrupt. This simply enters an infinite loop, preserving the system state */
223 /* for examination by a debugger. */
224 static void faultISR(void)
225 {
226 /* Fault trap exempt from ULP advisor */
227 #pragma diag_push
228 #pragma CHECK_ULP("-2.1")
230 /* Enter an infinite loop. */
231 while(1)
232 {
233 }
235 #pragma diag_pop
236 }
239 /* This is the code that gets called when the processor receives an unexpected */
240 /* interrupt. This simply enters an infinite loop, preserving the system state */
241 /* for examination by a debugger. */
242 static void defaultISR(void)
243 {
244 /* Fault trap exempt from ULP advisor */
245 #pragma diag_push
246 #pragma CHECK_ULP("-2.1")
248 /* Enter an infinite loop. */
249 while(1)
250 {
251 }
253 #pragma diag_pop
254 }