[i3-mote/i3-mote.git] / Basic-Test-Package / MSP432 / Test_MSP432_DebugUART_EchoPC / system_msp432p401r.c
1 /*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37 /**************************************************************************//**
38 * @file system_msp432p401r.c
39 * @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
40 * MSP432P401R
41 * @version V1.00
42 * @date 20-Oct-2015
43 *
44 * @note View configuration instructions embedded in comments
45 *
46 ******************************************************************************/
47 //*****************************************************************************
48 //
49 // Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
50 //
51 // Redistribution and use in source and binary forms, with or without
52 // modification, are permitted provided that the following conditions
53 // are met:
54 //
55 // Redistributions of source code must retain the above copyright
56 // notice, this list of conditions and the following disclaimer.
57 //
58 // Redistributions in binary form must reproduce the above copyright
59 // notice, this list of conditions and the following disclaimer in the
60 // documentation and/or other materials provided with the
61 // distribution.
62 //
63 // Neither the name of Texas Instruments Incorporated nor the names of
64 // its contributors may be used to endorse or promote products derived
65 // from this software without specific prior written permission.
66 //
67 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
68 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
69 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
70 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
71 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
72 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
74 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
75 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78 //
79 //*****************************************************************************
81 #include <stdint.h>
82 #include "msp.h"
84 /*--------------------- Configuration Instructions ----------------------------
85 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
86 #define __HALT_WDT 1
87 2. Insert your desired CPU frequency in Hz at:
88 #define __SYSTEM_CLOCK 3000000
89 3. If you prefer the DC-DC power regulator (more efficient at higher
90 frequencies), set the __REGULATOR to 1:
91 #define __REGULATOR 1
92 *---------------------------------------------------------------------------*/
94 /*--------------------- Watchdog Timer Configuration ------------------------*/
95 // Halt the Watchdog Timer
96 // <0> Do not halt the WDT
97 // <1> Halt the WDT
98 #define __HALT_WDT 1
100 /*--------------------- CPU Frequency Configuration -------------------------*/
101 // CPU Frequency
102 // <1500000> 1.5 MHz
103 // <3000000> 3 MHz
104 // <12000000> 12 MHz
105 // <24000000> 24 MHz
106 // <48000000> 48 MHz
107 #define __SYSTEM_CLOCK 1500000
109 /*--------------------- Power Regulator Configuration -----------------------*/
110 // Power Regulator Mode
111 // <0> LDO
112 // <1> DC-DC
113 #define __REGULATOR 1
115 /*----------------------------------------------------------------------------
116 Define clocks, used for SystemCoreClockUpdate()
117 *---------------------------------------------------------------------------*/
118 #define __VLOCLK 10000
119 #define __MODCLK 24000000
120 #define __LFXT 32768
121 #define __HFXT 48000000
123 /*----------------------------------------------------------------------------
124 Clock Variable definitions
125 *---------------------------------------------------------------------------*/
126 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
128 /**
129 * Update SystemCoreClock variable
130 *
131 * @param none
132 * @return none
133 *
134 * @brief Updates the SystemCoreClock with current core Clock
135 * retrieved from cpu registers.
136 */
137 void SystemCoreClockUpdate(void)
138 {
139 uint32_t source, divider;
140 uint8_t dividerValue;
142 float dcoConst;
143 int32_t calVal;
144 uint32_t centeredFreq;
145 int16_t dcoTune;
147 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
148 dividerValue = 1 << divider;
149 source = CS->CTL1 & CS_CTL1_SELM_MASK;
151 switch(source)
152 {
153 case CS_CTL1_SELM__LFXTCLK:
154 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
155 {
156 // Clear interrupt flag
157 CS->KEY = CS_KEY_VAL;
158 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
159 CS->KEY = 1;
161 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
162 {
163 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
164 {
165 SystemCoreClock = (128000 / dividerValue);
166 }
167 else
168 {
169 SystemCoreClock = (32000 / dividerValue);
170 }
171 }
172 else
173 {
174 SystemCoreClock = __LFXT / dividerValue;
175 }
176 }
177 else
178 {
179 SystemCoreClock = __LFXT / dividerValue;
180 }
181 break;
182 case CS_CTL1_SELM__VLOCLK:
183 SystemCoreClock = __VLOCLK / dividerValue;
184 break;
185 case CS_CTL1_SELM__REFOCLK:
186 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
187 {
188 SystemCoreClock = (128000 / dividerValue);
189 }
190 else
191 {
192 SystemCoreClock = (32000 / dividerValue);
193 }
194 break;
195 case CS_CTL1_SELM__DCOCLK:
196 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
198 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
199 {
200 case CS_CTL0_DCORSEL_0:
201 centeredFreq = 1500000;
202 break;
203 case CS_CTL0_DCORSEL_1:
204 centeredFreq = 3000000;
205 break;
206 case CS_CTL0_DCORSEL_2:
207 centeredFreq = 6000000;
208 break;
209 case CS_CTL0_DCORSEL_3:
210 centeredFreq = 12000000;
211 break;
212 case CS_CTL0_DCORSEL_4:
213 centeredFreq = 24000000;
214 break;
215 case CS_CTL0_DCORSEL_5:
216 centeredFreq = 48000000;
217 break;
218 }
220 if(dcoTune == 0)
221 {
222 SystemCoreClock = centeredFreq;
223 }
224 else
225 {
227 if(dcoTune & 0x1000)
228 {
229 dcoTune = dcoTune | 0xF000;
230 }
232 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
233 {
234 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
235 calVal = TLV->DCOER_FCAL_RSEL04;
236 }
237 /* Internal Resistor */
238 else
239 {
240 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
241 calVal = TLV->DCOIR_FCAL_RSEL04;
242 }
244 SystemCoreClock = (uint32_t) ((centeredFreq)
245 / (1
246 - ((dcoConst * dcoTune)
247 / (8 * (1 + dcoConst * (768 - calVal))))));
248 }
249 break;
250 case CS_CTL1_SELM__MODOSC:
251 SystemCoreClock = __MODCLK / dividerValue;
252 break;
253 case CS_CTL1_SELM__HFXTCLK:
254 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
255 {
256 // Clear interrupt flag
257 CS->KEY = CS_KEY_VAL;
258 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
259 CS->KEY = 1;
261 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
262 {
263 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
264 {
265 SystemCoreClock = (128000 / dividerValue);
266 }
267 else
268 {
269 SystemCoreClock = (32000 / dividerValue);
270 }
271 }
272 else
273 {
274 SystemCoreClock = __HFXT / dividerValue;
275 }
276 }
277 else
278 {
279 SystemCoreClock = __HFXT / dividerValue;
280 }
281 break;
282 }
283 }
285 /**
286 * Initialize the system
287 *
288 * @param none
289 * @return none
290 *
291 * @brief Setup the microcontroller system.
292 *
293 * Performs the following initialization steps:
294 * 1. Enables the FPU
295 * 2. Halts the WDT if requested
296 * 3. Enables all SRAM banks
297 * 4. Sets up power regulator and VCORE
298 * 5. Enable Flash wait states if needed
299 * 6. Change MCLK to desired frequency
300 * 7. Enable Flash read buffering
301 */
302 void SystemInit(void)
303 {
304 // Enable FPU if used
305 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
306 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
307 (3UL << 11 * 2)); /* Set CP11 Full Access */
308 #endif
310 #if (__HALT_WDT == 1)
311 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
312 #endif
314 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
316 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
317 // Default VCORE is LDO VCORE0 so no change necessary
319 // Switches LDO VCORE0 to DCDC VCORE0 if requested
320 #if __REGULATOR
321 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
322 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
323 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
324 #endif
326 // No flash wait states necessary
328 // DCO = 1.5 MHz; MCLK = source
329 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
330 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
331 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
332 CS->KEY = 0;
334 // Set Flash Bank read buffering
335 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
336 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
338 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
339 // Default VCORE is LDO VCORE0 so no change necessary
341 // Switches LDO VCORE0 to DCDC VCORE0 if requested
342 #if __REGULATOR
343 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
344 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
345 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
346 #endif
348 // No flash wait states necessary
350 // DCO = 3 MHz; MCLK = source
351 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
352 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
353 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
354 CS->KEY = 0;
356 // Set Flash Bank read buffering
357 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
358 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
360 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
361 // Default VCORE is LDO VCORE0 so no change necessary
363 // Switches LDO VCORE0 to DCDC VCORE0 if requested
364 #if __REGULATOR
365 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
366 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
367 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
368 #endif
370 // No flash wait states necessary
372 // DCO = 12 MHz; MCLK = source
373 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
374 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
375 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
376 CS->KEY = 0;
378 // Set Flash Bank read buffering
379 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
380 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
382 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
383 // Default VCORE is LDO VCORE0 so no change necessary
385 // Switches LDO VCORE0 to DCDC VCORE0 if requested
386 #if __REGULATOR
387 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
388 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
389 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
390 #endif
392 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
393 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
394 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
396 // DCO = 24 MHz; MCLK = source
397 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
398 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
399 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
400 CS->KEY = 0;
402 // Set Flash Bank read buffering
403 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
404 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
406 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
407 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
408 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
409 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
410 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
412 // Switches LDO VCORE1 to DCDC VCORE1 if requested
413 #if __REGULATOR
414 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
415 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
416 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
417 #endif
419 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
420 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
421 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
423 // DCO = 48 MHz; MCLK = source
424 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
425 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
426 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
427 CS->KEY = 0;
429 // Set Flash Bank read buffering
430 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
431 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
432 #endif
434 }