MSP430 BSL shared RST (JTAG chain)

diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd
new file mode 100644 (file)
index 0000000..a0ba06b
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd
@@ -0,0 +1,144 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated                           */
+/*  All rights reserved.                                                        */
+/*                                                                              */
+/*  Redistribution and use in source and binary forms, with or without          */
+/*  modification, are permitted provided that the following conditions          */
+/*  are met:                                                                    */
+/*                                                                              */
+/*  *  Redistributions of source code must retain the above copyright           */
+/*     notice, this list of conditions and the following disclaimer.            */
+/*                                                                              */
+/*  *  Redistributions in binary form must reproduce the above copyright        */
+/*     notice, this list of conditions and the following disclaimer in the      */
+/*     documentation and/or other materials provided with the distribution.     */
+/*                                                                              */
+/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
+/*     its contributors may be used to endorse or promote products derived      */
+/*     from this software without specific prior written permission.            */
+/*                                                                              */
+/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
+/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
+/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
+/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
+/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
+/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
+/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
+/* ============================================================================ */
+
+/******************************************************************************/
+/* lnk_msp430g2221.cmd - LINKER COMMAND FILE FOR LINKING MSP430G2221 PROGRAMS     */
+/*                                                                            */
+/*   Usage:  lnk430 <obj files...>    -o <out file> -m <map file> lnk.cmd     */
+/*           cl430  <src files...> -z -o <out file> -m <map file> lnk.cmd     */
+/*                                                                            */
+/*----------------------------------------------------------------------------*/
+/* These linker options are for command line linking only.  For IDE linking,  */
+/* you should set your linker options in Project Properties                   */
+/* -c                                               LINK USING C CONVENTIONS  */
+/* -stack  0x0100                                   SOFTWARE STACK SIZE       */
+/* -heap   0x0100                                   HEAP AREA SIZE            */
+/*                                                                            */
+/*----------------------------------------------------------------------------*/
+/* Version: 1.191                                                             */
+/*----------------------------------------------------------------------------*/
+
+/****************************************************************************/
+/* Specify the system memory map                                            */
+/****************************************************************************/
+
+MEMORY
+{
+    SFR                     : origin = 0x0000, length = 0x0010
+    PERIPHERALS_8BIT        : origin = 0x0010, length = 0x00F0
+    PERIPHERALS_16BIT       : origin = 0x0100, length = 0x0100
+    RAM                     : origin = 0x0200, length = 0x0080
+    INFOA                   : origin = 0x10C0, length = 0x0040
+    INFOB                   : origin = 0x1080, length = 0x0040
+    INFOC                   : origin = 0x1040, length = 0x0040
+    INFOD                   : origin = 0x1000, length = 0x0040
+    FLASH                   : origin = 0xF800, length = 0x07E0
+    INT00                   : origin = 0xFFE0, length = 0x0002
+    INT01                   : origin = 0xFFE2, length = 0x0002
+    INT02                   : origin = 0xFFE4, length = 0x0002
+    INT03                   : origin = 0xFFE6, length = 0x0002
+    INT04                   : origin = 0xFFE8, length = 0x0002
+    INT05                   : origin = 0xFFEA, length = 0x0002
+    INT06                   : origin = 0xFFEC, length = 0x0002
+    INT07                   : origin = 0xFFEE, length = 0x0002
+    INT08                   : origin = 0xFFF0, length = 0x0002
+    INT09                   : origin = 0xFFF2, length = 0x0002
+    INT10                   : origin = 0xFFF4, length = 0x0002
+    INT11                   : origin = 0xFFF6, length = 0x0002
+    INT12                   : origin = 0xFFF8, length = 0x0002
+    INT13                   : origin = 0xFFFA, length = 0x0002
+    INT14                   : origin = 0xFFFC, length = 0x0002
+    RESET                   : origin = 0xFFFE, length = 0x0002
+}
+
+/****************************************************************************/
+/* Specify the sections allocation into memory                              */
+/****************************************************************************/
+
+SECTIONS
+{
+    .bss        : {} > RAM                  /* Global & static vars              */
+    .data       : {} > RAM                  /* Global & static vars              */
+    .TI.noinit  : {} > RAM                  /* For #pragma noinit                */
+    .sysmem     : {} > RAM                  /* Dynamic memory allocation area    */
+    .stack      : {} > RAM (HIGH)           /* Software system stack             */
+
+    .text       : {} > FLASH                /* Code                              */
+    .cinit      : {} > FLASH                /* Initialization tables             */
+    .const      : {} > FLASH                /* Constant data                     */
+    .cio        : {} > RAM                  /* C I/O Buffer                      */
+
+    .pinit      : {} > FLASH                /* C++ Constructor tables            */
+    .binit      : {} > FLASH                /* Boot-time Initialization tables   */
+    .init_array : {} > FLASH                /* C++ Constructor tables            */
+    .mspabi.exidx : {} > FLASH              /* C++ Constructor tables            */
+    .mspabi.extab : {} > FLASH              /* C++ Constructor tables            */
+#ifdef __TI_COMPILER_VERSION
+  #if __TI_COMPILER_VERSION >= 15009000
+    #ifndef __LARGE_DATA_MODEL__
+    .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
+    #else
+    .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
+    #endif
+  #endif
+#endif
+
+    .infoA     : {} > INFOA              /* MSP430 INFO FLASH Memory segments */
+    .infoB     : {} > INFOB
+    .infoC     : {} > INFOC
+    .infoD     : {} > INFOD
+
+    /* MSP430 Interrupt vectors          */
+    .int00       : {}               > INT00
+    .int01       : {}               > INT01
+    PORT1        : { * ( .int02 ) } > INT02 type = VECT_INIT
+    PORT2        : { * ( .int03 ) } > INT03 type = VECT_INIT
+    USI          : { * ( .int04 ) } > INT04 type = VECT_INIT
+    .int05       : {}               > INT05
+    .int06       : {}               > INT06
+    .int07       : {}               > INT07
+    TIMERA1      : { * ( .int08 ) } > INT08 type = VECT_INIT
+    TIMERA0      : { * ( .int09 ) } > INT09 type = VECT_INIT
+    WDT          : { * ( .int10 ) } > INT10 type = VECT_INIT
+    .int11       : {}               > INT11
+    .int12       : {}               > INT12
+    .int13       : {}               > INT13
+    NMI          : { * ( .int14 ) } > INT14 type = VECT_INIT
+    .reset       : {}               > RESET  /* MSP430 Reset vector         */
+}
+
+/****************************************************************************/
+/* Include peripherals memory map                                           */
+/****************************************************************************/
+
+-l msp430g2221.cmd
+

diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c
new file mode 100644 (file)
index 0000000..c7e5407
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c
@@ -0,0 +1,391 @@
+/*---------------------------------------------------------------------------*/
+
+#include <msp430.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#define CC2650
+#define MSP432
+
+
+/*---------------------------------------------------------------------------*/
+#define BOOTLOADER_INVERT_LINES
+
+#ifndef BOOTLOADER_INVERT_LINES
+       /* MPS432 */
+       #define RESET_IN1            (BIT0)  // RTS - RESET
+       #define BOOT_IN1             (BIT1)  // DTR - BOOT
+       #define BOOT_OUT1            (BIT3)  // BSL
+
+    #define RESET_IN2            (BIT4)  // RTS - RESET
+       #define BOOT_IN2             (BIT5)  // DTR - BOOT
+       #define BOOT_OUT2            (BIT7)  // BSL
+
+       #define RESET_OUT            (BIT2)  // RESET
+#else
+    /* MPS432 */
+       #define BOOT_IN1             (BIT0)  // RTS - BOOT
+       #define RESET_IN1            (BIT1)  // DTR - RESET
+       #define BOOT_OUT1            (BIT3)  // BSL
+       /* CC2650 */
+    #define BOOT_IN2             (BIT4)  // RTS - BOOT
+       #define RESET_IN2            (BIT5)  // DTR - RESET
+       #define BOOT_OUT2            (BIT7)  // BSL
+
+    #define RESET_OUT           (BIT2)  // RESET
+#endif
+
+
+/*---------------------------------------------------------------------------*/
+/* Timer Delays*/
+#define STARTUP_DELAY        (750)  // ~0.5s @ 1.5 Khz
+#define BOOTLOADER_TIMEOUT    (75)  // ~50 ms @ 1.5 kHz
+
+/*---------------------------------------------------------------------------*/
+/* Procesor Delays */
+#define MSEC_DELAY          (4250)  // ~1 ms @ 4.25 MHz
+#define CC2650_BSL_DELAY    (8500)  //  2 ms @ 4.25 MHz
+#define MSP432_BSL_DELAY    (42500) // 10 ms @ 4.25 MHz
+
+
+/*---------------------------------------------------------------------------*/
+static volatile bool bootloader_active = false;
+static volatile bool bootload_enable   = false;
+
+
+/*---------------------------------------------------------------------------*/
+int main(void) {
+
+  int i;
+
+  // Disable Watchdog
+  WDTCTL = WDTPW + WDTHOLD;
+
+  // Set DCO operation to 4.25 MHz
+  BCSCTL1 &= ~(BIT2 + BIT1 + BIT0);
+  BCSCTL1 |= (BIT3 + BIT1 + BIT0);
+
+  /*
+     MCLK  = DCO / 1 = 4.25 MHz
+     SMCLK = DCO / 1 = 4.25 MHz
+     ACLK  = VLOCLK / 8 = 12 kHz / 8 = 1.5 kHz
+  */
+  BCSCTL1 |= (XT2OFF + DIVA_3);
+  BCSCTL3 |= (LFXT1S_2);
+
+  /* Wait Oscillator stable */
+  while (IFG1 & OFIFG)            // OSCFault flag still set?
+  {
+    IFG1 &= ~OFIFG;               // Clear OSCFault flag
+    for (i = 0xFFF; i > 0; i--);  // Time for flag to set
+  }
+
+  // Startup Delay: avoid DTR/RTS glitches on FDTI initialization
+  TACCTL1 = CCIE;
+  TACCR1  = STARTUP_DELAY;
+  TACTL = (TASSEL_1 + MC_2 + TAIE + TACLR);
+  _BIS_SR(LPM3_bits + GIE);
+
+// Configure P1 input and ouput
+  P1DIR &= ~(RESET_OUT);
+
+  #ifdef MSP432
+  P1DIR &= ~(RESET_IN1 + BOOT_IN1);
+  P1DIR |= (BOOT_OUT1);
+  P1OUT |= (BOOT_OUT1);
+#endif
+
+#ifdef CC2650
+  P1DIR &= ~(RESET_IN2 + BOOT_IN2);
+  P1DIR |= (BOOT_OUT2);
+  P1OUT |= (BOOT_OUT2);
+#endif
+
+// Configure P1 ints
+#ifdef MSP432
+  // Configure BOOT_IN1 interrupt high to low
+  P1IFG &=~ (BOOT_IN1);
+  P1IES |=  (BOOT_IN1);
+  P1IE  |=  (BOOT_IN1);
+#endif
+
+#ifdef CC2650
+  // Configure BOOT_IN2 interrupt high to low
+  P1IFG &=~ (BOOT_IN2);
+  P1IES |=  (BOOT_IN2);
+  P1IE  |=  (BOOT_IN2);
+#endif
+
+  // Forever: Go to the lowest LPM
+  while (1) {
+    if (bootloader_active == true) {
+      _BIS_SR(LPM3_bits + GIE);
+    } else {
+      _BIS_SR(LPM4_bits + GIE);
+    }
+  }
+
+  return 0;
+
+}
+/*---------------------------------------------------------------------------*/
+#pragma vector=PORT1_VECTOR
+__interrupt void port1_isr (void) {
+
+       int flag=0;
+
+#ifdef MSP432
+
+       // BOOT_IN2 high to low
+       if (((P1IFG & BOOT_IN1) == BOOT_IN1) &&
+         ((P1IN  & BOOT_IN1) == 0) &&
+         ((P1IES & BOOT_IN1) == BOOT_IN1)) {
+
+               // BOOT_IN2 interrupt clear and disable
+               P1IFG &=~ (BOOT_IN1);
+               P1IE &=~ (BOOT_IN1);
+
+               flag=1;
+
+               /* Disable CC2650 BSL */
+               P1IFG &=~(RESET_IN2|BOOT_IN2);
+               P1IE  &=~(RESET_IN2|BOOT_IN2);
+
+               /* Enable Reset High to Low */
+               P1IES |= (RESET_IN1);
+               P1IFG &=~ (RESET_IN1);
+               P1IE |= (RESET_IN1);
+
+               // RESET_IN1 should be low
+               if ((P1IN & RESET_IN1) == 0) {
+                       bootloader_active = true;
+               }
+       }
+
+
+       // RESET_IN1 high to low
+       if (((P1IFG & RESET_IN1) == RESET_IN1) &&
+      ((P1IN  & RESET_IN1) == 0) &&
+         ((P1IES & RESET_IN1) == RESET_IN1)) {
+
+               // RESET_IN1 interrupt clear and disable
+               P1IFG &=~(RESET_IN1);
+               P1IE &=~(RESET_IN1);
+
+               flag=1;
+
+               /* Enable Reset_IN Low to High */
+               P1IES &=~ (RESET_IN1);
+               P1IFG &=~ (RESET_IN1);
+               P1IE |= (RESET_IN1);
+
+               // Enable Bootload
+               bootload_enable = true;
+       }
+
+
+
+       // RESET_IN1 low to high
+       if (((P1IFG & RESET_IN1) == RESET_IN1) &&
+         ((P1IN  & RESET_IN1) == RESET_IN1) &&
+          ((P1IES & RESET_IN1) == 0)) {
+
+               // RESET_IN1 interrupt clear and dsiable
+               P1IFG &=~(RESET_IN1);
+               P1IE &= ~(RESET_IN1);
+
+               flag=1;
+
+               // If bootload_enable is set
+               if (bootload_enable == true) {
+
+                       // RESET_OUT ouput
+                       P1DIR |=  (RESET_OUT);
+                       P1OUT &= ~(BOOT_OUT1);
+
+                       // Reset Pulse
+                       __delay_cycles(MSEC_DELAY);
+                       P1OUT &=~(RESET_OUT);
+                       __delay_cycles(MSEC_DELAY);
+                       P1OUT |= (RESET_OUT);
+
+                       __delay_cycles(MSP432_BSL_DELAY);
+                       // Release Boot Pin
+                       P1OUT |= (BOOT_OUT1);
+                       P1DIR &= ~(RESET_OUT);
+
+               }
+  }
+#endif
+
+#ifdef CC2650
+
+    // BOOT_IN2 high to low
+    if (((P1IFG & BOOT_IN2) == BOOT_IN2) &&
+        ((P1IN  & BOOT_IN2) == 0) &&
+        ((P1IES & BOOT_IN2) == BOOT_IN2)) {
+
+               // BOOT_IN2 interrupt clear and disable
+               P1IFG &=~ (BOOT_IN2);
+               P1IE &=~ (BOOT_IN2);
+
+               flag=1;
+
+               /* Disable MCP432 Boot */
+               P1IFG &=~(RESET_IN1|BOOT_IN1);
+               P1IE  &=~(RESET_IN1|BOOT_IN1);
+
+               /* Enable Reset High to Low */
+               P1IES |= (RESET_IN2);
+               P1IFG &=~ (RESET_IN2);
+               P1IE |= (RESET_IN2);
+
+               // RESET_IN2 should be low
+               if ((P1IN & RESET_IN2) == 0) {
+                       bootloader_active = true;
+               }
+    }
+
+
+       // RESET_IN1 high to low
+       if (((P1IFG & RESET_IN2) == RESET_IN2) &&
+         ((P1IN  & RESET_IN2) == 0) &&
+         ((P1IES & RESET_IN2) == RESET_IN2)) {
+
+               // RESET_IN2 interrupt clear
+               P1IFG &=~(RESET_IN2);
+               P1IE &=~(RESET_IN2);
+
+               flag=1;
+
+               /* Low to High */
+               P1IES &=~ (RESET_IN2);
+               P1IFG &=~ (RESET_IN2);
+               P1IE |= (RESET_IN2);
+
+               // Set bootloader_active
+               bootload_enable = true;
+       }
+
+
+
+       // RESET_IN1 low to high
+       if (((P1IFG & RESET_IN2) == RESET_IN2) &&
+         ((P1IN  & RESET_IN2) == RESET_IN2) &&
+         ((P1IES & RESET_IN2) == 0)) {
+
+               // RESET_IN1 interrupt clear
+               P1IFG &=~(RESET_IN2);
+               P1IE &= ~(RESET_IN2);
+
+               flag=1;
+
+               // If bootload_enable is set
+               if (bootload_enable == true) {
+
+                       // RESET_OUT1 is now ouput
+                       P1DIR |=  (RESET_OUT);
+                       //__delay_cycles(STARTUP_DELAY);
+                       P1OUT &= ~(BOOT_OUT2);
+
+                       /* Reset Pulse */
+                       __delay_cycles(425);
+                       P1OUT &=~(RESET_OUT);
+                       __delay_cycles(MSEC_DELAY);
+                       P1OUT |= (RESET_OUT);
+                       __delay_cycles(CC2650_BSL_DELAY);
+
+                       /* Release Boot Pin*/
+                       P1OUT |= (BOOT_OUT2);
+                       // RESET_OUT2 is now input
+                       P1DIR &= ~(RESET_OUT);
+               }
+       }
+#endif
+
+  /* Unknown Sequence: Disable PIOs, Wait Timout */
+  if(flag==0){
+         P1IE  &=~ (RESET_IN1|RESET_IN2|BOOT_IN1|BOOT_IN2);
+         P1IFG = 0;
+  }
+
+  // Set TIMER_A-CCR0 Timout
+  TACCR0  = BOOTLOADER_TIMEOUT;
+  TACCTL0 = (CCIE);
+  TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
+
+  _BIC_SR_IRQ(LPM4_bits + GIE);
+
+}
+/*---------------------------------------------------------------------------*/
+#pragma vector=TIMERA0_VECTOR
+__interrupt void timera0_isr (void) {
+
+  // TIMERA0 reset
+  TACTL = 0;
+  TACCTL0 &=~(CCIE);
+
+  // Clear variables
+  bootloader_active = false;
+  bootload_enable   = false;
+
+  // Ensure RESET_OUT1 and BOOT_OUT1 are high
+  P1OUT |=  (RESET_OUT + BOOT_OUT1);
+  P1DIR &=~(RESET_OUT);
+
+#ifdef MSP432
+  // (Re)Enable BOOT_IN1 high to low Int
+  P1IES |= (BOOT_IN1);
+  P1IFG &= ~(RESET_IN1+BOOT_IN1);
+  P1IE  &=~ (RESET_IN1);
+  P1IE  |= (BOOT_IN1);
+#endif
+
+
+#ifdef CC2650
+  // (Re)Enable RESET_IN2 high to low Int
+  P1IES |= (BOOT_IN2);
+  P1IFG &= ~(RESET_IN2+BOOT_IN2);
+  P1IE  &=~ (RESET_IN2);
+  P1IE  |= (BOOT_IN2);
+#endif
+
+
+  _BIC_SR_IRQ(LPM3_bits + GIE);
+
+}
+
+#pragma vector=TIMERA1_VECTOR
+__interrupt void timera1_isr (void) {
+
+
+  switch(TAIV)
+  {
+    case TAIV_TACCR1: // CCR1
+       {
+         TACTL = 0;
+         TACCTL1 &=~(CCIE);
+       }
+       break;
+
+    case TAIV_TAIFG: // overflow not used
+    break;
+
+ }
+
+ _BIC_SR_IRQ(LPM3_bits + GIE);
+
+}
+
+
+/*
+#pragma vector=NMI_VECTOR
+__interrupt void nmi_isr (void) {
+    _BIC_SR_IRQ(LPM3_bits + GIE);
+}
+*/
+
+
+
+/*---------------------------------------------------------------------------*/