BSL msp430 Inverted DTR-RTS signals

diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
index 43007cb932c0db00f0c510a9d84f71c86b40cc55..fe0983ef003ac3e5ead53e2975f3b7afec383b3a 100644 (file)
--- a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
@@ -8,21 +8,39 @@
 #define CC2650
 #define MSP432
 
+
 /*---------------------------------------------------------------------------*/
-#define RESET_IN1            (BIT0)  // RTS - RESET
-#define BOOT_IN1             (BIT1)  // DTR - BOOT
-#define RESET_OUT1           (BIT2)  // RTS - RESET
-#define BOOT_OUT1            (BIT3)  // DTR - BOOT
-/*---------------------------------------------------------------------------*/
-#define RESET_IN2            (BIT4)  // RTS - RESET
-#define BOOT_IN2             (BIT5)  // DTR - BOOT
-#define RESET_OUT2           (BIT6)  // RTS - RESET
-#define BOOT_OUT2            (BIT7)  // DTR - BOOT
+#define BOOTLOADER_INVERT_LINES
+
+#ifndef BOOTLOADER_INVERT_LINES
+       /* MPS432 */
+       #define RESET_IN1            (BIT0)  // RTS - RESET
+       #define BOOT_IN1             (BIT1)  // DTR - BOOT
+       #define RESET_OUT1           (BIT2)  // RTS - RESET
+       #define BOOT_OUT1            (BIT3)  // DTR - BOOT
+    /* CC2650 */
+    #define RESET_IN2            (BIT4)  // RTS - RESET
+       #define BOOT_IN2             (BIT5)  // DTR - BOOT
+       #define RESET_OUT2           (BIT6)  // RTS - RESET
+       #define BOOT_OUT2            (BIT7)  // DTR - BOOT
+#else
+    /* MPS432 */
+       #define BOOT_IN1             (BIT0)  // RTS - BOOT
+       #define RESET_IN1            (BIT1)  // DTR - RESET
+       #define RESET_OUT1           (BIT2)  // RTS - RESET
+       #define BOOT_OUT1            (BIT3)  // DTR - BOOT
+       /* CC2650 */
+    #define BOOT_IN2             (BIT4)  // RTS - BOOT
+       #define RESET_IN2            (BIT5)  // DTR - RESET
+       #define RESET_OUT2           (BIT6)  // RTS - RESET
+       #define BOOT_OUT2            (BIT7)  // DTR - BOOT
+#endif
+
 
 /*---------------------------------------------------------------------------*/
 /* Timer Delays*/
-#define STARTUP_DELAY     (5*1500)  // ~5s @ 1.5 Khz
-#define BOOTLOADER_TIMEOUT    (50)  // ~100 ms @ 1.5 kHz
+#define STARTUP_DELAY        (750)  // ~0.5s @ 1.5 Khz
+#define BOOTLOADER_TIMEOUT    (75)  // ~50 ms @ 1.5 kHz
 
 /*---------------------------------------------------------------------------*/
 /* Procesor Delays */
@@ -286,15 +304,17 @@ __interrupt void port1_isr (void) {
        }
 #endif
 
+  /* Unknown Sequence: Disable PIOs, Wait Timout */
+  if(flag==0){
+         P1IE  &=~ (RESET_IN1|RESET_IN2|BOOT_IN1|BOOT_IN2);
+         P1IFG = 0;
+  }
+
   // Set TIMER_A-CCR0 Timout
   TACCR0  = BOOTLOADER_TIMEOUT;
   TACCTL0 = (CCIE);
   TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
 
-  if(flag==0){
-         P1IFG = 0;
-  }
-
   _BIC_SR_IRQ(LPM4_bits + GIE);
 
 }