Created Test MSP432 I2C M24xx256
authorBorja Martinez <borja.martinez@gmail.com>
Sat, 10 Sep 2016 17:09:15 +0000 (19:09 +0200)
committerBorja Martinez <borja.martinez@gmail.com>
Sat, 10 Sep 2016 17:09:15 +0000 (19:09 +0200)
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c [new file with mode: 0644]
Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c [new file with mode: 0644]

diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c
new file mode 100644 (file)
index 0000000..b30f071
--- /dev/null
@@ -0,0 +1,202 @@
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2015, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * *  Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * *  Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ *\r
+ * *  Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//****************************************************************************\r
+//\r
+// HAL_I2C.c - Hardware abstraction layer for I2C with MSP432P401R\r
+//\r
+//****************************************************************************\r
+\r
+#include <driverlib.h>\r
+#include <HAL_I2C.h>\r
+\r
+\r
+/* I2C Master Configuration Parameter */\r
+const eUSCI_I2C_MasterConfig i2cConfig =\r
+{\r
+        EUSCI_B_I2C_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source\r
+        12000000,                               // SMCLK = 48MHz\r
+        EUSCI_B_I2C_SET_DATA_RATE_100KBPS,      // Desired I2C Clock of 100khz\r
+        0,                                      // No byte counter threshold\r
+        EUSCI_B_I2C_NO_AUTO_STOP                // No Autostop\r
+};\r
+\r
+void Init_I2C_GPIO()\r
+{\r
+    /* Select I2C function for I2C_SCL(P6.5) */\r
+    GPIO_setAsPeripheralModuleFunctionOutputPin(\r
+               GPIO_PORT_P3,\r
+               GPIO_PIN7,\r
+            //GPIO_PORT_P6,\r
+            //GPIO_PIN5,\r
+               //GPIO_PORT_P1,\r
+               //GPIO_PIN7,\r
+            GPIO_PRIMARY_MODULE_FUNCTION);\r
+\r
+    /* Select I2C function for I2C_SDA(P6.4) */\r
+    GPIO_setAsPeripheralModuleFunctionOutputPin(\r
+            GPIO_PORT_P3,\r
+            GPIO_PIN6,\r
+            //GPIO_PORT_P6,\r
+            //GPIO_PIN4,\r
+               //GPIO_PORT_P1,\r
+               //GPIO_PIN6,\r
+            GPIO_PRIMARY_MODULE_FUNCTION);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief  Configures I2C\r
+ * @param  none\r
+ * @return none\r
+ ******************************************************************************/\r
+\r
+void I2C_init(void)\r
+{\r
+    /* Initialize USCI_B0 and I2C Master to communicate with slave devices*/\r
+    I2C_initMaster(EUSCI_B2_BASE, &i2cConfig);\r
+    //I2C_initMaster(EUSCI_B2_BASE, &i2cConfig);\r
+\r
+    /* Disable I2C module to make changes */\r
+    I2C_disableModule(EUSCI_B2_BASE);\r
+    //I2C_disableModule(EUSCI_B2_BASE);\r
+\r
+    /* Enable I2C Module to start operations */\r
+    I2C_enableModule(EUSCI_B2_BASE);\r
+    //I2C_enableModule(EUSCI_B2_BASE);\r
+\r
+    return;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief  Reads data from the sensor\r
+ * @param  writeByte Address of register to read from\r
+ * @return Register contents\r
+ ******************************************************************************/\r
+\r
+unsigned char I2C_eeprom_read_byte(unsigned short addr)\r
+{\r
+    volatile int val = 0;\r
+    volatile int valScratch = 0;\r
+\r
+    /* Set master to transmit mode PL */\r
+    I2C_setMode(EUSCI_B2_BASE,\r
+        EUSCI_B_I2C_TRANSMIT_MODE);\r
+\r
+    /* Clear any existing interrupt flag PL */\r
+    I2C_clearInterruptFlag(EUSCI_B2_BASE,\r
+        EUSCI_B_I2C_TRANSMIT_INTERRUPT0);\r
+\r
+    /* Wait until ready to write PL */\r
+    while (I2C_isBusBusy(EUSCI_B2_BASE));\r
+\r
+    /* Initiate start and send first character */\r
+    I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(addr>>8)&0x00FF);\r
+    /* Wait for TX to finish */\r
+    while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));\r
+\r
+    /* Send Next Character */\r
+    I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(addr&0x00FF));\r
+    /* Wait for TX to finish */\r
+    while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));\r
+\r
+    /* Initiate stop only */\r
+    I2C_masterSendMultiByteStop(EUSCI_B2_BASE);\r
+    /* Wait for Stop to finish */\r
+    while(!I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_STOP_INTERRUPT));\r
+\r
+    /*\r
+     * Generate Start condition and set it to receive mode.\r
+     * This sends out the slave address and continues to read until you issue a STOP\r
+     */\r
+\r
+    I2C_setMode(EUSCI_B2_BASE,EUSCI_B_I2C_RECEIVE_MODE);\r
+    while (I2C_isBusBusy(EUSCI_B2_BASE));\r
+\r
+    val=I2C_masterReceiveSingleByte(EUSCI_B2_BASE);\r
+\r
+    /* Return temperature value */\r
+    return val;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief  Writes data to the sensor\r
+ * @param  pointer  Address of register you want to modify\r
+ * @param  writeByte Data to be written to the specified register\r
+ * @return none\r
+ ******************************************************************************/\r
+\r
+void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte)\r
+{\r
+    /* Set master to transmit mode PL */\r
+    I2C_setMode(EUSCI_B2_BASE,\r
+        EUSCI_B_I2C_TRANSMIT_MODE);\r
+\r
+    /* Clear any existing interrupt flag PL */\r
+    I2C_clearInterruptFlag(EUSCI_B2_BASE,\r
+        EUSCI_B_I2C_TRANSMIT_INTERRUPT0);\r
+\r
+    /* Wait until ready to write PL */\r
+    while (I2C_isBusBusy(EUSCI_B2_BASE));\r
+\r
+    /* Initiate start and send first character */\r
+    I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(unsigned char)(pointer>>8));\r
+    while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));\r
+\r
+\r
+    I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(pointer&0x00FF));\r
+    while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));\r
+\r
+\r
+    I2C_masterSendMultiByteFinish(EUSCI_B2_BASE,\r
+        (unsigned char)(writeByte&0xFF));\r
+    while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));\r
+\r
+    while (I2C_isBusBusy(EUSCI_B2_BASE));\r
+\r
+}\r
+\r
+\r
+void I2C_setslave(unsigned int slaveAdr)\r
+{\r
+    /* Specify slave address for I2C */\r
+    //I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr);\r
+       I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr);\r
+\r
+    /* Enable and clear the interrupt flag */\r
+       I2C_clearInterruptFlag(EUSCI_B2_BASE,\r
+               EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0);\r
+       //I2C_clearInterruptFlag(EUSCI_B2_BASE,\r
+    //    EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0);\r
+    return;\r
+}\r
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h
new file mode 100644 (file)
index 0000000..917f385
--- /dev/null
@@ -0,0 +1,48 @@
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2015, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * *  Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * *  Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ *\r
+ * *  Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//****************************************************************************\r
+//\r
+// HAL_I2C.h - Prototypes of hardware abstraction layer for I2C between\r
+//             MSP432P401R and OPT3001\r
+//\r
+//****************************************************************************\r
+\r
+#ifndef __HAL_I2C_H_\r
+#define __HAL_I2C_H_\r
+\r
+void Init_I2C_GPIO(void);\r
+void I2C_init(void);\r
+unsigned char I2C_eeprom_read_byte(unsigned short);\r
+void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte);\r
+void I2C_setslave(unsigned int slaveAdr);\r
+\r
+#endif /* __HAL_I2C_H_ */\r
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h
new file mode 100644 (file)
index 0000000..750f90e
--- /dev/null
@@ -0,0 +1,16 @@
+/* Rev.B */
+#define HID_PORT GPIO_PORT_P6
+#define LEDR     GPIO_PIN2
+#define LEDG     GPIO_PIN3
+#define BUTTON   GPIO_PIN1
+
+
+/* Rev.A
+#define LED_PORT GPIO_PORT_P8
+#define LEDR    GPIO_PIN5
+#define LEDG    GPIO_PIN6
+#define BUTTON  GPIO_PIN7
+*/
+
+
+#define EEPROM_SLAVE_ADDRESS 0x50
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c
new file mode 100644 (file)
index 0000000..2c7286c
--- /dev/null
@@ -0,0 +1,91 @@
+//****************************************************************************\r
+//\r
+//\r
+//\r
+//****************************************************************************\r
+#include "i3mote.h"\r
+\r
+/* MSP432 Incldues */\r
+#include "msp.h"\r
+#include <driverlib.h>\r
+\r
+/* Standard Includes */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+\r
+\r
+/* I2C Support */\r
+#include <HAL_I2C.h>\r
+\r
+\r
+/* Local Definitions */\r
+#define NPOS 256 // EEPROM positions to Read/Write\r
+\r
+void main(void)\r
+{\r
+\r
+       unsigned short i=0;\r
+       unsigned short val;\r
+\r
+       /* Halting WDT and disabling master interrupts */\r
+    MAP_WDT_A_holdTimer();\r
+    MAP_Interrupt_disableMaster();\r
+\r
+    /* Initializes Clock System */\r
+    MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);\r
+    MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+    MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+    MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );\r
+    MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);\r
+\r
+    /* Disable GPS VCC */\r
+    MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P2,GPIO_PIN4);\r
+    MAP_GPIO_setAsOutputPin(GPIO_PORT_P2,GPIO_PIN4);\r
+\r
+    /* LEDs */\r
+    MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);\r
+    MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDG|LEDR);\r
+\r
+    /* Initialize I2C communication */\r
+    Init_I2C_GPIO();\r
+    I2C_init();\r
+\r
+    I2C_setslave(EEPROM_SLAVE_ADDRESS);\r
+\r
+\r
+    for(i=0;i<NPOS;i++){\r
+        I2C_eeprom_write_byte((int16_t)i,i);\r
+        __delay_cycles(12000*10);\r
+    }\r
+\r
+    for(i=0;i<NPOS;i++){\r
+        val=I2C_eeprom_read_byte(i);\r
+               printf("%02X %02X\n",i,val);\r
+        if(val!=(0xFF&i)){\r
+            MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);\r
+            exit(-1);\r
+        }\r
+    }\r
+\r
+    for(i=0;i<NPOS;i++){\r
+       I2C_eeprom_write_byte((int16_t)i,~i);\r
+        __delay_cycles(12000*10);\r
+    }\r
+\r
+    for(i=0;i<NPOS;i++){\r
+       val=I2C_eeprom_read_byte(i);\r
+               printf("%02X %02X\n",(~i)&0xFF,val);\r
+        if(val!=(0xFF&(~i))){\r
+            MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);\r
+            exit(-1);\r
+        }\r
+    }\r
+\r
+    MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDG);\r
+\r
+    /* Enter LPM0 forever*/\r
+    MAP_PCM_gotoLPM0();\r
+\r
+}\r
+\r
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd
new file mode 100644 (file)
index 0000000..41aad2d
--- /dev/null
@@ -0,0 +1,104 @@
+/******************************************************************************\r
+*\r
+* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+*\r
+*  Redistributions of source code must retain the above copyright\r
+*  notice, this list of conditions and the following disclaimer.\r
+*\r
+*  Redistributions in binary form must reproduce the above copyright\r
+*  notice, this list of conditions and the following disclaimer in the\r
+*  documentation and/or other materials provided with the\r
+*  distribution.\r
+*\r
+*  Neither the name of Texas Instruments Incorporated nor the names of\r
+*  its contributors may be used to endorse or promote products derived\r
+*  from this software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*\r
+* Default linker command file for Texas Instruments MSP432P401R\r
+*\r
+* File creation date: 2016-01-26\r
+*\r
+*****************************************************************************/\r
+\r
+--retain=flashMailbox\r
+\r
+MEMORY\r
+{\r
+    MAIN       (RX) : origin = 0x00000000, length = 0x00040000\r
+    INFO       (RX) : origin = 0x00200000, length = 0x00004000\r
+#ifdef  __TI_COMPILER_VERSION__\r
+#if     __TI_COMPILER_VERSION__ >= 15009000\r
+    ALIAS\r
+    {\r
+    SRAM_CODE  (RWX): origin = 0x01000000\r
+    SRAM_DATA  (RW) : origin = 0x20000000\r
+    } length = 0x00010000\r
+#else\r
+    /* Hint: If the user wants to use ram functions, please observe that SRAM_CODE             */\r
+    /* and SRAM_DATA memory areas are overlapping. You need to take measures to separate       */\r
+    /* data from code in RAM. This is only valid for Compiler version earlier than 15.09.0.STS.*/ \r
+    SRAM_CODE  (RWX): origin = 0x01000000, length = 0x00010000\r
+    SRAM_DATA  (RW) : origin = 0x20000000, length = 0x00010000\r
+#endif\r
+#endif\r
+}\r
+\r
+/* The following command line options are set as part of the CCS project.    */\r
+/* If you are building using the command line, or for some reason want to    */\r
+/* define them here, you can uncomment and modify these lines as needed.     */\r
+/* If you are using CCS for building, it is probably better to make any such */\r
+/* modifications in your CCS project and leave this file alone.              */\r
+/*                                                                           */\r
+/* A heap size of 1024 bytes is recommended when you plan to use printf()    */\r
+/* for debug output to the console window.                                   */\r
+/*                                                                           */\r
+/* --heap_size=1024                                                          */\r
+/* --stack_size=512                                                          */\r
+/* --library=rtsv7M4_T_le_eabi.lib                                           */\r
+\r
+/* Section allocation in memory */\r
+\r
+SECTIONS\r
+{\r
+    .intvecs:   > 0x00000000\r
+    .text   :   > MAIN\r
+    .const  :   > MAIN\r
+    .cinit  :   > MAIN\r
+    .pinit  :   > MAIN\r
+    .init_array   :     > MAIN\r
+    .binit        : {}  > MAIN\r
+\r
+    .flashMailbox : > 0x00200000\r
+\r
+    .vtable :   > 0x20000000\r
+    .data   :   > SRAM_DATA\r
+    .bss    :   > SRAM_DATA\r
+    .sysmem :   > SRAM_DATA\r
+    .stack  :   > SRAM_DATA (HIGH)\r
+\r
+#ifdef  __TI_COMPILER_VERSION__\r
+#if     __TI_COMPILER_VERSION__ >= 15009000\r
+    .TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT)\r
+#endif\r
+#endif\r
+}\r
+\r
+/* Symbolic definition of the WDTCTL register for RTS */\r
+WDTCTL_SYM = 0x4000480C;\r
+\r
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c
new file mode 100644 (file)
index 0000000..e8714ad
--- /dev/null
@@ -0,0 +1,219 @@
+/******************************************************************************\r
+* \r
+*  Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/ \r
+* \r
+*  Redistribution and use in source and binary forms, with or without \r
+*  modification, are permitted provided that the following conditions \r
+*  are met:\r
+* \r
+*   Redistributions of source code must retain the above copyright \r
+*   notice, this list of conditions and the following disclaimer.\r
+* \r
+*   Redistributions in binary form must reproduce the above copyright\r
+*   notice, this list of conditions and the following disclaimer in the \r
+*   documentation and/or other materials provided with the   \r
+*   distribution.\r
+* \r
+*   Neither the name of Texas Instruments Incorporated nor the names of\r
+*   its contributors may be used to endorse or promote products derived\r
+*   from this software without specific prior written permission.\r
+* \r
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \r
+* \r
+*  MSP432P401R Interrupt Vector Table and startup code for CCS TI ARM\r
+* \r
+*****************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* Forward declaration of the default fault handlers. */\r
+static void resetISR(void);\r
+static void nmiISR(void);\r
+static void faultISR(void);\r
+static void defaultISR(void);\r
+\r
+\r
+/* External declaration for the reset handler that is to be called when the */\r
+/* processor is started                                                     */\r
+extern void _c_int00(void);\r
+\r
+/* External declaration for system initialization function                  */\r
+extern void SystemInit(void);\r
+\r
+/* Linker variable that marks the top of the stack. */\r
+extern unsigned long __STACK_END;\r
+\r
+\r
+/* External declarations for the interrupt handlers used by the application. */\r
+/* To be added by user */\r
+\r
+\r
+/* Interrupt vector table.  Note that the proper constructs must be placed on this to */\r
+/* ensure that it ends up at physical address 0x0000.0000 or at the start of          */\r
+/* the program if located at a start address other than 0.                            */\r
+#pragma RETAIN(interruptVectors)\r
+#pragma DATA_SECTION(interruptVectors, ".intvecs")\r
+void (* const interruptVectors[])(void) =\r
+{\r
+    (void (*)(void))((uint32_t)&__STACK_END),\r
+                                            /* The initial stack pointer */\r
+    resetISR,                               /* The reset handler         */\r
+    nmiISR,                                 /* The NMI handler           */\r
+    faultISR,                               /* The hard fault handler    */\r
+    defaultISR,                             /* The MPU fault handler     */\r
+    defaultISR,                             /* The bus fault handler     */\r
+    defaultISR,                             /* The usage fault handler   */\r
+    0,                                      /* Reserved                  */\r
+    0,                                      /* Reserved                  */\r
+    0,                                      /* Reserved                  */\r
+    0,                                      /* Reserved                  */\r
+    defaultISR,                             /* SVCall handler            */\r
+    defaultISR,                             /* Debug monitor handler     */\r
+    0,                                      /* Reserved                  */\r
+    defaultISR,                             /* The PendSV handler        */\r
+       defaultISR,                             /* The SysTick handler       */\r
+    defaultISR,                             /* PSS ISR                   */\r
+    defaultISR,                             /* CS ISR                    */\r
+    defaultISR,                             /* PCM ISR                   */\r
+    defaultISR,                             /* WDT ISR                   */\r
+    defaultISR,                             /* FPU ISR                   */\r
+    defaultISR,                             /* FLCTL ISR                 */\r
+    defaultISR,                             /* COMP0 ISR                 */\r
+    defaultISR,                             /* COMP1 ISR                 */\r
+    defaultISR,                             /* TA0_0 ISR                 */\r
+    defaultISR,                             /* TA0_N ISR                 */\r
+    defaultISR,                             /* TA1_0 ISR                 */\r
+    defaultISR,                             /* TA1_N ISR                 */\r
+    defaultISR,                             /* TA2_0 ISR                 */\r
+    defaultISR,                             /* TA2_N ISR                 */\r
+    defaultISR,                             /* TA3_0 ISR                 */\r
+    defaultISR,                             /* TA3_N ISR                 */\r
+    defaultISR,                             /* EUSCIA0 ISR               */\r
+    defaultISR,                             /* EUSCIA1 ISR               */\r
+    defaultISR,                             /* EUSCIA2 ISR               */\r
+    defaultISR,                             /* EUSCIA3 ISR               */\r
+    defaultISR,                             /* EUSCIB0 ISR               */\r
+    defaultISR,                             /* EUSCIB1 ISR               */\r
+    defaultISR,                             /* EUSCIB2 ISR               */\r
+    defaultISR,                             /* EUSCIB3 ISR               */\r
+    defaultISR,                             /* ADC14 ISR                 */\r
+    defaultISR,                             /* T32_INT1 ISR              */\r
+    defaultISR,                             /* T32_INT2 ISR              */\r
+    defaultISR,                             /* T32_INTC ISR              */\r
+    defaultISR,                             /* AES ISR                   */\r
+    defaultISR,                             /* RTC ISR                   */\r
+    defaultISR,                             /* DMA_ERR ISR               */\r
+    defaultISR,                             /* DMA_INT3 ISR              */\r
+    defaultISR,                             /* DMA_INT2 ISR              */\r
+    defaultISR,                             /* DMA_INT1 ISR              */\r
+    defaultISR,                             /* DMA_INT0 ISR              */\r
+    defaultISR,                             /* PORT1 ISR                 */\r
+    defaultISR,                             /* PORT2 ISR                 */\r
+    defaultISR,                             /* PORT3 ISR                 */\r
+    defaultISR,                             /* PORT4 ISR                 */\r
+    defaultISR,                             /* PORT5 ISR                 */\r
+    defaultISR,                             /* PORT6 ISR                 */\r
+    defaultISR,                             /* Reserved 41               */\r
+    defaultISR,                             /* Reserved 42               */\r
+    defaultISR,                             /* Reserved 43               */\r
+    defaultISR,                             /* Reserved 44               */\r
+    defaultISR,                             /* Reserved 45               */\r
+    defaultISR,                             /* Reserved 46               */\r
+    defaultISR,                             /* Reserved 47               */\r
+    defaultISR,                             /* Reserved 48               */\r
+    defaultISR,                             /* Reserved 49               */\r
+    defaultISR,                             /* Reserved 50               */\r
+    defaultISR,                             /* Reserved 51               */\r
+    defaultISR,                             /* Reserved 52               */\r
+    defaultISR,                             /* Reserved 53               */\r
+    defaultISR,                             /* Reserved 54               */\r
+    defaultISR,                             /* Reserved 55               */\r
+    defaultISR,                             /* Reserved 56               */\r
+    defaultISR,                             /* Reserved 57               */\r
+    defaultISR,                             /* Reserved 58               */\r
+    defaultISR,                             /* Reserved 59               */\r
+    defaultISR,                             /* Reserved 60               */\r
+    defaultISR,                             /* Reserved 61               */\r
+    defaultISR,                             /* Reserved 62               */\r
+    defaultISR                              /* Reserved 63               */\r
+};\r
+\r
+\r
+/* This is the code that gets called when the processor first starts execution */\r
+/* following a reset event.  Only the absolutely necessary set is performed,   */\r
+/* after which the application supplied entry() routine is called.  Any fancy  */\r
+/* actions (such as making decisions based on the reset cause register, and    */\r
+/* resetting the bits in that register) are left solely in the hands of the    */\r
+/* application.                                                                */\r
+void resetISR(void)\r
+{\r
+    SystemInit();\r
+\r
+    /* Jump to the CCS C Initialization Routine. */\r
+    __asm("    .global _c_int00\n"\r
+          "    b.w     _c_int00");\r
+}\r
+\r
+/* This is the code that gets called when the processor receives a NMI.  This  */\r
+/* simply enters an infinite loop, preserving the system state for examination */\r
+/* by a debugger.                                                              */\r
+static void nmiISR(void)\r
+{\r
+    /* Fault trap exempt from ULP advisor */\r
+    #pragma diag_push\r
+    #pragma CHECK_ULP("-2.1")\r
+\r
+    /* Enter an infinite loop. */\r
+    while(1)\r
+    {\r
+    }\r
+\r
+    #pragma diag_pop\r
+}\r
+\r
+\r
+/* This is the code that gets called when the processor receives a fault        */\r
+/* interrupt.  This simply enters an infinite loop, preserving the system state */\r
+/* for examination by a debugger.                                               */\r
+static void faultISR(void)\r
+{\r
+    /* Fault trap exempt from ULP advisor */\r
+    #pragma diag_push\r
+    #pragma CHECK_ULP("-2.1")\r
+\r
+    /* Enter an infinite loop. */\r
+    while(1)\r
+    {\r
+    }\r
+\r
+    #pragma diag_pop\r
+}\r
+\r
+\r
+/* This is the code that gets called when the processor receives an unexpected  */\r
+/* interrupt.  This simply enters an infinite loop, preserving the system state */\r
+/* for examination by a debugger.                                               */\r
+static void defaultISR(void)\r
+{\r
+    /* Fault trap exempt from ULP advisor */\r
+    #pragma diag_push\r
+    #pragma CHECK_ULP("-2.1")\r
+\r
+    /* Enter an infinite loop. */\r
+    while(1)\r
+    {\r
+    }\r
+\r
+    #pragma diag_pop\r
+}\r
+\r
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c
new file mode 100644 (file)
index 0000000..fb2b92e
--- /dev/null
@@ -0,0 +1,399 @@
+/**************************************************************************//**\r
+* @file     system_msp432p401r.c\r
+* @brief    CMSIS Cortex-M4F Device Peripheral Access Layer Source File for\r
+*           MSP432P401R\r
+* @version  V2.1.0\r
+* @date     2016-01-26\r
+*\r
+* @note     View configuration instructions embedded in comments\r
+*\r
+******************************************************************************/\r
+//*****************************************************************************\r
+//\r
+// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions\r
+// are met:\r
+//\r
+//  Redistributions of source code must retain the above copyright\r
+//  notice, this list of conditions and the following disclaimer.\r
+//\r
+//  Redistributions in binary form must reproduce the above copyright\r
+//  notice, this list of conditions and the following disclaimer in the\r
+//  documentation and/or other materials provided with the\r
+//  distribution.\r
+//\r
+//  Neither the name of Texas Instruments Incorporated nor the names of\r
+//  its contributors may be used to endorse or promote products derived\r
+//  from this software without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//\r
+//*****************************************************************************\r
+\r
+#include <stdint.h>\r
+#include "msp.h"\r
+\r
+/*--------------------- Configuration Instructions ----------------------------\r
+   1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:\r
+   #define __HALT_WDT       1\r
+   2. Insert your desired CPU frequency in Hz at:\r
+   #define __SYSTEM_CLOCK   12000000\r
+   3. If you prefer the DC-DC power regulator (more efficient at higher\r
+       frequencies), set the __REGULATOR to 1:\r
+   #define __REGULATOR      1\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/*--------------------- Watchdog Timer Configuration ------------------------*/\r
+//  Halt the Watchdog Timer\r
+//     <0> Do not halt the WDT\r
+//     <1> Halt the WDT\r
+#define __HALT_WDT         1\r
+\r
+/*--------------------- CPU Frequency Configuration -------------------------*/\r
+//  CPU Frequency\r
+//     <1500000> 1.5 MHz\r
+//     <3000000> 3 MHz\r
+//     <12000000> 12 MHz\r
+//     <24000000> 24 MHz\r
+//     <48000000> 48 MHz\r
+#define  __SYSTEM_CLOCK    3000000\r
+\r
+/*--------------------- Power Regulator Configuration -----------------------*/\r
+//  Power Regulator Mode\r
+//     <0> LDO\r
+//     <1> DC-DC\r
+#define __REGULATOR        0\r
+\r
+/*----------------------------------------------------------------------------\r
+   Define clocks, used for SystemCoreClockUpdate()\r
+ *---------------------------------------------------------------------------*/\r
+#define __VLOCLK           10000\r
+#define __MODCLK           24000000\r
+#define __LFXT             32768\r
+#define __HFXT             48000000\r
+\r
+/*----------------------------------------------------------------------------\r
+   Clock Variable definitions\r
+ *---------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Updates the SystemCoreClock with current core Clock\r
+ *         retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+    uint32_t source, divider;\r
+    uint8_t dividerValue;\r
+\r
+    float dcoConst;\r
+    int32_t calVal;\r
+    uint32_t centeredFreq;\r
+    int16_t dcoTune;\r
+\r
+    divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;\r
+    dividerValue = 1 << divider;\r
+    source = CS->CTL1 & CS_CTL1_SELM_MASK;\r
+\r
+    switch(source)\r
+    {\r
+    case CS_CTL1_SELM__LFXTCLK:\r
+        if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))\r
+        {\r
+            // Clear interrupt flag\r
+            CS->KEY = CS_KEY_VAL;\r
+            CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;\r
+            CS->KEY = 1;\r
+\r
+            if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))\r
+            {\r
+                if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))\r
+                {\r
+                    SystemCoreClock = (128000 / dividerValue);\r
+                }\r
+                else\r
+                {\r
+                    SystemCoreClock = (32000 / dividerValue);\r
+                }\r
+            }\r
+            else\r
+            {\r
+                SystemCoreClock = __LFXT / dividerValue;\r
+            }\r
+        }\r
+        else\r
+        {\r
+            SystemCoreClock = __LFXT / dividerValue;\r
+        }\r
+        break;\r
+    case CS_CTL1_SELM__VLOCLK:\r
+        SystemCoreClock = __VLOCLK / dividerValue;\r
+        break;\r
+    case CS_CTL1_SELM__REFOCLK:\r
+        if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))\r
+        {\r
+            SystemCoreClock = (128000 / dividerValue);\r
+        }\r
+        else\r
+        {\r
+            SystemCoreClock = (32000 / dividerValue);\r
+        }\r
+        break;\r
+    case CS_CTL1_SELM__DCOCLK:\r
+        dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;\r
+    \r
+        switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)\r
+        {\r
+        case CS_CTL0_DCORSEL_0:\r
+            centeredFreq = 1500000;\r
+            break;\r
+        case CS_CTL0_DCORSEL_1:\r
+            centeredFreq = 3000000;\r
+            break;\r
+        case CS_CTL0_DCORSEL_2:\r
+            centeredFreq = 6000000;\r
+            break;\r
+        case CS_CTL0_DCORSEL_3:\r
+            centeredFreq = 12000000;\r
+            break;\r
+        case CS_CTL0_DCORSEL_4:\r
+            centeredFreq = 24000000;\r
+            break;\r
+        case CS_CTL0_DCORSEL_5:\r
+            centeredFreq = 48000000;\r
+            break;\r
+        }\r
+\r
+        if(dcoTune == 0)\r
+        {\r
+            SystemCoreClock = centeredFreq;\r
+        }\r
+        else\r
+        {\r
+\r
+            if(dcoTune & 0x1000)\r
+            {\r
+                dcoTune = dcoTune | 0xF000;\r
+            }\r
+\r
+            if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))\r
+            {\r
+                dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);\r
+                calVal = TLV->DCOER_FCAL_RSEL04;\r
+            }\r
+            /* Internal Resistor */\r
+            else\r
+            {\r
+                dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);\r
+                calVal = TLV->DCOIR_FCAL_RSEL04;\r
+            }\r
+\r
+            SystemCoreClock = (uint32_t) ((centeredFreq)\r
+                               / (1\r
+                                    - ((dcoConst * dcoTune)\r
+                                            / (8 * (1 + dcoConst * (768 - calVal))))));\r
+        }\r
+        break;\r
+    case CS_CTL1_SELM__MODOSC:\r
+        SystemCoreClock = __MODCLK / dividerValue;\r
+        break;\r
+    case CS_CTL1_SELM__HFXTCLK:\r
+        if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))\r
+        {\r
+            // Clear interrupt flag\r
+            CS->KEY = CS_KEY_VAL;\r
+            CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;\r
+            CS->KEY = 1;\r
+\r
+            if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))\r
+            {\r
+                if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))\r
+                {\r
+                    SystemCoreClock = (128000 / dividerValue);\r
+                }\r
+                else\r
+                {\r
+                    SystemCoreClock = (32000 / dividerValue);\r
+                }\r
+            }\r
+            else\r
+            {\r
+                SystemCoreClock = __HFXT / dividerValue;\r
+            }\r
+        }\r
+        else\r
+        {\r
+            SystemCoreClock = __HFXT / dividerValue;\r
+        }\r
+        break;\r
+    }\r
+}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *\r
+ * Performs the following initialization steps:\r
+ *     1. Enables the FPU\r
+ *     2. Halts the WDT if requested\r
+ *     3. Enables all SRAM banks\r
+ *     4. Sets up power regulator and VCORE\r
+ *     5. Enable Flash wait states if needed\r
+ *     6. Change MCLK to desired frequency\r
+ *     7. Enable Flash read buffering\r
+ */\r
+void SystemInit(void)\r
+{\r
+    // Enable FPU if used\r
+    #if (__FPU_USED == 1)                              /* __FPU_USED is defined in core_cm4.h */\r
+    SCB->CPACR |= ((3UL << 10 * 2) |                   /* Set CP10 Full Access */\r
+                   (3UL << 11 * 2));                   /* Set CP11 Full Access */\r
+    #endif\r
+\r
+    #if (__HALT_WDT == 1)\r
+    WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;         // Halt the WDT\r
+    #endif\r
+\r
+    SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN;   // Enable all SRAM banks\r
+\r
+    #if (__SYSTEM_CLOCK == 1500000)                                  // 1.5 MHz\r
+    // Default VCORE is LDO VCORE0 so no change necessary\r
+\r
+    // Switches LDO VCORE0 to DCDC VCORE0 if requested\r
+    #if __REGULATOR\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    #endif\r
+\r
+    // No flash wait states necessary\r
+\r
+    // DCO = 1.5 MHz; MCLK = source\r
+    CS->KEY = CS_KEY_VAL;                                 // Unlock CS module for register access\r
+    CS->CTL0 = CS_CTL0_DCORSEL_0;                                // Set DCO to 1.5MHz\r
+    CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK;  // Select MCLK as DCO source\r
+    CS->KEY = 0;\r
+\r
+    // Set Flash Bank read buffering\r
+    FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+    FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+\r
+    #elif (__SYSTEM_CLOCK == 3000000)                                  // 3 MHz\r
+    // Default VCORE is LDO VCORE0 so no change necessary\r
+\r
+    // Switches LDO VCORE0 to DCDC VCORE0 if requested\r
+    #if __REGULATOR\r
+    while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;\r
+    while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);\r
+    #endif\r
+\r
+    // No flash wait states necessary\r
+\r
+    // DCO = 3 MHz; MCLK = source\r
+    CS->KEY = CS_KEY_VAL;                                                         // Unlock CS module for register access\r
+    CS->CTL0 = CS_CTL0_DCORSEL_1;                                                  // Set DCO to 1.5MHz\r
+    CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK;  // Select MCLK as DCO source\r
+    CS->KEY = 0;\r
+\r
+    // Set Flash Bank read buffering\r
+    FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+    FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+\r
+    #elif (__SYSTEM_CLOCK == 12000000)                                // 12 MHz\r
+    // Default VCORE is LDO VCORE0 so no change necessary\r
+\r
+    // Switches LDO VCORE0 to DCDC VCORE0 if requested\r
+    #if __REGULATOR\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    #endif\r
+\r
+    // No flash wait states necessary\r
+\r
+    // DCO = 12 MHz; MCLK = source\r
+    CS->KEY = CS_KEY_VAL;                                                         // Unlock CS module for register access\r
+    CS->CTL0 = CS_CTL0_DCORSEL_3;                                                  // Set DCO to 12MHz\r
+    CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK;  // Select MCLK as DCO source\r
+    CS->KEY = 0;\r
+\r
+    // Set Flash Bank read buffering\r
+    FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+    FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+\r
+    #elif (__SYSTEM_CLOCK == 24000000)                                // 24 MHz\r
+    // Default VCORE is LDO VCORE0 so no change necessary\r
+\r
+    // Switches LDO VCORE0 to DCDC VCORE0 if requested\r
+    #if __REGULATOR\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    #endif\r
+\r
+    // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)\r
+    FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;\r
+    FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;\r
+\r
+    // DCO = 24 MHz; MCLK = source\r
+    CS->KEY = CS_KEY_VAL;                                                         // Unlock CS module for register access\r
+    CS->CTL0 = CS_CTL0_DCORSEL_4;                                                  // Set DCO to 24MHz\r
+    CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK;  // Select MCLK as DCO source\r
+    CS->KEY = 0;\r
+\r
+    // Set Flash Bank read buffering\r
+    FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+    FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+\r
+    #elif (__SYSTEM_CLOCK == 48000000)                                // 48 MHz\r
+    // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+\r
+    // Switches LDO VCORE1 to DCDC VCORE1 if requested\r
+    #if __REGULATOR\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;\r
+    while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));\r
+    #endif\r
+\r
+    // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)\r
+    FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;\r
+    FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;\r
+\r
+    // DCO = 48 MHz; MCLK = source\r
+    CS->KEY = CS_KEY_VAL;                                                         // Unlock CS module for register access\r
+    CS->CTL0 = CS_CTL0_DCORSEL_5;                                                  // Set DCO to 48MHz\r
+    CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK;  // Select MCLK as DCO source\r
+    CS->KEY = 0;\r
+\r
+    // Set Flash Bank read buffering\r
+    FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);\r
+    FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);\r
+    #endif\r
+\r
+}\r
+\r