From: Borja Martinez Date: Fri, 16 Dec 2016 16:39:22 +0000 (+0100) Subject: Removed aold version MSP432 X-Git-Url: https://git.ti.com/gitweb?p=i3-mote%2Fi3-mote.git;a=commitdiff_plain;h=199cad64eb7f25e2263049ca41c349ceb16e7db5 Removed aold version MSP432 --- diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c deleted file mode 100644 index 6240674..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c +++ /dev/null @@ -1,191 +0,0 @@ -/****************************************************************************** - * MSP432 SPI - 3-wire Master Interface to on-board M24P40 - * - * Reads M25P40 Chip ID: - * - * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 12MHz - * - * - * MSP432P401 - * ----------------- - * | | - * | P1.4|-> FLASH_SPI_CSN (GPIO) - * | | - * | P1.5|-> FLASH_SPI_CLK (UCB0CLK) - * | | - * | P1.6|-> FLASH_SPI_MOSI_PIN (UCB0SIMO) - * | | - * | P1.7|<- FLASH_SPI_MISO_PIN (UCB0SOMI) - * | | - * - * Author: B.Martinez -*******************************************************************************/ -#include "i3mote.h" - - -/* DriverLib Includes */ -#include "driverlib.h" - -/* Standard Includes */ -#include -#include -#include -#include - -/* Statics */ -static volatile uint8_t RXData = 0; -static volatile uint8_t RXDataCnt = 0; -static uint8_t TXData = 0; - -#define SYSFREQ 12000000 - -/* SPI Master Configuration Parameter */ -const eUSCI_SPI_MasterConfig spiMasterConfig = -{ - EUSCI_A_SPI_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - SYSFREQ, // SMCLK = DCO = 12MHZ - 100000, // SPICLK = 100kbps - EUSCI_A_SPI_MSB_FIRST, // MSB First - EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase (Default) - EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // High polarity - EUSCI_A_SPI_3PIN -}; - - -int main(void) -{ - volatile uint32_t ii; - - /* Halting WDT */ - WDT_A_holdTimer(); - - /* Initializes Clock System */ - MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); - - - /* LEDS as output */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDR|LEDG); - MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDR|LEDG); - - - /* CS Configuring P3.0 as output */ - MAP_GPIO_setAsOutputPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN); - MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN); - - /* SPI */ - GPIO_setAsPeripheralModuleFunctionInputPin(FLASH_SPI_PORT, - FLASH_SPI_CLK_PIN | FLASH_SPI_MISO_PIN | FLASH_SPI_MOSI_PIN, GPIO_PRIMARY_MODULE_FUNCTION); - - - /* Configuring SPI in 3wire master mode */ - SPI_initMaster(EUSCI_A2_BASE, &spiMasterConfig); - - /* Enable SPI module */ - SPI_enableModule(EUSCI_A2_BASE); - - /* Enabling interrupts */ - SPI_enableInterrupt(EUSCI_A2_BASE, EUSCI_A_SPI_RECEIVE_INTERRUPT); - Interrupt_enableInterrupt(INT_EUSCIA2); - Interrupt_enableSleepOnIsrExit(); - - /* Polling to see if the TX buffer is ready */ - while (!(SPI_getInterruptStatus(EUSCI_A2_BASE,EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - // CS - MAP_GPIO_setOutputLowOnPin(FLASH_SPI_PORT,FLASH_SPI_CSN_PIN); - - /* Transmitting first command to slave */ - TXData=0x9E; - SPI_transmitData(EUSCI_A2_BASE, TXData); - - //P6OUT |= BIT0; - //MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6, LEDG); - /* Enabling MASTER interrupts */ - // MAP_Interrupt_enableMaster(); - - while(1) - { - MAP_PCM_gotoLPM0(); - } - -} - -//****************************************************************************** -// -//This is the EUSCI_A2 interrupt vector service routine. -// -//****************************************************************************** -void EUSCIA2_IRQHandler(void) -{ - uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_A2_BASE); - uint32_t jj; - - SPI_clearInterruptFlag(EUSCI_A2_BASE, status); - - if(status & EUSCI_A_SPI_RECEIVE_INTERRUPT) - { - - /* USCI_B0 TX buffer ready? */ - while (!(SPI_getInterruptStatus(EUSCI_A2_BASE, EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - RXData = SPI_receiveData(EUSCI_A2_BASE); - printf("%i %02X\n",RXDataCnt,RXData); - - switch(RXDataCnt){ - case 1: - if(RXData!=0x20){ - MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR); - exit(-1); - } - break; - case 2: - if(RXData!=0x71){ - MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR); - exit(-1); - } - break; - case 3: - if(RXData!=0x15){ - MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR); - exit(-1); - } - break; - case 4: - if(RXData!=0x10){ - MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR); - exit(-1); - } - break; - } - - RXDataCnt++; - - if(RXDataCnt==5){ - - MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN); - - /* Enable SysTick and Blink Forever */ - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(SYSFREQ/4); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_SysTick_enableInterrupt(); - - } - else{ - /* Send the next data packet */ - SPI_transmitData(EUSCI_A2_BASE, ++TXData); - } - - /* Delay between transmissions for slave to process information */ - for(jj=50;jj<50;jj++); - } -} - -void SysTick_Handler(void) -{ - MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG); -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c deleted file mode 100644 index c168bfa..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- -*/ - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -// extern void EUSCIB0_IRQHandler (void); -extern void EUSCIA2_IRQHandler (void); -extern void SysTick_Handler(void); - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - defaultISR, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - EUSCIA2_IRQHandler, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c deleted file mode 100644 index 93b5a72..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include - -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 1500000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c deleted file mode 100644 index a86aee1..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c +++ /dev/null @@ -1,247 +0,0 @@ -/****************************************************************************** - * MSP432 SPI - 3-wire Slave Echo - * - * This example shows how SPI slave echoes to SPI master using 3-wire mode. - * - * Incrementing data is sent by the master starting at 0x01. Received data is - * expected to be same as the previous transmission. eUSCI RX ISR is used to - * handle communication with the CPU, normally in LPM0. - * - * Transactions are started by the slave (MSP432) through IRQ line. - * - * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 12MHz - * - * MSP432P401 - * ----------------- - * | | - * | P2.3|<- Data In (UCA1SIMO) - * | | - * | P2.2|-> Data Out (UCA1SOMI) - * | | - * | P2.1|<- Serial Clock Out (UCA1CLK) - * | | - * | P2.0|<- CS - * | | - * - * Use with Test_CC2650_3wSPI_Master_MSP432_SlaveIRQ - * - * I3Mote: B.Martinez -*******************************************************************************/ - -#include "i3mote.h" - -/* DriverLib Includes */ -#include "driverlib.h" - -/* Standard Includes */ -#include -#include -#include - -//#define DEBUG_UART -#define UART_BAUD_115200 - -/* Statics */ -static volatile uint8_t RXData = 0; -static volatile uint8_t RXDataCnt = 0; - -static volatile uint8_t TXData = 0; - -const eUSCI_SPI_SlaveConfig spiSlaveConfig = -{ - EUSCI_B_SPI_MSB_FIRST, // MSB First - EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase - EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // Normal Polarity - EUSCI_B_SPI_3PIN // 3wire mode -}; - -/* UART Configuration Parameter. These are the configuration parameters to - * make the eUSCI A UART module to operate with a 9600 baud rate. - * These values were calculated using the online calculator that TI provides at: - * http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html - */ -#ifdef UART_BAUD_9600 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 78, // BRDIV = 78 - 2, // UCxBRF = 2 - 0, // UCxBRS = 0 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - -#ifdef UART_BAUD_115200 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 6, // BRDIV = 78 - 8, // UCxBRF = 2 - 0, // UCxBRS = 0 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - - -int main(void) -{ - volatile uint32_t ii; - - /* Halting WDT */ - WDT_A_holdTimer(); - - /* Set LED Pins as Output */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR); - MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDG|LEDR); - - /* Setting DCO to 12MHz */ - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - - /******************************************************************************/ - /******************************************************************************/ - - /* Configure INT Pin */ - MAP_GPIO_setOutputHighOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN); - MAP_GPIO_setAsOutputPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN); - - /* CS Configuring P2.0 as Input */ - MAP_GPIO_setAsInputPin(CC2650_SPI_PORT, CC2650_SPI_CSN_PIN); - - /* Selecting P2.1, P2.2 and P2.3 in SPI mode */ - GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P2, - CC2650_SPI_CLK_PIN | CC2650_SPI_MOSI_PIN | CC2650_SPI_MISO_PIN, GPIO_PRIMARY_MODULE_FUNCTION); - - /* Configuring SPI in 3wire master mode */ - //SPI_initMaster(EUSCI_A1_BASE, &spiMasterConfig); - SPI_initSlave(EUSCI_A1_BASE, &spiSlaveConfig); - - /* Enable SPI module */ - SPI_enableModule(EUSCI_A1_BASE); - - /* Enabling interrupts */ - SPI_enableInterrupt(EUSCI_A1_BASE, EUSCI_A_SPI_RECEIVE_INTERRUPT); - Interrupt_enableSleepOnIsrExit(); - Interrupt_enableInterrupt(INT_EUSCIA1); - MAP_Interrupt_enableMaster(); - - /******************************************************************************/ - /******************************************************************************/ - - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(12000000); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_SysTick_enableInterrupt(); - - /******************************************************************************/ - /******************************************************************************/ - -#ifdef DEBUG_UART - - /* Selecting P1.2 and P1.3 in UART mode */ - MAP_GPIO_setAsPeripheralModuleFunctionInputPin(UART_PORT, - UART_RX_PIN | UART_TX_PIN, GPIO_PRIMARY_MODULE_FUNCTION); - - /* Configuring UART Module */ - MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig); - - /* Enable UART module */ - MAP_UART_enableModule(EUSCI_A0_BASE); - - /* Enabling UART interrupts */ - /* - * MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT); - * MAP_Interrupt_enableInterrupt(INT_EUSCIA0); - */ -#endif - - /******************************************************************************/ - /******************************************************************************/ - - - PCM_gotoLPM0(); - __no_operation(); -} - -//****************************************************************************** -// -//This is the EUSCI_A1 interrupt vector service routine. -// -//****************************************************************************** -void EUSCIA1_IRQHandler(void) -{ - - int i; - - uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_A1_BASE); - - SPI_clearInterruptFlag(EUSCI_A1_BASE, status); - - if(status & EUSCI_A_SPI_RECEIVE_INTERRUPT) - { - - MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6,GPIO_PIN3); - - RXData = SPI_receiveData(EUSCI_A1_BASE); - RXDataCnt++; - - printf("Cnt: %d Rx: %02X\n",RXDataCnt,RXData); - - /* Extrenal UART Debug */ - #ifdef DEBUG_UART - MAP_UART_transmitData(EUSCI_A0_BASE, TXData); - MAP_UART_transmitData(EUSCI_A0_BASE, RXData); - #endif - - /* Send the next data packet */ - - /* USCI_A1 TX buffer ready? */ - while (!(SPI_getInterruptStatus(EUSCI_A1_BASE, EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - SPI_transmitData(EUSCI_A1_BASE, RXData); - - for(i=0;i<20000;i++); - MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6,GPIO_PIN3); - - } -} - - -void SysTick_Handler(void) -{ - int i; - /* Generate Periodic Interrupt */ - MAP_GPIO_setOutputLowOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN); - for(i=0;i<10000;i++); - MAP_GPIO_setOutputHighOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN); - - //MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6, GPIO_PIN2); - -} - -//****************************************************************************** -/* EUSCI A0 UART ISR - Echoes data back to PC host */ -//****************************************************************************** -/* - * - * void EUSCIA0_IRQHandler(void) - * { - * uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE); - * - * MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status); - * - * if(status & EUSCI_A_UART_RECEIVE_INTERRUPT) - * { - * MAP_UART_transmitData(EUSCI_A0_BASE, MAP_UART_receiveData(EUSCI_A0_BASE)); - * } - * - * } - * - */ diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c deleted file mode 100644 index 47af010..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- -*/ - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -extern void EUSCIA1_IRQHandler (void); -extern void EUSCIA0_IRQHandler (void); -extern void SysTick_Handler (void); - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - defaultISR, /* EUSCIA0 ISR */ - EUSCIA1_IRQHandler, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c deleted file mode 100644 index 93b5a72..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include - -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 1500000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c deleted file mode 100644 index 0ad179c..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c +++ /dev/null @@ -1,80 +0,0 @@ -/******************************************************************************* - * MSP432 Blink - * - * Description: - * Blinks two LEDs using SysTick (which is sourced from MCLK). - * - * Configuration: - * Starts the DCO to 12MHz and sources MCLK from it. - * BT1 pauses blinking. - * - * - * MSP432P401 - * ------------------ - * /|\| | - * --|RST | - * | |---> LEDG - * BT1 --->| |---> LEDR - * | | - * | < 12Mhz DCO > | - * | | - * - * Author: B.Martinez - ******************************************************************************/ -#include "i3mote.h" - -/* DriverLib Includes */ -#include "driverlib.h" - -/* Standard Includes */ -#include -#include - - -int main(void) -{ - /* Halting the Watchdog */ - MAP_WDT_A_holdTimer(); - - /* Set Button Pin as Input */ - MAP_GPIO_setAsInputPin(HID_PORT,BUTTON); - - /* Set LED Pins as Output */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR); - - /* Set LED Initial Value */ - MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDG); - MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDR); - //MAP_GPIO_setOutputHighOnPin(HID_PORT, LEDR); - - /* Setting the external clock frequency (This API is optional) */ - CS_setExternalClockSourceFrequency(32000,12000000); - - /* Initializes MCLK Clocks System with DCO */ - MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1); - - /* - * Configuring SysTick to trigger at 6000000 - * MCLK is 12MHz so this will make it toggle every 0.5s - */ - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(6000000); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_SysTick_enableInterrupt(); - - /* Enabling MASTER interrupts */ - MAP_Interrupt_enableMaster(); - - while (1) - { - MAP_PCM_gotoLPM0(); - } -} - -void SysTick_Handler(void) -{ - if(MAP_GPIO_getInputPinValue(HID_PORT,BUTTON)){ - MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6, GPIO_PIN2|GPIO_PIN3); - } -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c deleted file mode 100644 index d5f9a14..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//***************************************************************************** -// -// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP432 Family Interrupt Vector Table for CGT -// -//**************************************************************************** - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -extern void SysTick_Handler(void); - - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - defaultISR, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c deleted file mode 100644 index 4dcf1da..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ - -//***************************************************************************** - -#include -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 12000000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c deleted file mode 100644 index e4df695..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* - * MSP432 Clock System - HFXT Startup - * - * Description: - * - * HFXTAL: - * Starts the 48MHz crystal attached to HFXTIN/HFXTOUT - * Sources MCLK from the crystal - * - * LFXTL: - * Starts the 32khz crystal attached to LFXTIN/LFXTOUT - * Sources AMCLK from crystal - * - * Internal DCO: - * Starts the DCO - * Sources SMCLK from DCO - * - * Blinks LEDs using SysTick (which is sourced from MCLK). - * - * - * - * MSP432P401 - * ------------------ - * /|\| | - * | | | - * --|RST P8.5 |---> LED - * | | - * | PJ.3 HFXTIN |<-------- - * | | < 48Mhz xTal > - * | PJ.2 HFXTOUT |<-------- - * | | - * | PJ.0 LFXIN |<-------- - * | | < 32khz xTal > - * | PJ.1 LFXOUT |<-------- - * | | - * | P4.2 |--> ACLK - 32.768 KHz - * | P4.3 |--> MCLK - 12.000 MHz - * | P4.4 |--> HSMCLK - 6.000 MHz - * | P7.0 |--> SMCLK - * | | - * - * Author: Timothy Logan - * Rev: B.Martinez - ******************************************************************************/ -#include "i3mote.h" - -/* DriverLib Includes */ -#include "driverlib.h" - -/* Standard Includes */ -#include -#include - -int main(void) -{ - /* Halting the Watchdog */ - MAP_WDT_A_holdTimer(); - - /* Configuring pins for peripheral/crystal usage*/ - /* LFXTAL */ - MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_PJ, - GPIO_PIN0 | GPIO_PIN1, GPIO_PRIMARY_MODULE_FUNCTION); - - /* HFXTL */ - MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_PJ, - GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION); - - /* Clocks Output */ - GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P4, - GPIO_PIN2|GPIO_PIN3|GPIO_PIN4, GPIO_PRIMARY_MODULE_FUNCTION); - GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, - GPIO_PIN0, GPIO_PRIMARY_MODULE_FUNCTION); - - /* LEDs */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR); - MAP_GPIO_setOutputHighOnPin(HID_PORT, LEDG|LEDR); - - /* Setting the external clock frequency. This API is optional */ - CS_setExternalClockSourceFrequency(32000,12000000); - - /* Starting HFXT in non-bypass mode without a timeout. Before we start - * we have to change VCORE to 1 to support the 48MHz frequency */ - MAP_PCM_setCoreVoltageLevel(PCM_VCORE1); - MAP_FlashCtl_setWaitState(FLASH_BANK0, 2); - MAP_FlashCtl_setWaitState(FLASH_BANK1, 2); - CS_startHFXT(false); - - /* Initializing MCLK to HFXT (effectively 48/4 MHz) */ - MAP_CS_initClockSignal(CS_MCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_4); - - /* Initializing ACLK to LFXT */ - CS_startLFXT(false); - MAP_CS_initClockSignal(CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1); - - - /* Initializes Aux. Clocks System with DCO */ - MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48); - MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8); - MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8); - - /* - * Configuring SysTick to trigger at 6000000 - * MCLK is 12MHz so this will make it toggle every 0.5s - * */ - - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(6000000); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_SysTick_enableInterrupt(); - - /* Enabling MASTER interrupts */ - MAP_Interrupt_enableMaster(); - - while (1) - { - MAP_PCM_gotoLPM0(); - } -} - -void SysTick_Handler(void) -{ - MAP_GPIO_toggleOutputOnPin(HID_PORT, LEDG|LEDR); -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c deleted file mode 100644 index d5f9a14..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//***************************************************************************** -// -// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP432 Family Interrupt Vector Table for CGT -// -//**************************************************************************** - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -extern void SysTick_Handler(void); - - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - defaultISR, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/system_msp432p401r.c deleted file mode 100644 index 3cd0694..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/system_msp432p401r.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 12000000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c deleted file mode 100644 index 8fc2001..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** - * MSP432 UART - PC Echo with 12MHz BRCLK - * - * Description: This demo echoes back characters received via a PC serial port. - * SMCLK/DCO is used as a clock source and the device is put in LPM0 - * The auto-clock enable feature is used by the eUSCI and SMCLK is turned off - * when the UART is idle and turned on when a receive edge is detected. - * Note that level shifter hardware is needed to shift between RS232 and MSP - * voltage levels. - * - * MSP432P401 - * ----------------- - * | | - * | | - * | | - * RST -| P1.3/UCA0TXD|----> PC (echo) - * | | - * | | - * | P1.2/UCA0RXD|<---- PC - * | | - * - * Author: Timothy Logan - * - * I3Mote Version: B.Martinez - * - * - * -*******************************************************************************/ -#include "i3mote.h" - -/* DriverLib Includes */ -#include "driverlib.h" - - -/* Standard Includes */ -#include -#include - -#define SYSFREQ 12000000 - -/* UART Configuration Parameter. These are the configuration parameters to - * make the eUSCI A UART module to operate with a 9600 baud rate. - * These values were calculated using the online calculator that TI provides at: - * http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html - */ - -#ifdef UART_BAUD_9600 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 78, // BRDIV = 78 - 2, // UCxBRF = 2 - 0, // UCxBRS = 0 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - -#ifdef UART_BAUD_115200 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 6, // BRDIV = 6 - 8, // UCxBRF = 8 - 32, // UCxBRS = 32 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - - - -int main(void) -{ - - /* Halting WDT */ - MAP_WDT_A_holdTimer(); - - /* Selecting P1.2 and P1.3 in UART mode */ - MAP_GPIO_setAsPeripheralModuleFunctionInputPin(UART_PORT, - UART_RX_PIN | UART_TX_PIN, GPIO_PRIMARY_MODULE_FUNCTION); - - /* Set LEDS as output */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR); - MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDG|LEDR); - - /* Setting DCO to 12MHz */ - #if SYSFREQ==12000000 - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - #else - #error "Undefinde CLock Frequency" - #endif - - /* Configuring UART Module */ - MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig); - - /* Enable UART module */ - MAP_UART_enableModule(EUSCI_A0_BASE); - - /* Enabling UART interrupts */ - MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT); - MAP_Interrupt_enableInterrupt(INT_EUSCIA0); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_Interrupt_enableMaster(); - - /* Enable SysTick (Toggle 0.5s) */ - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(SYSFREQ/2); - MAP_SysTick_enableInterrupt(); - - /* Enabling MASTER interrupts */ - MAP_Interrupt_enableMaster(); - - while(1) - { - MAP_PCM_gotoLPM0(); - } -} - -/* EUSCI A0 UART ISR - Echoes data back to PC host */ -void EUSCIA0_IRQHandler(void) -{ - uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE); - - MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status); - - if(status & EUSCI_A_UART_RECEIVE_INTERRUPT) - { - MAP_UART_transmitData(EUSCI_A0_BASE, MAP_UART_receiveData(EUSCI_A0_BASE)); - } - -} - -void SysTick_Handler(void) -{ - MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG); -} - - - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c deleted file mode 100644 index e7fcb9f..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//***************************************************************************** -// -// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP432 Family Interrupt Vector Table for CGT -// -//**************************************************************************** - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -extern void EUSCIA0_IRQHandler (void); -extern void SysTick_Handler(void); - - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - EUSCIA0_IRQHandler, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c deleted file mode 100644 index 9479e03..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 1500000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c deleted file mode 100644 index b30f071..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c +++ /dev/null @@ -1,202 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//**************************************************************************** -// -// HAL_I2C.c - Hardware abstraction layer for I2C with MSP432P401R -// -//**************************************************************************** - -#include -#include - - -/* I2C Master Configuration Parameter */ -const eUSCI_I2C_MasterConfig i2cConfig = -{ - EUSCI_B_I2C_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 12000000, // SMCLK = 48MHz - EUSCI_B_I2C_SET_DATA_RATE_100KBPS, // Desired I2C Clock of 100khz - 0, // No byte counter threshold - EUSCI_B_I2C_NO_AUTO_STOP // No Autostop -}; - -void Init_I2C_GPIO() -{ - /* Select I2C function for I2C_SCL(P6.5) */ - GPIO_setAsPeripheralModuleFunctionOutputPin( - GPIO_PORT_P3, - GPIO_PIN7, - //GPIO_PORT_P6, - //GPIO_PIN5, - //GPIO_PORT_P1, - //GPIO_PIN7, - GPIO_PRIMARY_MODULE_FUNCTION); - - /* Select I2C function for I2C_SDA(P6.4) */ - GPIO_setAsPeripheralModuleFunctionOutputPin( - GPIO_PORT_P3, - GPIO_PIN6, - //GPIO_PORT_P6, - //GPIO_PIN4, - //GPIO_PORT_P1, - //GPIO_PIN6, - GPIO_PRIMARY_MODULE_FUNCTION); -} - - -/***************************************************************************//** - * @brief Configures I2C - * @param none - * @return none - ******************************************************************************/ - -void I2C_init(void) -{ - /* Initialize USCI_B0 and I2C Master to communicate with slave devices*/ - I2C_initMaster(EUSCI_B2_BASE, &i2cConfig); - //I2C_initMaster(EUSCI_B2_BASE, &i2cConfig); - - /* Disable I2C module to make changes */ - I2C_disableModule(EUSCI_B2_BASE); - //I2C_disableModule(EUSCI_B2_BASE); - - /* Enable I2C Module to start operations */ - I2C_enableModule(EUSCI_B2_BASE); - //I2C_enableModule(EUSCI_B2_BASE); - - return; -} - - -/***************************************************************************//** - * @brief Reads data from the sensor - * @param writeByte Address of register to read from - * @return Register contents - ******************************************************************************/ - -unsigned char I2C_eeprom_read_byte(unsigned short addr) -{ - volatile int val = 0; - volatile int valScratch = 0; - - /* Set master to transmit mode PL */ - I2C_setMode(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_MODE); - - /* Clear any existing interrupt flag PL */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0); - - /* Wait until ready to write PL */ - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - /* Initiate start and send first character */ - I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(addr>>8)&0x00FF); - /* Wait for TX to finish */ - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - /* Send Next Character */ - I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(addr&0x00FF)); - /* Wait for TX to finish */ - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - /* Initiate stop only */ - I2C_masterSendMultiByteStop(EUSCI_B2_BASE); - /* Wait for Stop to finish */ - while(!I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_STOP_INTERRUPT)); - - /* - * Generate Start condition and set it to receive mode. - * This sends out the slave address and continues to read until you issue a STOP - */ - - I2C_setMode(EUSCI_B2_BASE,EUSCI_B_I2C_RECEIVE_MODE); - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - val=I2C_masterReceiveSingleByte(EUSCI_B2_BASE); - - /* Return temperature value */ - return val; -} - - -/***************************************************************************//** - * @brief Writes data to the sensor - * @param pointer Address of register you want to modify - * @param writeByte Data to be written to the specified register - * @return none - ******************************************************************************/ - -void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte) -{ - /* Set master to transmit mode PL */ - I2C_setMode(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_MODE); - - /* Clear any existing interrupt flag PL */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0); - - /* Wait until ready to write PL */ - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - /* Initiate start and send first character */ - I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(unsigned char)(pointer>>8)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - - I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(pointer&0x00FF)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - - I2C_masterSendMultiByteFinish(EUSCI_B2_BASE, - (unsigned char)(writeByte&0xFF)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - while (I2C_isBusBusy(EUSCI_B2_BASE)); - -} - - -void I2C_setslave(unsigned int slaveAdr) -{ - /* Specify slave address for I2C */ - //I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr); - I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr); - - /* Enable and clear the interrupt flag */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0); - //I2C_clearInterruptFlag(EUSCI_B2_BASE, - // EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0); - return; -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h deleted file mode 100644 index 917f385..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h +++ /dev/null @@ -1,48 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//**************************************************************************** -// -// HAL_I2C.h - Prototypes of hardware abstraction layer for I2C between -// MSP432P401R and OPT3001 -// -//**************************************************************************** - -#ifndef __HAL_I2C_H_ -#define __HAL_I2C_H_ - -void Init_I2C_GPIO(void); -void I2C_init(void); -unsigned char I2C_eeprom_read_byte(unsigned short); -void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte); -void I2C_setslave(unsigned int slaveAdr); - -#endif /* __HAL_I2C_H_ */ diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c deleted file mode 100644 index 6c38663..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c +++ /dev/null @@ -1,91 +0,0 @@ -//**************************************************************************** -// -// -// -//**************************************************************************** -#include "i3mote.h" - -/* MSP432 Incldues */ -#include "msp.h" -#include - -/* Standard Includes */ -#include -#include -#include - - -/* I2C Support */ -#include - - -/* Local Definitions */ -#define NPOS 256 // EEPROM positions to Read/Write - -void main(void) -{ - - unsigned short i=0; - unsigned short val; - - /* Halting WDT and disabling master interrupts */ - MAP_WDT_A_holdTimer(); - MAP_Interrupt_disableMaster(); - - /* Initializes Clock System */ - MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); - - /* Disable GPS VCC */ - MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P2,GPIO_PIN4); - MAP_GPIO_setAsOutputPin(GPIO_PORT_P2,GPIO_PIN4); - - /* LEDs */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR); - MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDG|LEDR); - - /* Initialize I2C communication */ - Init_I2C_GPIO(); - I2C_init(); - - I2C_setslave(EEPROM_SLAVE_ADDRESS); - - - for(i=0;i= 15009000 - ALIAS - { - SRAM_CODE (RWX): origin = 0x01000000 - SRAM_DATA (RW) : origin = 0x20000000 - } length = 0x00010000 -#else - /* Hint: If the user wants to use ram functions, please observe that SRAM_CODE */ - /* and SRAM_DATA memory areas are overlapping. You need to take measures to separate */ - /* data from code in RAM. This is only valid for Compiler version earlier than 15.09.0.STS.*/ - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -#endif -#endif -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - .binit : {} > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) - -#ifdef __TI_COMPILER_VERSION__ -#if __TI_COMPILER_VERSION__ >= 15009000 - .TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT) -#endif -#endif -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c deleted file mode 100644 index e8714ad..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,219 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401R Interrupt Vector Table and startup code for CCS TI ARM -* -*****************************************************************************/ - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -/* To be added by user */ - - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - defaultISR, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - defaultISR, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c deleted file mode 100644 index fb2b92e..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c +++ /dev/null @@ -1,399 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V2.1.0 -* @date 2016-01-26 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 3000000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.c deleted file mode 100644 index 1ee90a5..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.c +++ /dev/null @@ -1,250 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//**************************************************************************** -// -// HAL_I2C.c - Hardware abstraction layer for I2C with MSP432P401R -// -//**************************************************************************** - -#include -#include - - -/* I2C Master Configuration Parameter */ -const eUSCI_I2C_MasterConfig i2cConfig = -{ - EUSCI_B_I2C_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 12000000, // SMCLK = 12MHz - EUSCI_B_I2C_SET_DATA_RATE_100KBPS, // Desired I2C Clock of 100khz - 0, // No byte counter threshold - EUSCI_B_I2C_NO_AUTO_STOP // No Autostop -}; - -void Init_I2C_GPIO() -{ - /* Select I2C function for I2C_SCL(P3.7) */ - GPIO_setAsPeripheralModuleFunctionOutputPin( - GPIO_PORT_P3, - GPIO_PIN7, - GPIO_PRIMARY_MODULE_FUNCTION); - - /* Select I2C function for I2C_SDA(P3.6) */ - GPIO_setAsPeripheralModuleFunctionOutputPin( - GPIO_PORT_P3, - GPIO_PIN6, - GPIO_PRIMARY_MODULE_FUNCTION); -} - - -/***************************************************************************//** - * @brief Configures I2C - * @param none - * @return none - ******************************************************************************/ - -void I2C_init(void) -{ - /* Initialize USCI_B0 and I2C Master to communicate with slave devices*/ - I2C_initMaster(EUSCI_B2_BASE, &i2cConfig); - //I2C_initMaster(EUSCI_B2_BASE, &i2cConfig); - - /* Disable I2C module to make changes */ - I2C_disableModule(EUSCI_B2_BASE); - //I2C_disableModule(EUSCI_B2_BASE); - - /* Enable I2C Module to start operations */ - I2C_enableModule(EUSCI_B2_BASE); - //I2C_enableModule(EUSCI_B2_BASE); - - return; -} - - -/***************************************************************************//** - * @brief Reads data from the sensor - * @param writeByte Address of register to read from - * @return Register contents - ******************************************************************************/ - -unsigned short I2C_read16(unsigned char writeByte) -{ - volatile int val = 0; - volatile int valScratch = 0; - - /* Set master to transmit mode PL */ - I2C_setMode(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_MODE); - - /* Clear any existing interrupt flag PL */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0); - - /* Wait until ready to write PL */ - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - /* Initiate start and send first character */ - I2C_masterSendMultiByteStart(EUSCI_B2_BASE, writeByte); - - /* Wait for TX to finish */ - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - /* Initiate stop only */ - I2C_masterSendMultiByteStop(EUSCI_B2_BASE); - - /* Wait for Stop to finish */ - while(!I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_STOP_INTERRUPT)); - - /* - * Generate Start condition and set it to receive mode. - * This sends out the slave address and continues to read - * until you issue a STOP - */ - I2C_masterReceiveStart(EUSCI_B2_BASE); - - /* Wait for RX buffer to fill */ - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_RECEIVE_INTERRUPT0))); - - /* Read from I2C RX register */ - val = I2C_masterReceiveMultiByteNext(EUSCI_B2_BASE); - - /* Receive second byte then send STOP condition */ - valScratch = I2C_masterReceiveMultiByteFinish(EUSCI_B2_BASE); - - /* Shift val to top MSB */ - val = (val << 8); - /* Read from I2C RX Register and write to LSB of val */ - val |= valScratch; - - /* Return temperature value */ - return (int16_t)val; -} - - - - -unsigned char I2C_read8(unsigned short addr) -{ - volatile int val = 0; - volatile int valScratch = 0; - - /* Set master to transmit mode PL */ - I2C_setMode(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_MODE); - - /* Clear any existing interrupt flag PL */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0); - - /* Wait until ready to write PL */ - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - /* Initiate start and send first character */ - I2C_masterSendMultiByteStart(EUSCI_B2_BASE,addr&0x00FF); - /* Wait for TX to finish */ - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - /* Send Next Character */ - //I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(addr&0x00FF)); - /* Wait for TX to finish */ - //while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - /* Initiate stop only */ - I2C_masterSendMultiByteStop(EUSCI_B2_BASE); - /* Wait for Stop to finish */ - while(!I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_STOP_INTERRUPT)); - - /* - * Generate Start condition and set it to receive mode. - * This sends out the slave address and continues to read until you issue a STOP - */ - - I2C_setMode(EUSCI_B2_BASE,EUSCI_B_I2C_RECEIVE_MODE); - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - val=I2C_masterReceiveSingleByte(EUSCI_B2_BASE); - - /* Return temperature value */ - return val; -} - - - -/***************************************************************************//** - * @brief Writes data to the sensor - * @param pointer Address of register you want to modify - * @param writeByte Data to be written to the specified register - * @return none - ******************************************************************************/ - -void I2C_write16(unsigned short pointer, unsigned short writeByte) -{ - /* Set master to transmit mode PL */ - I2C_setMode(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_MODE); - - /* Clear any existing interrupt flag PL */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0); - - /* Wait until ready to write PL */ - while (I2C_isBusBusy(EUSCI_B2_BASE)); - - /* Initiate start and send first character */ - I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(unsigned char)(pointer>>8)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - - I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(pointer&0x00FF)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - - I2C_masterSendMultiByteFinish(EUSCI_B2_BASE, - (unsigned char)(writeByte&0xFF)); - while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0))); - - while (I2C_isBusBusy(EUSCI_B2_BASE)); - -} - - -void I2C_setslave(unsigned int slaveAdr) -{ - /* Specify slave address for I2C */ - I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr); - - /* Enable and clear the interrupt flag */ - I2C_clearInterruptFlag(EUSCI_B2_BASE, - EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0); - - return; -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.h deleted file mode 100644 index d8bf2c0..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.h +++ /dev/null @@ -1,50 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//**************************************************************************** -// -// HAL_I2C.h - Prototypes of hardware abstraction layer for I2C between -// MSP432P401R and OPT3001 -// -//**************************************************************************** - -#ifndef __HAL_I2C_H_ -#define __HAL_I2C_H_ - -void Init_I2C_GPIO(void); -void I2C_init(void); -unsigned short I2C_read16(unsigned char); -unsigned char I2C_read8(unsigned short writeByte); -void I2C_write16(unsigned short pointer, unsigned short writeByte); -void I2C_setslave(unsigned int slaveAdr); - - -#endif /* __HAL_I2C_H_ */ diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/i3mote.h deleted file mode 100644 index e27c845..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/i3mote.h +++ /dev/null @@ -1,62 +0,0 @@ -/* HID Rev.B */ -#define HID_PORT GPIO_PORT_P6 -#define LEDR GPIO_PIN2 -#define LEDG GPIO_PIN3 -#define BUTTON GPIO_PIN1 - -/* Rev.A -#define HID_PORT GPIO_PORT_P8 -#define LEDR GPIO_PIN5 -#define LEDG GPIO_PIN6 -#define BUTTON GPIO_PIN7 -*/ - -/* Power Control */ -#define CTL_PWR_PORT GPIO_PORT_P2 -#define GPS_PWR_nEN_PIN GPIO_PIN4 -#define SSM_PWR_nEN_PIN GPIO_PIN5 - - -/* Debg UART */ -#define UART_BAUD_115200 -#define UART_PORT GPIO_PORT_P1 -#define UART_TX_PIN GPIO_PIN3 -#define UART_RX_PIN GPIO_PIN2 - -/* Flash SPI */ -#define FLASH_SPI_PORT GPIO_PORT_P3 -#define FLASH_SPI_CSN_PIN GPIO_PIN0 -#define FLASH_SPI_CLK_PIN GPIO_PIN1 -#define FLASH_SPI_MISO_PIN GPIO_PIN2 -#define FLASH_SPI_MOSI_PIN GPIO_PIN3 - - -/* CC2650 SPI */ -#define CC2650_SPI_PORT GPIO_PORT_P2 -#define CC2650_SPI_CSN_PIN GPIO_PIN0 -#define CC2650_SPI_CLK_PIN GPIO_PIN1 -#define CC2650_SPI_MISO_PIN GPIO_PIN2 -#define CC2650_SPI_MOSI_PIN GPIO_PIN3 - -#define CC2650_IRQ_PORT GPIO_PORT_P4 -#define CC2650_IRQ_PIN GPIO_PIN0 - -/* On Board EEPROM 25xx256*/ -#define EEPROM_SLAVE_ADDRESS 0x50 - - -/* On Board Sensors */ -#define IN219 -#define OPT3001 -#define HDC1080 -#define BMP280 -#define MPU9250 -#define TMP007 - -#define Board_HDC1080_ADDR 0x40 -#define Board_INA219_ADDR 0x41 -#define Board_TMP007_ADDR 0x44 -#define Board_OPT3001_ADDR 0x45 -#define Board_MPU9250_ADDR 0x68 -#define Board_BMP280_ADDR 0x77 - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/main.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/main.c deleted file mode 100644 index a112ea0..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/main.c +++ /dev/null @@ -1,266 +0,0 @@ -//**************************************************************************** -// -//**************************************************************************** -#include "i3mote.h" -#include "HAL_I2C.h" - -/* DriverLib Includes */ -#include - -/* Standard Includes */ -#include -#include - - -/* UART Configuration Parameter. These are the configuration parameters to - * make the eUSCI A UART module to operate with a 9600 baud rate. - * These values were calculated using the online calculator that TI provides at: - * http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html - */ -#ifdef UART_BAUD_9600 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 78, // BRDIV = 78 - 2, // UCxBRF = 2 - 0, // UCxBRS = 0 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - -#ifdef UART_BAUD_115200 - const eUSCI_UART_Config uartConfig = - { - EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source - 6, // BRDIV = 6 - 8, // UCxBRF = 8 - 32, // UCxBRS = 32 - EUSCI_A_UART_NO_PARITY, // No Parity - EUSCI_A_UART_LSB_FIRST, // LSB First - EUSCI_A_UART_ONE_STOP_BIT, // One stop bit - EUSCI_A_UART_MODE, // UART mode - EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling - }; -#endif - -#define SYSFREQ 12000000 - -/* External UART */ -#undef UART - -/* - * Global Variables - */ -#define BUFF_SIZE 4 -char buffer[BUFF_SIZE]; -unsigned int i=0; -unsigned short val; - - -void exit_err(int val, int err){ - MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6, GPIO_PIN2); - exit(-1); -} - - -void main(void) -{ - /* Halting WDT and disabling master interrupts */ - MAP_WDT_A_holdTimer(); - MAP_Interrupt_disableMaster(); - - /* Initializes Clock System: Required Freq 12Mhz */ - MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); - MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); - - /* Set LED as outputs and Initial Value */ - MAP_GPIO_setAsOutputPin(HID_PORT,LEDR|LEDG); - MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDR|LEDG); - - /* Set ENA Pin as Output and Enable (Active Low) */ - MAP_GPIO_setAsOutputPin(CTL_PWR_PORT,GPS_PWR_nEN_PIN); - MAP_GPIO_setOutputLowOnPin(CTL_PWR_PORT,GPS_PWR_nEN_PIN); - - /* UART */ - #ifdef UART - /* Selecting P1.2 and P1.3 in UART mode */ - MAP_GPIO_setAsPeripheralModuleFunctionInputPin(UART_PORT, - UART_RX_PIN | UART_TX_PIN, GPIO_PRIMARY_MODULE_FUNCTION); - /* Configuring UART Module */ - MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig); - /* Enable UART module */ - MAP_UART_enableModule(EUSCI_A0_BASE); - /* Enabling UART interrupts */ - MAP_UART_enableInterrupt(EUSCI_A0_BASE,EUSCI_A_UART_RECEIVE_INTERRUPT); - MAP_Interrupt_enableInterrupt(INT_EUSCIA0); - MAP_Interrupt_enableSleepOnIsrExit(); - #endif - - /* Initialize I2C communication */ - Init_I2C_GPIO(); - I2C_init(); - #ifndef UART - printf("I2C Init\n\r"); - #endif - - /* INA219 */ - #ifdef INA219 - - I2C_setslave(Board_INA219_ADDR); - - val=I2C_read16(0x00); - - #ifndef UART - printf("INA219 ConfReg (default) 0x399F: %04X\n",val); - #endif - - if( (val&0xFFFF) != 0x399F) - exit_err(0x399F,val); - - #endif - - - - /* OPT3001 */ - #ifdef OPT3001 - - I2C_setslave(Board_OPT3001_ADDR); - - val=I2C_read16(0x7E); - #ifndef UART - printf("OPT3001 Manufactured ID 0x5449: %04X\n",val); - #endif - val=I2C_read16(0x7F); - - #ifndef UART - printf("OPT3001 Device ID 0x3001: %04X\n",val); - #endif - - if( (val&0xFFFF) != 0x3001) - exit_err(0x3001,val); - - #endif - - - /* HDC1080 */ - #ifdef HDC1080 - - I2C_setslave(Board_HDC1080_ADDR); - - val=I2C_read16(0xFE); - #ifndef UART - printf("HDC1080 Manufactured ID 0x5449: %04X\n",val); - #endif - - val=I2C_read16(0xFF); - #ifndef UART - printf("HDC1080 Device ID 0x1050: %04X\n",val); - #endif - - if( (val&0xFFFF) != 0x1050) - exit_err(0x1050,val); - - #endif - - - /* TMP007 */ - #ifdef TMP007 - - I2C_setslave(Board_TMP007_ADDR); - - val=I2C_read16(0x1E); - #ifndef UART - printf("TMP007 Manufactured ID 0x5449: %04X\n",val); - #endif - - val=I2C_read16(0x1F); - #ifndef UART - printf("TMP007 Device ID 0x0078: %04X\n",val); - #endif - - if( (val&0xFFFF) != 0x0078) - exit_err(0x0078,val); - #endif - - /* BMP280 */ - #ifdef BMP280 - - I2C_setslave(Board_BMP280_ADDR); - - val=I2C_read8(0xD0); - #ifndef UART - printf("BMP280 ID 0x58: %02X\n",val); - #endif - - if( (val&0xFF) != 0x58) - exit_err(0x58,val); - #endif - - /* MPU9250 */ - #ifdef MPU9250 - - I2C_setslave(Board_MPU9250_ADDR); - - val=I2C_read8(0x75); - #ifndef UART - printf("MPU9250 WHOIAM 0x71: %02X\n",val); - #endif - - if( (val&0xFF) != 0x71) - exit_err(0x71,val); - #endif - - /* Done */ - MAP_GPIO_setOutputHighOnPin(CTL_PWR_PORT,GPS_PWR_nEN_PIN); - - /* - * Configuring SysTick to toggle every 0.25s - */ - MAP_SysTick_enableModule(); - MAP_SysTick_setPeriod(SYSFREQ/4); - MAP_Interrupt_enableSleepOnIsrExit(); - MAP_SysTick_enableInterrupt(); - - /* Enabling MASTER interrupts */ - MAP_Interrupt_enableMaster(); - - while(1){ - MAP_PCM_gotoLPM0(); - } - -} - - -void SysTick_Handler(void) -{ - MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG); -} - -/* EUSCI A0 UART ISR - Nothing to do now */ -void EUSCIA0_IRQHandler(void) -{ - - /* - * EUSCI A0 UART ISR - Echoes data back to PC host - * - uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE); - MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status); - - if(status & EUSCI_A_UART_RECEIVE_INTERRUPT) - { - MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDR); - MAP_UART_transmitData(EUSCI_A0_BASE, MAP_UART_receiveData(EUSCI_A0_BASE)); - } - **/ -} - - - - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/msp432p401r.cmd deleted file mode 100644 index 346c191..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/msp432p401r.cmd +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Default linker command file for Texas Instruments MSP432P401R -* -* File creation date: 2015-09-03 -* -*****************************************************************************/ - ---retain=flashMailbox - -MEMORY -{ - MAIN (RX) : origin = 0x00000000, length = 0x00040000 - INFO (RX) : origin = 0x00200000, length = 0x00004000 - SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000 - SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000 -} - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* A heap size of 1024 bytes is recommended when you plan to use printf() */ -/* for debug output to the console window. */ -/* */ -/* --heap_size=1024 */ -/* --stack_size=512 */ -/* --library=rtsv7M4_T_le_eabi.lib */ - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs: > 0x00000000 - .text : > MAIN - .const : > MAIN - .cinit : > MAIN - .pinit : > MAIN - .init_array : > MAIN - - .flashMailbox : > 0x00200000 - - .vtable : > 0x20000000 - .data : > SRAM_DATA - .bss : > SRAM_DATA - .sysmem : > SRAM_DATA - .stack : > SRAM_DATA (HIGH) -} - -/* Symbolic definition of the WDTCTL register for RTS */ -WDTCTL_SYM = 0x4000480C; - diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/startup_msp432p401r_ccs.c deleted file mode 100644 index 0852500..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/startup_msp432p401r_ccs.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -//***************************************************************************** -// -// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP432 Family Interrupt Vector Table for CGT -// -//**************************************************************************** - -#include - -/* Forward declaration of the default fault handlers. */ -static void resetISR(void); -static void nmiISR(void); -static void faultISR(void); -static void defaultISR(void); - - -/* External declaration for the reset handler that is to be called when the */ -/* processor is started */ -extern void _c_int00(void); - -/* External declaration for system initialization function */ -extern void SystemInit(void); - -/* Linker variable that marks the top of the stack. */ -extern unsigned long __STACK_END; - - -/* External declarations for the interrupt handlers used by the application. */ -extern void EUSCIA0_IRQHandler (void); -extern void SysTick_Handler(void); - - -/* Interrupt vector table. Note that the proper constructs must be placed on this to */ -/* ensure that it ends up at physical address 0x0000.0000 or at the start of */ -/* the program if located at a start address other than 0. */ -#pragma RETAIN(interruptVectors) -#pragma DATA_SECTION(interruptVectors, ".intvecs") -void (* const interruptVectors[])(void) = -{ - (void (*)(void))((uint32_t)&__STACK_END), - /* The initial stack pointer */ - resetISR, /* The reset handler */ - nmiISR, /* The NMI handler */ - faultISR, /* The hard fault handler */ - defaultISR, /* The MPU fault handler */ - defaultISR, /* The bus fault handler */ - defaultISR, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - defaultISR, /* SVCall handler */ - defaultISR, /* Debug monitor handler */ - 0, /* Reserved */ - defaultISR, /* The PendSV handler */ - SysTick_Handler, /* The SysTick handler */ - defaultISR, /* PSS ISR */ - defaultISR, /* CS ISR */ - defaultISR, /* PCM ISR */ - defaultISR, /* WDT ISR */ - defaultISR, /* FPU ISR */ - defaultISR, /* FLCTL ISR */ - defaultISR, /* COMP0 ISR */ - defaultISR, /* COMP1 ISR */ - defaultISR, /* TA0_0 ISR */ - defaultISR, /* TA0_N ISR */ - defaultISR, /* TA1_0 ISR */ - defaultISR, /* TA1_N ISR */ - defaultISR, /* TA2_0 ISR */ - defaultISR, /* TA2_N ISR */ - defaultISR, /* TA3_0 ISR */ - defaultISR, /* TA3_N ISR */ - EUSCIA0_IRQHandler, /* EUSCIA0 ISR */ - defaultISR, /* EUSCIA1 ISR */ - defaultISR, /* EUSCIA2 ISR */ - defaultISR, /* EUSCIA3 ISR */ - defaultISR, /* EUSCIB0 ISR */ - defaultISR, /* EUSCIB1 ISR */ - defaultISR, /* EUSCIB2 ISR */ - defaultISR, /* EUSCIB3 ISR */ - defaultISR, /* ADC14 ISR */ - defaultISR, /* T32_INT1 ISR */ - defaultISR, /* T32_INT2 ISR */ - defaultISR, /* T32_INTC ISR */ - defaultISR, /* AES ISR */ - defaultISR, /* RTC ISR */ - defaultISR, /* DMA_ERR ISR */ - defaultISR, /* DMA_INT3 ISR */ - defaultISR, /* DMA_INT2 ISR */ - defaultISR, /* DMA_INT1 ISR */ - defaultISR, /* DMA_INT0 ISR */ - defaultISR, /* PORT1 ISR */ - defaultISR, /* PORT2 ISR */ - defaultISR, /* PORT3 ISR */ - defaultISR, /* PORT4 ISR */ - defaultISR, /* PORT5 ISR */ - defaultISR, /* PORT6 ISR */ - defaultISR, /* Reserved 41 */ - defaultISR, /* Reserved 42 */ - defaultISR, /* Reserved 43 */ - defaultISR, /* Reserved 44 */ - defaultISR, /* Reserved 45 */ - defaultISR, /* Reserved 46 */ - defaultISR, /* Reserved 47 */ - defaultISR, /* Reserved 48 */ - defaultISR, /* Reserved 49 */ - defaultISR, /* Reserved 50 */ - defaultISR, /* Reserved 51 */ - defaultISR, /* Reserved 52 */ - defaultISR, /* Reserved 53 */ - defaultISR, /* Reserved 54 */ - defaultISR, /* Reserved 55 */ - defaultISR, /* Reserved 56 */ - defaultISR, /* Reserved 57 */ - defaultISR, /* Reserved 58 */ - defaultISR, /* Reserved 59 */ - defaultISR, /* Reserved 60 */ - defaultISR, /* Reserved 61 */ - defaultISR, /* Reserved 62 */ - defaultISR /* Reserved 63 */ -}; - - -/* This is the code that gets called when the processor first starts execution */ -/* following a reset event. Only the absolutely necessary set is performed, */ -/* after which the application supplied entry() routine is called. Any fancy */ -/* actions (such as making decisions based on the reset cause register, and */ -/* resetting the bits in that register) are left solely in the hands of the */ -/* application. */ -void resetISR(void) -{ - SystemInit(); - - /* Jump to the CCS C Initialization Routine. */ - __asm(" .global _c_int00\n" - " b.w _c_int00"); -} - -/* This is the code that gets called when the processor receives a NMI. This */ -/* simply enters an infinite loop, preserving the system state for examination */ -/* by a debugger. */ -static void nmiISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives a fault */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void faultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} - - -/* This is the code that gets called when the processor receives an unexpected */ -/* interrupt. This simply enters an infinite loop, preserving the system state */ -/* for examination by a debugger. */ -static void defaultISR(void) -{ - /* Fault trap exempt from ULP advisor */ - #pragma diag_push - #pragma CHECK_ULP("-2.1") - - /* Enter an infinite loop. */ - while(1) - { - } - - #pragma diag_pop -} diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/system_msp432p401r.c deleted file mode 100644 index 9479e03..0000000 --- a/Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/system_msp432p401r.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * ------------------------------------------- - * MSP432 DriverLib - v3_10_00_09 - * ------------------------------------------- - * - * --COPYRIGHT--,BSD,BSD - * Copyright (c) 2014, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/**************************************************************************//** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version V1.00 -* @date 20-Oct-2015 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include "msp.h" - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 3000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK 1500000 - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 1 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; - FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -}