packages/ti/configs/omap54xx/DspAmmu.cfg

   1 /*
   2  * Copyright (c) 2012-2013, Texas Instruments Incorporated
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * *  Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  * *  Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * *  Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  *  ======== DspAmmu.cfg ========
  35  *
  36  *  An example configuration script used by DSP sample applications.
  37  */
  38
  39 /* -------------------------------- Cache ----------------------------------*/
  40 var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
  41 Cache.enableCache = true;
  42
  43 if (Cache.enableCache) {
  44     Cache.ocpL1.wrap = 1;
  45     Cache.ocpL1.wrbuffer = 1;
  46     Cache.ocpL1.prefetch = 0;
  47
  48     Cache.ocpL2.wrap = 1;
  49     Cache.ocpL2.wrbuffer = 1;
  50     Cache.ocpL2.prefetch = 0;
  51
  52     print("DSP Unicache = ON");
  53 }
  54 else {
  55     print("DSP Unicache = OFF");
  56 }
  57
  58 /* -------------------------------- AMMU -----------------------------------*/
  59 var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
  60
  61 /*********************** Small Pages *************************/
  62 /* Work-around for bug in BIOS 6.33.06.50 */
  63 AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
  64 AMMU.smallPages[1].logicalAddress = 0x01c30000;
  65 AMMU.smallPages[1].translationEnabled = AMMU.Enable_NO;
  66 AMMU.smallPages[1].size = AMMU.Small_4K;
  67 AMMU.smallPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  68 AMMU.smallPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  69
  70 /*********************** Medium Pages *************************/
  71 /* config medium page[0] to map 1MB VA 0x01d00000 to 0x01dFFFFF */
  72 /* ABE NC region */
  73 AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
  74 AMMU.mediumPages[0].logicalAddress = 0x01d00000;
  75 AMMU.mediumPages[0].size = AMMU.Medium_1M;
  76 AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  77 AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
  78 AMMU.mediumPages[0].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
  79 AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
  80 AMMU.mediumPages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  81 AMMU.mediumPages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;
  82 AMMU.mediumPages[0].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
  83 AMMU.mediumPages[0].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
  84
  85 /* config medium page[1] to map 1MB VA 0x01e00000 to 0x01eFFFFF */
  86 /* IVA-HD (accelerator memories, NC region) */
  87 AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
  88 AMMU.mediumPages[1].logicalAddress = 0x01e00000;
  89 AMMU.mediumPages[1].size = AMMU.Medium_1M;
  90 AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  91 AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
  92 AMMU.mediumPages[1].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
  93 AMMU.mediumPages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
  94 AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
  95 AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
  96 AMMU.mediumPages[1].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
  97 AMMU.mediumPages[1].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
  98
  99 /* config medium page[2] to map 128kB VA 0x10800000 to 0x1081FFFF */
 100 /* SL2->L1 */
 101 AMMU.mediumPages[2].pageEnabled = AMMU.Enable_YES;
 102 AMMU.mediumPages[2].logicalAddress = 0x10800000;
 103 AMMU.mediumPages[2].size = AMMU.Medium_128K;
 104 AMMU.mediumPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 105 AMMU.mediumPages[2].L1_posted = AMMU.PostedPolicy_POSTED;
 106 AMMU.mediumPages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 107 AMMU.mediumPages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 108 AMMU.mediumPages[2].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 109 AMMU.mediumPages[2].L2_posted = AMMU.PostedPolicy_POSTED;
 110 AMMU.mediumPages[2].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 111 AMMU.mediumPages[2].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 112
 113 /* config medium page[3] to map 128kB VA 0x10820000 to 0x1083FFFF  */
 114 /* SL2->L2 */
 115 AMMU.mediumPages[3].pageEnabled = AMMU.Enable_YES;
 116 AMMU.mediumPages[3].logicalAddress = 0x10820000;
 117 AMMU.mediumPages[3].size = AMMU.Medium_128K;
 118 AMMU.mediumPages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 119 AMMU.mediumPages[3].L1_posted = AMMU.PostedPolicy_POSTED;
 120 AMMU.mediumPages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 121 AMMU.mediumPages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 122 AMMU.mediumPages[3].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 123 AMMU.mediumPages[3].L2_posted = AMMU.PostedPolicy_POSTED;
 124 AMMU.mediumPages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 125 AMMU.mediumPages[3].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 126
 127 /* config medium page[4] to map 1MB VA 0x10900000 to 0x109FFFFF */
 128 /* SL2 Locked Region */
 129 AMMU.mediumPages[4].pageEnabled = AMMU.Enable_YES;
 130 AMMU.mediumPages[4].logicalAddress = 0x10900000;
 131 AMMU.mediumPages[4].size = AMMU.Medium_1M;
 132 AMMU.mediumPages[4].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 133 AMMU.mediumPages[4].L1_posted = AMMU.PostedPolicy_POSTED;
 134 AMMU.mediumPages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 135 AMMU.mediumPages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 136 AMMU.mediumPages[4].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 137 AMMU.mediumPages[4].L2_posted = AMMU.PostedPolicy_POSTED;
 138 AMMU.mediumPages[4].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 139 AMMU.mediumPages[4].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 140
 141 /* config medium page[5] to map 1MB VA 0x10d00000 to 0x10dFFFFF */
 142 /* ABE */
 143 AMMU.mediumPages[5].pageEnabled = AMMU.Enable_YES;
 144 AMMU.mediumPages[5].logicalAddress = 0x10d00000;
 145 AMMU.mediumPages[5].size = AMMU.Medium_1M;
 146 AMMU.mediumPages[5].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 147 AMMU.mediumPages[5].L1_posted = AMMU.PostedPolicy_POSTED;
 148 AMMU.mediumPages[5].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 149 AMMU.mediumPages[5].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 150 AMMU.mediumPages[5].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 151 AMMU.mediumPages[5].L2_posted = AMMU.PostedPolicy_POSTED;
 152 AMMU.mediumPages[5].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 153 AMMU.mediumPages[5].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
 154
 155 /* config medium page[6] to map 1MB VA 0x10e00000 to 0x10eFFFFF */
 156 /* ABE Locked Region */
 157 AMMU.mediumPages[6].pageEnabled = AMMU.Enable_YES;
 158 AMMU.mediumPages[6].logicalAddress = 0x10e00000;
 159 AMMU.mediumPages[6].size = AMMU.Medium_1M;
 160 AMMU.mediumPages[6].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 161 AMMU.mediumPages[6].L1_posted = AMMU.PostedPolicy_NON_POSTED;
 162 AMMU.mediumPages[6].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
 163 AMMU.mediumPages[6].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 164 AMMU.mediumPages[6].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 165 AMMU.mediumPages[6].L2_posted = AMMU.PostedPolicy_NON_POSTED;
 166 AMMU.mediumPages[6].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
 167 AMMU.mediumPages[6].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 168
 169 /*********************** Large Pages *************************/
 170 /* Instruction Code: Large page  (512M); cacheable, posted */
 171 /* config large page[0] to map 512MB VA 0x20000000 to L3 0x3FFFFFFF */
 172 AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
 173 AMMU.largePages[0].logicalAddress = 0x20000000;
 174 AMMU.largePages[0].size = AMMU.Large_512M;
 175 AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 176 AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED;
 177 AMMU.largePages[0].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 178 AMMU.largePages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 179 AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 180 AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_POSTED;
 181 AMMU.largePages[0].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 182 AMMU.largePages[0].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 183
 184 /* Peripheral regions: Large Page (512M); non-cacheable, posted */
 185 /* config large page[1] to map 512MB VA 0x40000000 to L3 0x5FFFFFFF */
 186 AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
 187 AMMU.largePages[1].logicalAddress = 0x40000000;
 188 AMMU.largePages[1].size = AMMU.Large_512M;
 189 AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 190 AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
 191 AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 192 AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 193 AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 194 AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_POSTED;
 195 AMMU.largePages[1].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 196 AMMU.largePages[1].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 197
 198 /* TILER region: Large Page (512M); cacheable, posted */
 199 /* config large page[2] to map 512MB VA 0x60000000 to L3 0x7FFFFFFF */
 200 AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
 201 AMMU.largePages[2].logicalAddress = 0x60000000;
 202 AMMU.largePages[2].size = AMMU.Large_512M;
 203 AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 204 AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
 205 AMMU.largePages[2].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 206 AMMU.largePages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 207 AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 208 AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_POSTED;
 209 AMMU.largePages[2].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 210 AMMU.largePages[2].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 211
 212 /* Private and Heap Data regions: Large page (512M); cacheable, posted */
 213 /* config large page[2] to map 512MB VA 0x80000000 to L3 0x9FFFFFFF */
 214 AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
 215 AMMU.largePages[3].logicalAddress = 0x80000000;
 216 AMMU.largePages[3].size = AMMU.Large_512M;
 217 AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 218 AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
 219 AMMU.largePages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 220 AMMU.largePages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 221 AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
 222 AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_POSTED;
 223 AMMU.largePages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 224 AMMU.largePages[3].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 225
 226 /* IPC region: Large Page (512M); non-cacheable, posted */
 227 /* config large page[3] to map 512MB VA 0xA0000000 to L3 0xBFFFFFFF */
 228 AMMU.largePages[4].pageEnabled = AMMU.Enable_YES;
 229 AMMU.largePages[4].logicalAddress = 0xA0000000;
 230 AMMU.largePages[4].size = AMMU.Large_512M;
 231 AMMU.largePages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 232 AMMU.largePages[4].L1_posted = AMMU.PostedPolicy_POSTED;
 233 AMMU.largePages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
 234 AMMU.largePages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
 235 AMMU.largePages[4].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 236 AMMU.largePages[4].L2_posted = AMMU.PostedPolicy_POSTED;
 237 AMMU.largePages[4].L2_allocate = AMMU.AllocatePolicy_ALLOCATE;
 238 AMMU.largePages[4].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;