1 /*
2 * Copyright (c) 2012-2013, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== rsc_table_omap5_dsp.h ========
35 *
36 * Define the resource table entries for all DSP cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_DSP_H_
43 #define _RSC_TABLE_DSP_H_
45 #include <xdc/std.h>
46 #include "rsc_types.h"
47 #include <ti/gates/hwspinlock/HwSpinlock.h>
49 /* DSP Memory Map */
50 #define L4_44XX_BASE 0x4A000000
52 #define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
53 #define DSP_PERIPHERAL_L4CFG 0x4A000000
55 #define L4_PERIPHERAL_L4PER 0x48000000
56 #define DSP_PERIPHERAL_L4PER 0x48000000
58 #define L4_PERIPHERAL_L4EMU 0x54000000
59 #define DSP_PERIPHERAL_L4EMU 0x54000000
61 #define L3_PERIPHERAL_DMM 0x4E000000
62 #define DSP_PERIPHERAL_DMM 0x4E000000
64 #define L3_PERIPHERAL_ISS 0x52000000
65 #define DSP_PERIPHERAL_ISS 0x52000000
67 #define L3_TILER_MODE_0_1 0x60000000
68 #define DSP_TILER_MODE_0_1 0x60000000
70 #define L3_TILER_MODE_2 0x70000000
71 #define DSP_TILER_MODE_2 0x70000000
73 #define L3_TILER_MODE_3 0x78000000
74 #define DSP_TILER_MODE_3 0x78000000
76 #define DSP_MEM_TEXT 0x20000000
77 /* Co-locate alongside TILER region for easier flushing */
78 #define DSP_MEM_IOBUFS 0x80000000
79 #define DSP_MEM_DATA 0x90000000
80 #define DSP_MEM_HEAP 0x90100000
82 #define DSP_MEM_IPC_DATA 0x9F000000
83 #define DSP_MEM_IPC_VRING 0xA0000000
84 #define DSP_MEM_RPMSG_VRING0 0xA0000000
85 #define DSP_MEM_RPMSG_VRING1 0xA0004000
86 #define DSP_MEM_VRING_BUFS0 0xA0040000
87 #define DSP_MEM_VRING_BUFS1 0xA0080000
89 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
90 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
91 #define DSP_MEM_TEXT_SIZE SZ_1M
92 #define DSP_MEM_DATA_SIZE SZ_1M
93 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
94 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
96 /*
97 * Assign fixed RAM addresses to facilitate a fixed MMU table.
98 */
99 /* This address is derived from current IPU & ION carveouts */
100 #ifdef OMAP5
101 #define PHYS_MEM_IPC_VRING 0x95000000
102 #else
103 #define PHYS_MEM_IPC_VRING 0x98800000
104 #endif
106 /* Need to be identical to that of Ducati */
107 #define PHYS_MEM_IOBUFS 0xBA300000
109 /*
110 * Sizes of the virtqueues (expressed in number of buffers supported,
111 * and must be power of 2)
112 */
113 #define DSP_RPMSG_VQ0_SIZE 256
114 #define DSP_RPMSG_VQ1_SIZE 256
116 /* flip up bits whose indices represent features we support */
117 #define RPMSG_DSP_C0_FEATURES 1
119 struct resource_table {
120 UInt32 version;
121 UInt32 num;
122 UInt32 reserved[2];
123 UInt32 offset[17]; /* Should match 'num' in actual definition */
125 /* rpmsg vdev entry */
126 struct fw_rsc_vdev rpmsg_vdev;
127 struct fw_rsc_vdev_vring rpmsg_vring0;
128 struct fw_rsc_vdev_vring rpmsg_vring1;
130 /* text carveout entry */
131 struct fw_rsc_carveout text_cout;
133 /* data carveout entry */
134 struct fw_rsc_carveout data_cout;
136 /* heap carveout entry */
137 struct fw_rsc_carveout heap_cout;
139 /* ipcdata carveout entry */
140 struct fw_rsc_carveout ipcdata_cout;
142 /* trace entry */
143 struct fw_rsc_trace trace;
145 /* devmem entry */
146 struct fw_rsc_devmem devmem0;
148 /* devmem entry */
149 struct fw_rsc_devmem devmem1;
151 /* devmem entry */
152 struct fw_rsc_devmem devmem2;
154 /* devmem entry */
155 struct fw_rsc_devmem devmem3;
157 /* devmem entry */
158 struct fw_rsc_devmem devmem4;
160 /* devmem entry */
161 struct fw_rsc_devmem devmem5;
163 /* devmem entry */
164 struct fw_rsc_devmem devmem6;
166 /* devmem entry */
167 struct fw_rsc_devmem devmem7;
169 /* devmem entry */
170 struct fw_rsc_devmem devmem8;
172 /* devmem entry */
173 struct fw_rsc_devmem devmem9;
175 /* hwspinlock custom entry */
176 struct fw_rsc_custom hwspin;
177 };
179 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
180 #define HWSPINKLOCKSTATEADDR (UInt32)&ti_gates_HwSpinlock_sharedState
181 #define HWSPINKLOCKNUMADDR (UInt32)&ti_gates_HwSpinlock_numLocks
183 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
184 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
186 struct resource_table ti_ipc_remoteproc_ResourceTable = {
187 1, /* we're the first version that implements this */
188 17, /* number of entries in the table */
189 0, 0, /* reserved, must be zero */
190 /* offsets to entries */
191 {
192 offsetof(struct resource_table, rpmsg_vdev),
193 offsetof(struct resource_table, text_cout),
194 offsetof(struct resource_table, data_cout),
195 offsetof(struct resource_table, heap_cout),
196 offsetof(struct resource_table, ipcdata_cout),
197 offsetof(struct resource_table, trace),
198 offsetof(struct resource_table, devmem0),
199 offsetof(struct resource_table, devmem1),
200 offsetof(struct resource_table, devmem2),
201 offsetof(struct resource_table, devmem3),
202 offsetof(struct resource_table, devmem4),
203 offsetof(struct resource_table, devmem5),
204 offsetof(struct resource_table, devmem6),
205 offsetof(struct resource_table, devmem7),
206 offsetof(struct resource_table, devmem8),
207 offsetof(struct resource_table, devmem9),
208 offsetof(struct resource_table, hwspin),
209 },
211 /* rpmsg vdev entry */
212 {
213 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
214 RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
215 /* no config data */
216 },
217 /* the two vrings */
218 { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
219 { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
221 {
222 TYPE_CARVEOUT,
223 DSP_MEM_TEXT, 0,
224 DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
225 },
227 {
228 TYPE_CARVEOUT,
229 DSP_MEM_DATA, 0,
230 DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
231 },
233 {
234 TYPE_CARVEOUT,
235 DSP_MEM_HEAP, 0,
236 DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
237 },
239 {
240 TYPE_CARVEOUT,
241 DSP_MEM_IPC_DATA, 0,
242 DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
243 },
245 {
246 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
247 },
249 {
250 TYPE_DEVMEM,
251 DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
252 DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
253 },
255 {
256 TYPE_DEVMEM,
257 DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
258 DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
259 },
261 {
262 TYPE_DEVMEM,
263 DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
264 SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
265 },
267 {
268 TYPE_DEVMEM,
269 DSP_TILER_MODE_2, L3_TILER_MODE_2,
270 SZ_128M, 0, 0, "DSP_TILER_MODE_2",
271 },
273 {
274 TYPE_DEVMEM,
275 DSP_TILER_MODE_3, L3_TILER_MODE_3,
276 SZ_128M, 0, 0, "DSP_TILER_MODE_3",
277 },
279 {
280 TYPE_DEVMEM,
281 DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
282 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
283 },
285 {
286 TYPE_DEVMEM,
287 DSP_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
288 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4PER",
289 },
291 {
292 TYPE_DEVMEM,
293 DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
294 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
295 },
297 {
298 TYPE_DEVMEM,
299 DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
300 SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
301 },
303 {
304 TYPE_DEVMEM,
305 DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
306 SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
307 },
309 {
310 TYPE_CUSTOM, TYPE_HWSPIN,
311 sizeof(struct fw_rsc_custom_hwspin),
312 { HWSPINKLOCKNUMADDR, HWSPINKLOCKSTATEADDR, "hwspin"},
313 },
314 };
316 #endif /* _RSC_TABLE_DSP_H_ */