1 /*
2 * Copyright (c) 2012-2013, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== rsc_table_vayu_dsp.h ========
35 *
36 * Define the resource table entries for all DSP cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_VAYU_DSP_H_
43 #define _RSC_TABLE_VAYU_DSP_H_
45 #include "rsc_types.h"
47 /* DSP Memory Map */
48 #define L4_DRA7XX_BASE 0x4A000000
50 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
51 #define DSP_PERIPHERAL_L4CFG 0x4A000000
53 #define L4_PERIPHERAL_L4PER1 0x48000000
54 #define DSP_PERIPHERAL_L4PER1 0x48000000
56 #define L4_PERIPHERAL_L4PER2 0x48400000
57 #define DSP_PERIPHERAL_L4PER2 0x48400000
59 #define L4_PERIPHERAL_L4PER3 0x48800000
60 #define DSP_PERIPHERAL_L4PER3 0x48800000
62 #define L4_PERIPHERAL_L4EMU 0x54000000
63 #define DSP_PERIPHERAL_L4EMU 0x54000000
65 #define L3_PERIPHERAL_DMM 0x4E000000
66 #define DSP_PERIPHERAL_DMM 0x4E000000
68 #define L3_PERIPHERAL_ISS 0x52000000
69 #define DSP_PERIPHERAL_ISS 0x52000000
71 #define L3_TILER_MODE_0_1 0x60000000
72 #define DSP_TILER_MODE_0_1 0x60000000
74 #define L3_TILER_MODE_2 0x70000000
75 #define DSP_TILER_MODE_2 0x70000000
77 #define L3_TILER_MODE_3 0x78000000
78 #define DSP_TILER_MODE_3 0x78000000
80 #define DSP_MEM_TEXT 0x95000000
81 /* Co-locate alongside TILER region for easier flushing */
82 #define DSP_MEM_IOBUFS 0x80000000
83 #define DSP_MEM_DATA 0x95100000
84 #define DSP_MEM_HEAP 0x95200000
86 #define DSP_MEM_IPC_DATA 0x9F000000
87 #define DSP_MEM_IPC_VRING 0xA0000000
88 #define DSP_MEM_RPMSG_VRING0 0xA0000000
89 #define DSP_MEM_RPMSG_VRING1 0xA0004000
90 #define DSP_MEM_VRING_BUFS0 0xA0040000
91 #define DSP_MEM_VRING_BUFS1 0xA0080000
93 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
94 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
95 #define DSP_MEM_TEXT_SIZE SZ_1M
96 #define DSP_MEM_DATA_SIZE SZ_1M
97 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
98 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
100 /*
101 * Assign fixed RAM addresses to facilitate a fixed MMU table.
102 */
103 /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
104 #if defined (VAYU_DSP_1)
105 #define PHYS_MEM_IPC_VRING 0x95000000
106 #elif defined (VAYU_DSP_2)
107 #define PHYS_MEM_IPC_VRING 0x94800000
108 #endif
110 /* Need to be identical to that of IPU */
111 #define PHYS_MEM_IOBUFS 0xBA300000
113 /*
114 * Sizes of the virtqueues (expressed in number of buffers supported,
115 * and must be power of 2)
116 */
117 #define DSP_RPMSG_VQ0_SIZE 256
118 #define DSP_RPMSG_VQ1_SIZE 256
120 /* flip up bits whose indices represent features we support */
121 #define RPMSG_DSP_C0_FEATURES 1
123 struct my_resource_table {
124 struct resource_table base;
126 UInt32 offset[18]; /* Should match 'num' in actual definition */
128 /* rpmsg vdev entry */
129 struct fw_rsc_vdev rpmsg_vdev;
130 struct fw_rsc_vdev_vring rpmsg_vring0;
131 struct fw_rsc_vdev_vring rpmsg_vring1;
133 /* text carveout entry */
134 struct fw_rsc_carveout text_cout;
136 /* data carveout entry */
137 struct fw_rsc_carveout data_cout;
139 /* heap carveout entry */
140 struct fw_rsc_carveout heap_cout;
142 /* ipcdata carveout entry */
143 struct fw_rsc_carveout ipcdata_cout;
145 /* trace entry */
146 struct fw_rsc_trace trace;
148 /* devmem entry */
149 struct fw_rsc_devmem devmem0;
151 /* devmem entry */
152 struct fw_rsc_devmem devmem1;
154 /* devmem entry */
155 struct fw_rsc_devmem devmem2;
157 /* devmem entry */
158 struct fw_rsc_devmem devmem3;
160 /* devmem entry */
161 struct fw_rsc_devmem devmem4;
163 /* devmem entry */
164 struct fw_rsc_devmem devmem5;
166 /* devmem entry */
167 struct fw_rsc_devmem devmem6;
169 /* devmem entry */
170 struct fw_rsc_devmem devmem7;
172 /* devmem entry */
173 struct fw_rsc_devmem devmem8;
175 /* devmem entry */
176 struct fw_rsc_devmem devmem9;
178 /* devmem entry */
179 struct fw_rsc_devmem devmem10;
181 /* devmem entry */
182 struct fw_rsc_devmem devmem11;
183 };
185 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
187 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
188 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
190 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
191 1, /* we're the first version that implements this */
192 18, /* number of entries in the table */
193 0, 0, /* reserved, must be zero */
194 /* offsets to entries */
195 {
196 offsetof(struct my_resource_table, rpmsg_vdev),
197 offsetof(struct my_resource_table, text_cout),
198 offsetof(struct my_resource_table, data_cout),
199 offsetof(struct my_resource_table, heap_cout),
200 offsetof(struct my_resource_table, ipcdata_cout),
201 offsetof(struct my_resource_table, trace),
202 offsetof(struct my_resource_table, devmem0),
203 offsetof(struct my_resource_table, devmem1),
204 offsetof(struct my_resource_table, devmem2),
205 offsetof(struct my_resource_table, devmem3),
206 offsetof(struct my_resource_table, devmem4),
207 offsetof(struct my_resource_table, devmem5),
208 offsetof(struct my_resource_table, devmem6),
209 offsetof(struct my_resource_table, devmem7),
210 offsetof(struct my_resource_table, devmem8),
211 offsetof(struct my_resource_table, devmem9),
212 offsetof(struct my_resource_table, devmem10),
213 offsetof(struct my_resource_table, devmem11),
214 },
216 /* rpmsg vdev entry */
217 {
218 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
219 RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
220 /* no config data */
221 },
222 /* the two vrings */
223 { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
224 { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
226 {
227 TYPE_CARVEOUT,
228 DSP_MEM_TEXT, 0,
229 DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
230 },
232 {
233 TYPE_CARVEOUT,
234 DSP_MEM_DATA, 0,
235 DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
236 },
238 {
239 TYPE_CARVEOUT,
240 DSP_MEM_HEAP, 0,
241 DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
242 },
244 {
245 TYPE_CARVEOUT,
246 DSP_MEM_IPC_DATA, 0,
247 DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
248 },
250 {
251 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
252 },
254 {
255 TYPE_DEVMEM,
256 DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
257 DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
258 },
260 {
261 TYPE_DEVMEM,
262 DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
263 DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
264 },
266 {
267 TYPE_DEVMEM,
268 DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
269 SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
270 },
272 {
273 TYPE_DEVMEM,
274 DSP_TILER_MODE_2, L3_TILER_MODE_2,
275 SZ_128M, 0, 0, "DSP_TILER_MODE_2",
276 },
278 {
279 TYPE_DEVMEM,
280 DSP_TILER_MODE_3, L3_TILER_MODE_3,
281 SZ_128M, 0, 0, "DSP_TILER_MODE_3",
282 },
284 {
285 TYPE_DEVMEM,
286 DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
287 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
288 },
290 {
291 TYPE_DEVMEM,
292 DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
293 SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
294 },
296 {
297 TYPE_DEVMEM,
298 DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
299 SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
300 },
302 {
303 TYPE_DEVMEM,
304 DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
305 SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
306 },
308 {
309 TYPE_DEVMEM,
310 DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
311 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
312 },
314 {
315 TYPE_DEVMEM,
316 DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
317 SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
318 },
320 {
321 TYPE_DEVMEM,
322 DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
323 SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
324 },
325 };
327 #endif /* _RSC_TABLE_VAYU_DSP_H_ */