1 /*
2 * Copyright (c) 2012-2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== rsc_table_vayu_dsp.h ========
35 *
36 * Define the resource table entries for all DSP cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_VAYU_DSP_H_
43 #define _RSC_TABLE_VAYU_DSP_H_
45 #include "rsc_types.h"
47 /* DSP Memory Map */
48 #define L4_DRA7XX_BASE 0x4A000000
50 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
51 #define DSP_PERIPHERAL_L4CFG 0x4A000000
53 #define L4_PERIPHERAL_L4PER1 0x48000000
54 #define DSP_PERIPHERAL_L4PER1 0x48000000
56 #define L4_PERIPHERAL_L4PER2 0x48400000
57 #define DSP_PERIPHERAL_L4PER2 0x48400000
59 #define L4_PERIPHERAL_L4PER3 0x48800000
60 #define DSP_PERIPHERAL_L4PER3 0x48800000
62 #define L4_PERIPHERAL_L4EMU 0x54000000
63 #define DSP_PERIPHERAL_L4EMU 0x54000000
65 #define L3_PERIPHERAL_DMM 0x4E000000
66 #define DSP_PERIPHERAL_DMM 0x4E000000
68 #define L3_TILER_MODE_0_1 0x60000000
69 #define DSP_TILER_MODE_0_1 0x60000000
71 #define L3_TILER_MODE_2 0x70000000
72 #define DSP_TILER_MODE_2 0x70000000
74 #define L3_TILER_MODE_3 0x78000000
75 #define DSP_TILER_MODE_3 0x78000000
77 #define DSP_MEM_TEXT 0x95000000
78 /* Co-locate alongside TILER region for easier flushing */
79 #define DSP_MEM_IOBUFS 0x80000000
80 #define DSP_MEM_DATA 0x95100000
81 #define DSP_MEM_HEAP 0x95200000
83 #define DSP_MEM_IPC_DATA 0x9F000000
84 #define DSP_MEM_IPC_VRING 0xA0000000
85 #define DSP_MEM_RPMSG_VRING0 0xA0000000
86 #define DSP_MEM_RPMSG_VRING1 0xA0004000
87 #define DSP_MEM_VRING_BUFS0 0xA0040000
88 #define DSP_MEM_VRING_BUFS1 0xA0080000
90 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
91 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
92 #define DSP_MEM_TEXT_SIZE SZ_1M
93 #define DSP_MEM_DATA_SIZE SZ_1M
94 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
95 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
97 /*
98 * Assign fixed RAM addresses to facilitate a fixed MMU table.
99 */
100 /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
101 #if defined (VAYU_DSP_1)
102 #define PHYS_MEM_IPC_VRING 0x99000000
103 #elif defined (VAYU_DSP_2)
104 #define PHYS_MEM_IPC_VRING 0x9F000000
105 #endif
107 /* Need to be identical to that of IPU */
108 #define PHYS_MEM_IOBUFS 0xBA300000
110 /*
111 * Sizes of the virtqueues (expressed in number of buffers supported,
112 * and must be power of 2)
113 */
114 #define DSP_RPMSG_VQ0_SIZE 256
115 #define DSP_RPMSG_VQ1_SIZE 256
117 /* flip up bits whose indices represent features we support */
118 #define RPMSG_DSP_C0_FEATURES 1
120 struct my_resource_table {
121 struct resource_table base;
123 UInt32 offset[18]; /* Should match 'num' in actual definition */
125 /* rpmsg vdev entry */
126 struct fw_rsc_vdev rpmsg_vdev;
127 struct fw_rsc_vdev_vring rpmsg_vring0;
128 struct fw_rsc_vdev_vring rpmsg_vring1;
130 /* text carveout entry */
131 struct fw_rsc_carveout text_cout;
133 /* data carveout entry */
134 struct fw_rsc_carveout data_cout;
136 /* heap carveout entry */
137 struct fw_rsc_carveout heap_cout;
139 /* ipcdata carveout entry */
140 struct fw_rsc_carveout ipcdata_cout;
142 /* trace entry */
143 struct fw_rsc_trace trace;
145 /* devmem entry */
146 struct fw_rsc_devmem devmem0;
148 /* devmem entry */
149 struct fw_rsc_devmem devmem1;
151 /* devmem entry */
152 struct fw_rsc_devmem devmem2;
154 /* devmem entry */
155 struct fw_rsc_devmem devmem3;
157 /* devmem entry */
158 struct fw_rsc_devmem devmem4;
160 /* devmem entry */
161 struct fw_rsc_devmem devmem5;
163 /* devmem entry */
164 struct fw_rsc_devmem devmem6;
166 /* devmem entry */
167 struct fw_rsc_devmem devmem7;
169 /* devmem entry */
170 struct fw_rsc_devmem devmem8;
172 /* devmem entry */
173 struct fw_rsc_devmem devmem9;
175 /* devmem entry */
176 struct fw_rsc_devmem devmem10;
177 };
179 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
181 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
182 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
184 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
185 1, /* we're the first version that implements this */
186 17, /* number of entries in the table */
187 0, 0, /* reserved, must be zero */
188 /* offsets to entries */
189 {
190 offsetof(struct my_resource_table, rpmsg_vdev),
191 offsetof(struct my_resource_table, text_cout),
192 offsetof(struct my_resource_table, data_cout),
193 offsetof(struct my_resource_table, heap_cout),
194 offsetof(struct my_resource_table, ipcdata_cout),
195 offsetof(struct my_resource_table, trace),
196 offsetof(struct my_resource_table, devmem0),
197 offsetof(struct my_resource_table, devmem1),
198 offsetof(struct my_resource_table, devmem2),
199 offsetof(struct my_resource_table, devmem3),
200 offsetof(struct my_resource_table, devmem4),
201 offsetof(struct my_resource_table, devmem5),
202 offsetof(struct my_resource_table, devmem6),
203 offsetof(struct my_resource_table, devmem7),
204 offsetof(struct my_resource_table, devmem8),
205 offsetof(struct my_resource_table, devmem9),
206 offsetof(struct my_resource_table, devmem10),
207 },
209 /* rpmsg vdev entry */
210 {
211 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
212 RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
213 /* no config data */
214 },
215 /* the two vrings */
216 { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
217 { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
219 {
220 TYPE_CARVEOUT,
221 DSP_MEM_TEXT, 0,
222 DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
223 },
225 {
226 TYPE_CARVEOUT,
227 DSP_MEM_DATA, 0,
228 DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
229 },
231 {
232 TYPE_CARVEOUT,
233 DSP_MEM_HEAP, 0,
234 DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
235 },
237 {
238 TYPE_CARVEOUT,
239 DSP_MEM_IPC_DATA, 0,
240 DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
241 },
243 {
244 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
245 },
247 {
248 TYPE_DEVMEM,
249 DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
250 DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
251 },
253 {
254 TYPE_DEVMEM,
255 DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
256 DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
257 },
259 {
260 TYPE_DEVMEM,
261 DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
262 SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
263 },
265 {
266 TYPE_DEVMEM,
267 DSP_TILER_MODE_2, L3_TILER_MODE_2,
268 SZ_128M, 0, 0, "DSP_TILER_MODE_2",
269 },
271 {
272 TYPE_DEVMEM,
273 DSP_TILER_MODE_3, L3_TILER_MODE_3,
274 SZ_128M, 0, 0, "DSP_TILER_MODE_3",
275 },
277 {
278 TYPE_DEVMEM,
279 DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
280 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
281 },
283 {
284 TYPE_DEVMEM,
285 DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
286 SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
287 },
289 {
290 TYPE_DEVMEM,
291 DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
292 SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
293 },
295 {
296 TYPE_DEVMEM,
297 DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
298 SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
299 },
301 {
302 TYPE_DEVMEM,
303 DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
304 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
305 },
307 {
308 TYPE_DEVMEM,
309 DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
310 SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
311 },
312 };
314 #endif /* _RSC_TABLE_VAYU_DSP_H_ */