1 /*
2 * Copyright (c) 2012-2013, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== rsc_table_omap5_ipu.h ========
35 *
36 * Define the resource table entries for all IPU cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_IPU_H_
43 #define _RSC_TABLE_IPU_H_
45 #include "rsc_types.h"
47 /* IPU Memory Map */
48 #define L4_44XX_BASE 0x4a000000
50 #define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
51 #define IPU_PERIPHERAL_L4CFG 0x6A000000
53 #define L4_PERIPHERAL_L4PER 0x48000000
54 #define IPU_PERIPHERAL_L4PER 0x68000000
56 #define L4_PERIPHERAL_L4EMU 0x54000000
57 #define IPU_PERIPHERAL_L4EMU 0x74000000
59 #define L3_PERIPHERAL_DMM 0x4E000000
60 #define IPU_PERIPHERAL_DMM 0x6E000000
62 #define L3_IVAHD_CONFIG 0x5A000000
63 #define IPU_IVAHD_CONFIG 0x7A000000
65 #define L3_IVAHD_SL2 0x5B000000
66 #define IPU_IVAHD_SL2 0x7B000000
68 #define L3_TILER_MODE_0_1 0x60000000
69 #define IPU_TILER_MODE_0_1 0xA0000000
71 #define L3_TILER_MODE_2 0x70000000
72 #define IPU_TILER_MODE_2 0xB0000000
74 #define L3_TILER_MODE_3 0x78000000
75 #define IPU_TILER_MODE_3 0xB8000000
77 #define IPU_MEM_TEXT 0x0
78 #define IPU_MEM_DATA 0x80000000
80 #ifdef OMAP5
81 #define IPU_MEM_IOBUFS 0x90000000
82 #else
83 #define IPU_MEM_IOBUFS 0x88000000
84 #endif
86 #define IPU_MEM_IPC_DATA 0x9F000000
87 #define IPU_MEM_IPC_VRING 0x60000000
88 #define IPU_MEM_RPMSG_VRING0 0x60000000
89 #define IPU_MEM_RPMSG_VRING1 0x60004000
90 #define IPU_MEM_VRING_BUFS0 0x60040000
91 #define IPU_MEM_VRING_BUFS1 0x60080000
93 #define IPU_MEM_IPC_VRING_SIZE SZ_1M
94 #define IPU_MEM_IPC_DATA_SIZE SZ_1M
95 #define IPU_MEM_TEXT_SIZE (SZ_1M * 6)
96 #ifdef OMAP5
97 #define IPU_MEM_DATA_SIZE (SZ_1M * 156)
98 #else
99 #define IPU_MEM_DATA_SIZE (SZ_1M * 100)
100 #endif
101 #define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90)
103 /*
104 * Assign fixed RAM addresses to facilitate a fixed MMU table.
105 * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
106 */
107 #ifdef OMAP5
108 #define PHYS_MEM_IPC_VRING 0x95800000
109 #else
110 #define PHYS_MEM_IPC_VRING 0x99000000
111 #endif
113 #define PHYS_MEM_IOBUFS 0xBA300000
115 /*
116 * Sizes of the virtqueues (expressed in number of buffers supported,
117 * and must be power of 2)
118 */
119 #define IPU_RPMSG_VQ0_SIZE 256
120 #define IPU_RPMSG_VQ1_SIZE 256
122 /* flip up bits whose indices represent features we support */
123 #define RPMSG_IPU_C0_FEATURES 1
125 struct my_resource_table {
126 struct resource_table base;
128 UInt32 offset[16]; /* Should match 'num' in actual definition */
130 /* rpmsg vdev entry */
131 struct fw_rsc_vdev rpmsg_vdev;
132 struct fw_rsc_vdev_vring rpmsg_vring0;
133 struct fw_rsc_vdev_vring rpmsg_vring1;
135 /* text carveout entry */
136 struct fw_rsc_carveout text_cout;
138 /* data carveout entry */
139 struct fw_rsc_carveout data_cout;
141 /* ipcdata carveout entry */
142 struct fw_rsc_carveout ipcdata_cout;
144 /* trace entry */
145 struct fw_rsc_trace trace;
147 /* devmem entry */
148 struct fw_rsc_devmem devmem0;
150 /* devmem entry */
151 struct fw_rsc_devmem devmem1;
153 /* devmem entry */
154 struct fw_rsc_devmem devmem2;
156 /* devmem entry */
157 struct fw_rsc_devmem devmem3;
159 /* devmem entry */
160 struct fw_rsc_devmem devmem4;
162 /* devmem entry */
163 struct fw_rsc_devmem devmem5;
165 /* devmem entry */
166 struct fw_rsc_devmem devmem6;
168 /* devmem entry */
169 struct fw_rsc_devmem devmem7;
171 /* devmem entry */
172 struct fw_rsc_devmem devmem8;
174 /* devmem entry */
175 struct fw_rsc_devmem devmem9;
177 /* devmem entry */
178 struct fw_rsc_devmem devmem10;
179 };
181 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
183 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
184 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
186 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
187 1, /* we're the first version that implements this */
188 16, /* number of entries in the table */
189 0, 0, /* reserved, must be zero */
190 /* offsets to entries */
191 {
192 offsetof(struct my_resource_table, rpmsg_vdev),
193 offsetof(struct my_resource_table, text_cout),
194 offsetof(struct my_resource_table, data_cout),
195 offsetof(struct my_resource_table, ipcdata_cout),
196 offsetof(struct my_resource_table, trace),
197 offsetof(struct my_resource_table, devmem0),
198 offsetof(struct my_resource_table, devmem1),
199 offsetof(struct my_resource_table, devmem2),
200 offsetof(struct my_resource_table, devmem3),
201 offsetof(struct my_resource_table, devmem4),
202 offsetof(struct my_resource_table, devmem5),
203 offsetof(struct my_resource_table, devmem6),
204 offsetof(struct my_resource_table, devmem7),
205 offsetof(struct my_resource_table, devmem8),
206 offsetof(struct my_resource_table, devmem9),
207 offsetof(struct my_resource_table, devmem10),
208 },
210 /* rpmsg vdev entry */
211 {
212 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
213 RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
214 /* no config data */
215 },
216 /* the two vrings */
217 { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
218 { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
220 {
221 TYPE_CARVEOUT,
222 IPU_MEM_TEXT, 0,
223 IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
224 },
226 {
227 TYPE_CARVEOUT,
228 IPU_MEM_DATA, 0,
229 IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
230 },
232 {
233 TYPE_CARVEOUT,
234 IPU_MEM_IPC_DATA, 0,
235 IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
236 },
238 {
239 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
240 },
242 {
243 TYPE_DEVMEM,
244 IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
245 IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
246 },
248 {
249 TYPE_DEVMEM,
250 IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS,
251 IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS",
252 },
254 {
255 TYPE_DEVMEM,
256 IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1,
257 SZ_256M, 0, 0, "IPU_TILER_MODE_0_1",
258 },
260 {
261 TYPE_DEVMEM,
262 IPU_TILER_MODE_2, L3_TILER_MODE_2,
263 SZ_128M, 0, 0, "IPU_TILER_MODE_2",
264 },
266 {
267 TYPE_DEVMEM,
268 IPU_TILER_MODE_3, L3_TILER_MODE_3,
269 SZ_128M, 0, 0, "IPU_TILER_MODE_3",
270 },
272 {
273 TYPE_DEVMEM,
274 IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
275 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG",
276 },
278 {
279 TYPE_DEVMEM,
280 IPU_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
281 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4PER",
282 },
284 {
285 TYPE_DEVMEM,
286 IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
287 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU",
288 },
290 {
291 TYPE_DEVMEM,
292 IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG,
293 SZ_16M, 0, 0, "IPU_IVAHD_CONFIG",
294 },
296 {
297 TYPE_DEVMEM,
298 IPU_IVAHD_SL2, L3_IVAHD_SL2,
299 SZ_16M, 0, 0, "IPU_IVAHD_SL2",
300 },
302 {
303 TYPE_DEVMEM,
304 IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
305 SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM",
306 },
307 };
309 #endif /* _RSC_TABLE_IPU_H_ */