1 /*
2 * Copyright (c) 2013, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== gatempapp_rsc_table_vayu_dsp.h ========
35 *
36 * Define the resource table entries for all DSP cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_DSP_H_
43 #define _RSC_TABLE_DSP_H_
45 #include <ti/ipc/remoteproc/rsc_types.h>
47 /* DSP Memory Map */
48 #define L4_44XX_BASE 0x4A000000
50 #define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
51 #define DSP_PERIPHERAL_L4CFG 0x4A000000
53 #define L4_PERIPHERAL_L4PER 0x48000000
54 #define DSP_PERIPHERAL_L4PER 0x48000000
56 #define L4_PERIPHERAL_L4EMU 0x54000000
57 #define DSP_PERIPHERAL_L4EMU 0x54000000
59 #define L3_PERIPHERAL_DMM 0x4E000000
60 #define DSP_PERIPHERAL_DMM 0x4E000000
62 #define L3_PERIPHERAL_ISS 0x52000000
63 #define DSP_PERIPHERAL_ISS 0x52000000
65 #define L3_TILER_MODE_0_1 0x60000000
66 #define DSP_TILER_MODE_0_1 0x60000000
68 #define L3_TILER_MODE_2 0x70000000
69 #define DSP_TILER_MODE_2 0x70000000
71 #define L3_TILER_MODE_3 0x78000000
72 #define DSP_TILER_MODE_3 0x78000000
74 #define DSP_MEM_TEXT 0x95000000
75 /* Co-locate alongside TILER region for easier flushing */
76 #define DSP_MEM_IOBUFS 0x80000000
77 #define DSP_MEM_DATA 0x95100000
78 #define DSP_MEM_HEAP 0x95200000
80 //0x85900000
81 #define DSP_SR0_VIRT 0xBFC00000
82 #define DSP_SR0 0xBFC00000
84 #define DSP_MEM_IPC_DATA 0x9F000000
85 #define DSP_MEM_IPC_VRING 0xA0000000
86 #define DSP_MEM_RPMSG_VRING0 0xA0000000
87 #define DSP_MEM_RPMSG_VRING1 0xA0004000
88 #define DSP_MEM_VRING_BUFS0 0xA0040000
89 #define DSP_MEM_VRING_BUFS1 0xA0080000
91 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
92 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
93 #define DSP_MEM_TEXT_SIZE SZ_1M
94 #define DSP_MEM_DATA_SIZE SZ_1M
95 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
96 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 89)
97 #define DSP_SR0_SIZE (SZ_1M * 1)
99 /*
100 * Assign fixed RAM addresses to facilitate a fixed MMU table.
101 */
102 /* This address is derived from current IPU & ION carveouts */
103 #ifdef OMAP5
104 #define PHYS_MEM_IPC_VRING 0x95000000
105 #else
106 #define PHYS_MEM_IPC_VRING 0x98800000
107 #endif
109 /* Need to be identical to that of IPU */
110 #define PHYS_MEM_IOBUFS 0xBA300000
112 /*
113 * Sizes of the virtqueues (expressed in number of buffers supported,
114 * and must be power of 2)
115 */
116 #define DSP_RPMSG_VQ0_SIZE 256
117 #define DSP_RPMSG_VQ1_SIZE 256
119 /* flip up bits whose indices represent features we support */
120 #define RPMSG_DSP_C0_FEATURES 1
122 struct my_resource_table {
123 struct resource_table base;
125 UInt32 offset[17]; /* Should match 'num' in actual definition */
127 /* rpmsg vdev entry */
128 struct fw_rsc_vdev rpmsg_vdev;
129 struct fw_rsc_vdev_vring rpmsg_vring0;
130 struct fw_rsc_vdev_vring rpmsg_vring1;
132 /* text carveout entry */
133 struct fw_rsc_carveout text_cout;
135 /* data carveout entry */
136 struct fw_rsc_carveout data_cout;
138 /* heap carveout entry */
139 struct fw_rsc_carveout heap_cout;
141 /* ipcdata carveout entry */
142 struct fw_rsc_carveout ipcdata_cout;
144 /* trace entry */
145 struct fw_rsc_trace trace;
147 /* devmem entry */
148 struct fw_rsc_devmem devmem0;
150 /* devmem entry */
151 struct fw_rsc_devmem devmem1;
153 /* devmem entry */
154 struct fw_rsc_devmem devmem2;
156 /* devmem entry */
157 struct fw_rsc_devmem devmem3;
159 /* devmem entry */
160 struct fw_rsc_devmem devmem4;
162 /* devmem entry */
163 struct fw_rsc_devmem devmem5;
165 /* devmem entry */
166 struct fw_rsc_devmem devmem6;
168 /* devmem entry */
169 struct fw_rsc_devmem devmem7;
171 /* devmem entry */
172 struct fw_rsc_devmem devmem8;
174 /* devmem entry */
175 struct fw_rsc_devmem devmem9;
177 /* devmem entry */
178 struct fw_rsc_devmem devmem10;
180 };
182 extern char ti_trace_SysMin_Module_State_0_outbuf__A;
183 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
185 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
186 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
188 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
189 1, /* we're the first version that implements this */
190 17, /* number of entries in the table */
191 0, 0, /* reserved, must be zero */
192 /* offsets to entries */
193 {
194 offsetof(struct my_resource_table, rpmsg_vdev),
195 offsetof(struct my_resource_table, text_cout),
196 offsetof(struct my_resource_table, data_cout),
197 offsetof(struct my_resource_table, heap_cout),
198 offsetof(struct my_resource_table, ipcdata_cout),
199 offsetof(struct my_resource_table, trace),
200 offsetof(struct my_resource_table, devmem0),
201 offsetof(struct my_resource_table, devmem1),
202 offsetof(struct my_resource_table, devmem2),
203 offsetof(struct my_resource_table, devmem3),
204 offsetof(struct my_resource_table, devmem4),
205 offsetof(struct my_resource_table, devmem5),
206 offsetof(struct my_resource_table, devmem6),
207 offsetof(struct my_resource_table, devmem7),
208 offsetof(struct my_resource_table, devmem8),
209 offsetof(struct my_resource_table, devmem9),
210 offsetof(struct my_resource_table, devmem10),
211 },
213 /* rpmsg vdev entry */
214 {
215 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
216 RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
217 /* no config data */
218 },
219 /* the two vrings */
220 { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
221 { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
223 {
224 TYPE_CARVEOUT,
225 DSP_MEM_TEXT, 0,
226 DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
227 },
229 {
230 TYPE_CARVEOUT,
231 DSP_MEM_DATA, 0,
232 DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
233 },
235 {
236 TYPE_CARVEOUT,
237 DSP_MEM_HEAP, 0,
238 DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
239 },
241 {
242 TYPE_CARVEOUT,
243 DSP_MEM_IPC_DATA, 0,
244 DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
245 },
247 {
248 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
249 },
251 {
252 TYPE_DEVMEM,
253 DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
254 DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
255 },
257 {
258 TYPE_DEVMEM,
259 DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
260 DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
261 },
263 {
264 TYPE_DEVMEM,
265 DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
266 SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
267 },
269 {
270 TYPE_DEVMEM,
271 DSP_TILER_MODE_2, L3_TILER_MODE_2,
272 SZ_128M, 0, 0, "DSP_TILER_MODE_2",
273 },
275 {
276 TYPE_DEVMEM,
277 DSP_TILER_MODE_3, L3_TILER_MODE_3,
278 SZ_128M, 0, 0, "DSP_TILER_MODE_3",
279 },
281 {
282 TYPE_DEVMEM,
283 DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
284 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
285 },
287 {
288 TYPE_DEVMEM,
289 DSP_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
290 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4PER",
291 },
293 {
294 TYPE_DEVMEM,
295 DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
296 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
297 },
299 {
300 TYPE_DEVMEM,
301 DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
302 SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
303 },
305 {
306 TYPE_DEVMEM,
307 DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
308 SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
309 },
311 {
312 TYPE_DEVMEM,
313 DSP_SR0_VIRT, DSP_SR0,
314 DSP_SR0_SIZE, 0, 0, "DSP_SR0",
315 },
317 };
319 #endif /* _RSC_TABLE_DSP_H_ */