437077627622e94449930eaa27463dfed74e2095
1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== power_rsc_table_vayu_dsp.h ========
35 *
36 * Define the resource table entries for all DSP cores. This adds
37 * an entry on top of the default resource table for L2 internal memory,
38 * in order to accomodate for a silicon bug workaround.
39 *
40 */
42 #ifndef _POWER_RSC_TABLE_VAYU_DSP_H_
43 #define _POWER_RSC_TABLE_VAYU_DSP_H_
45 #include <ti/ipc/remoteproc/rsc_types.h>
47 /* DSP Memory Map */
48 #define L4_DRA7XX_BASE 0x4A000000
50 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
51 #define DSP_PERIPHERAL_L4CFG 0x4A000000
53 #define L4_PERIPHERAL_L4PER1 0x48000000
54 #define DSP_PERIPHERAL_L4PER1 0x48000000
56 #define L4_PERIPHERAL_L4PER2 0x48400000
57 #define DSP_PERIPHERAL_L4PER2 0x48400000
59 #define L4_PERIPHERAL_L4PER3 0x48800000
60 #define DSP_PERIPHERAL_L4PER3 0x48800000
62 #define L4_PERIPHERAL_L4EMU 0x54000000
63 #define DSP_PERIPHERAL_L4EMU 0x54000000
65 #define L3_PERIPHERAL_DMM 0x4E000000
66 #define DSP_PERIPHERAL_DMM 0x4E000000
68 #define L3_TILER_MODE_0_1 0x60000000
69 #define DSP_TILER_MODE_0_1 0x60000000
71 #define L3_TILER_MODE_2 0x70000000
72 #define DSP_TILER_MODE_2 0x70000000
74 #define L3_TILER_MODE_3 0x78000000
75 #define DSP_TILER_MODE_3 0x78000000
77 #define DSP_MEM_TEXT 0x95000000
78 /* Co-locate alongside TILER region for easier flushing */
79 #define DSP_MEM_IOBUFS 0x80000000
80 #define DSP_MEM_DATA 0x95100000
81 #define DSP_MEM_HEAP 0x95200000
82 #define DSP_INTMEM_L2 0x800000
83 #if defined (DSP_1)
84 #define PHYS_MEM_L2_RAM 0x40800000
85 #elif defined (DSP_2)
86 #define PHYS_MEM_L2_RAM 0x41000000
87 #endif
88 #define DSP_MEM_L2_RAM_SIZE 0x00040000
90 #define DSP_MEM_IPC_DATA 0x9F000000
91 #define DSP_MEM_IPC_VRING 0xA0000000
92 #define DSP_MEM_RPMSG_VRING0 0xA0000000
93 #define DSP_MEM_RPMSG_VRING1 0xA0004000
94 #define DSP_MEM_VRING_BUFS0 0xA0040000
95 #define DSP_MEM_VRING_BUFS1 0xA0080000
97 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
98 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
99 #define DSP_MEM_TEXT_SIZE SZ_1M
100 #define DSP_MEM_DATA_SIZE SZ_1M
101 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
102 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
104 /*
105 * Assign fixed RAM addresses to facilitate a fixed MMU table.
106 */
107 /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
108 #if defined (DSP_1)
109 #define PHYS_MEM_IPC_VRING 0x99000000
110 #elif defined (DSP_2)
111 #define PHYS_MEM_IPC_VRING 0x9F000000
112 #endif
114 /* Need to be identical to that of IPU */
115 #define PHYS_MEM_IOBUFS 0xBA300000
117 /*
118 * Sizes of the virtqueues (expressed in number of buffers supported,
119 * and must be power of 2)
120 */
121 #define DSP_RPMSG_VQ0_SIZE 256
122 #define DSP_RPMSG_VQ1_SIZE 256
124 /* flip up bits whose indices represent features we support */
125 #define RPMSG_DSP_C0_FEATURES 1
127 struct my_resource_table {
128 struct resource_table base;
130 UInt32 offset[18]; /* Should match 'num' in actual definition */
132 /* rpmsg vdev entry */
133 struct fw_rsc_vdev rpmsg_vdev;
134 struct fw_rsc_vdev_vring rpmsg_vring0;
135 struct fw_rsc_vdev_vring rpmsg_vring1;
137 /* text carveout entry */
138 struct fw_rsc_carveout text_cout;
140 /* data carveout entry */
141 struct fw_rsc_carveout data_cout;
143 /* heap carveout entry */
144 struct fw_rsc_carveout heap_cout;
146 /* ipcdata carveout entry */
147 struct fw_rsc_carveout ipcdata_cout;
149 /* trace entry */
150 struct fw_rsc_trace trace;
152 /* devmem entry */
153 struct fw_rsc_devmem devmem0;
155 /* devmem entry */
156 struct fw_rsc_devmem devmem1;
158 /* devmem entry */
159 struct fw_rsc_devmem devmem2;
161 /* devmem entry */
162 struct fw_rsc_devmem devmem3;
164 /* devmem entry */
165 struct fw_rsc_devmem devmem4;
167 /* devmem entry */
168 struct fw_rsc_devmem devmem5;
170 /* devmem entry */
171 struct fw_rsc_devmem devmem6;
173 /* devmem entry */
174 struct fw_rsc_devmem devmem7;
176 /* devmem entry */
177 struct fw_rsc_devmem devmem8;
179 /* devmem entry */
180 struct fw_rsc_devmem devmem9;
182 /* devmem entry */
183 struct fw_rsc_devmem devmem10;
185 /* L2 intmem entry */
186 struct fw_rsc_intmem l2_intmem;
187 };
189 extern char ti_trace_SysMin_Module_State_0_outbuf__A;
190 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
192 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
193 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
195 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
196 1, /* we're the first version that implements this */
197 18, /* number of entries in the table */
198 0, 0, /* reserved, must be zero */
199 /* offsets to entries */
200 {
201 offsetof(struct my_resource_table, rpmsg_vdev),
202 offsetof(struct my_resource_table, text_cout),
203 offsetof(struct my_resource_table, data_cout),
204 offsetof(struct my_resource_table, heap_cout),
205 offsetof(struct my_resource_table, ipcdata_cout),
206 offsetof(struct my_resource_table, trace),
207 offsetof(struct my_resource_table, devmem0),
208 offsetof(struct my_resource_table, devmem1),
209 offsetof(struct my_resource_table, devmem2),
210 offsetof(struct my_resource_table, devmem3),
211 offsetof(struct my_resource_table, devmem4),
212 offsetof(struct my_resource_table, devmem5),
213 offsetof(struct my_resource_table, devmem6),
214 offsetof(struct my_resource_table, devmem7),
215 offsetof(struct my_resource_table, devmem8),
216 offsetof(struct my_resource_table, devmem9),
217 offsetof(struct my_resource_table, devmem10),
218 offsetof(struct my_resource_table, l2_intmem),
219 },
221 /* rpmsg vdev entry */
222 {
223 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
224 RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
225 /* no config data */
226 },
227 /* the two vrings */
228 { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
229 { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
231 {
232 TYPE_CARVEOUT,
233 DSP_MEM_TEXT, 0,
234 DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
235 },
237 {
238 TYPE_CARVEOUT,
239 DSP_MEM_DATA, 0,
240 DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
241 },
243 {
244 TYPE_CARVEOUT,
245 DSP_MEM_HEAP, 0,
246 DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
247 },
249 {
250 TYPE_CARVEOUT,
251 DSP_MEM_IPC_DATA, 0,
252 DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
253 },
255 {
256 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
257 },
259 {
260 TYPE_DEVMEM,
261 DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
262 DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
263 },
265 {
266 TYPE_DEVMEM,
267 DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
268 DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
269 },
271 {
272 TYPE_DEVMEM,
273 DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
274 SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
275 },
277 {
278 TYPE_DEVMEM,
279 DSP_TILER_MODE_2, L3_TILER_MODE_2,
280 SZ_128M, 0, 0, "DSP_TILER_MODE_2",
281 },
283 {
284 TYPE_DEVMEM,
285 DSP_TILER_MODE_3, L3_TILER_MODE_3,
286 SZ_128M, 0, 0, "DSP_TILER_MODE_3",
287 },
289 {
290 TYPE_DEVMEM,
291 DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
292 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
293 },
295 {
296 TYPE_DEVMEM,
297 DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
298 SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
299 },
301 {
302 TYPE_DEVMEM,
303 DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
304 SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
305 },
307 {
308 TYPE_DEVMEM,
309 DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
310 SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
311 },
313 {
314 TYPE_DEVMEM,
315 DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
316 SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
317 },
319 {
320 TYPE_DEVMEM,
321 DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
322 SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
323 },
325 {
326 TYPE_INTMEM, 1,
327 DSP_INTMEM_L2, PHYS_MEM_L2_RAM,
328 DSP_MEM_L2_RAM_SIZE, 0, "DSP_MEM_L2_RAM",
329 },
330 };
332 #endif /* _POWER_RSC_TABLE_VAYU_DSP_H_ */