[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / common / vayu / vayudsp / VAYUDspHalReset.c
1 /*
2 * @file VAYUDspHalReset.c
3 *
4 * @brief Reset control module.
5 *
6 * This module is responsible for handling reset-related hardware-
7 * specific operations.
8 * The implementation is specific to VAYUDSP.
9 *
10 *
11 * ============================================================================
12 *
13 * Copyright (c) 2013-2015, Texas Instruments Incorporated
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
32 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
34 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
35 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
36 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
38 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
39 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 */
43 #include <ti/syslink/Std.h>
45 /* OSAL & Utils headers */
46 #include <ti/syslink/utils/Trace.h>
47 #include <Bitops.h>
49 /* Module level headers */
50 #include <_ProcDefs.h>
51 #include <Processor.h>
53 /* Hardware Abstraction Layer headers */
54 #include <VAYUDspHal.h>
55 #include <VAYUDspHalReset.h>
57 #include <hw/inout.h>
59 #if defined (__cplusplus)
60 extern "C" {
61 #endif
64 /* =============================================================================
65 * Macros and types
66 * =============================================================================
67 */
68 /* DSP PRCM Regs*/
69 #define CM_DSP_CLKSTCTRL 0x00
70 #define CM_DSP_STATICDEP 0x04
71 #define CM_DSP_DYNMICDEP 0x08
72 #define CM_DSP_DSP_CLKCTRL 0x20
74 #define PM_DSP_PWRSTCTRL 0x00
75 #define PM_DSP_PWRSTST 0x04
76 #define RM_DSP_RSTCTRL 0x10
77 #define RM_DSP_RSTST 0x14
79 #define DSP_SYS_MMU_CONFIG_OFFSET 0x18
81 /* =============================================================================
82 * APIs called by VAYUDSPPROC module
83 * =============================================================================
84 */
85 /*!
86 * @brief Function to control reset operations
87 *
88 * @param halObj Pointer to the HAL object
89 * @param cmd Reset control command
90 * @param arg Arguments specific to the reset control command
91 *
92 * @sa
93 */
94 Int
95 VAYUDSP_halResetCtrl(Ptr halObj, VAYUDspHal_ResetCmd cmd)
96 {
97 Int status = PROCESSOR_SUCCESS;
98 VAYUDSP_HalObject * halObject = NULL;
99 UInt32 cmBase;
100 UInt32 prmBase;
101 UInt32 mmuSysBase;
102 UInt32 addr;
103 UInt32 val;
104 Int32 counter = 10;
106 GT_2trace(curTrace, GT_ENTER, "VAYUDSP_halResetCTRL", halObj, cmd);
108 GT_assert(curTrace, (halObj != NULL));
109 GT_assert(curTrace, (cmd < VAYUDspHal_Reset_EndValue));
111 halObject = (VAYUDSP_HalObject *)halObj;
112 cmBase = halObject->cmBase;
113 prmBase = halObject->prmBase;
114 mmuSysBase = halObject->mmuSysBase;
116 switch (cmd) {
117 case Processor_ResetCtrlCmd_Reset:
118 {
119 /* assert GEM global and cpu resets */
120 addr = prmBase + RM_DSP_RSTCTRL;
121 SETBITREG32(addr, 0x0);
123 }
124 break;
126 case Processor_ResetCtrlCmd_MMU_Reset:
127 {
128 /* Assert MMU Reset */
129 addr = prmBase + RM_DSP_RSTCTRL;
130 SETBITREG32(addr, 0x1);
132 }
133 break;
135 case Processor_ResetCtrlCmd_MMU_Release:
136 {
137 /* clear status bit, write-1 to clear bit */
138 addr = prmBase + RM_DSP_RSTST;
139 val = INREG32(addr);
140 if (val != 0x0) {
141 Osal_printf("VAYUDSP_halResetCtrl: clearing DSP reset status!\n");
142 OUTREG32(addr, val);
143 while ((val = INREG32(addr)) != 0x0);
144 Osal_printf("VAYUDSP_halResetCtrl: DSP reset state reset!\n");
145 }
147 addr = prmBase + PM_DSP_PWRSTCTRL;
148 val = INREG32(addr);
149 val |= 0x7;
150 OUTREG32(addr, val);
151 addr = prmBase + PM_DSP_PWRSTST;
152 val = INREG32(addr);
153 /* Module is managed automatically by HW */
154 addr = cmBase + CM_DSP_DSP_CLKCTRL;
155 OUTREG32(addr, 0x01);
156 /* Enable the DSP clock */
157 addr = cmBase + CM_DSP_CLKSTCTRL;
158 OUTREG32(addr, 0x02);
160 do {
161 val = INREG32(addr);
162 if (val & 0x100) {
163 Osal_printf("DSP clock enabled:DSP_CLKSTCTRL = 0x%x\n", val);
164 break;
165 }
166 } while (--counter);
167 if (counter == 0) {
168 Osal_printf("FAILED TO ENABLE DSP CLOCK !\n");
169 status = -1;
170 break;
171 }
173 /* Check that releasing resets would indeed be effective */
174 addr = prmBase + RM_DSP_RSTCTRL;
175 val = INREG32(addr);
176 if (val != 3) {
177 Osal_printf("DSP Resets in not proper state! [0x%x]\n", val);
178 OUTREG32(addr, 0x3);
179 counter = 1000;
181 while ((--counter)&&((INREG32(addr) & 0x3) != 0x3));
182 if (counter == 0) {
183 Osal_printf("RESET bits not set in DSP reset Ctrl!\n");
184 status = -1;
185 break;
186 }
187 }
188 /* De-assert RST2, and clear the Reset status */
189 OUTREG32(addr, 0x1);
190 addr = prmBase + RM_DSP_RSTST;
192 while (!((INREG32(addr))& 0x2));
194 Osal_printf("DSP:RST2 released!\n");
195 OUTREG32(addr, 0x2);
197 /* enable MMU0 and MMU1 through global system register */
198 val = INREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET);
199 OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x11) | 0x11);
200 Osal_printf("DSP:SYS_MMU_CONFIG MMU0 and MMU1 enabled!\n");
201 }
202 break;
204 case Processor_ResetCtrlCmd_Release:
205 {
206 addr = prmBase + PM_DSP_PWRSTCTRL;
207 val = INREG32(addr);
208 val |= 0x7;
209 OUTREG32(addr, val);
210 addr = prmBase + PM_DSP_PWRSTST;
211 val = INREG32(addr);
212 /* Module is managed automatically by HW */
213 addr = cmBase + CM_DSP_DSP_CLKCTRL;
214 OUTREG32(addr, 0x01);
215 /* Enable the DSP clock */
216 addr = cmBase + CM_DSP_CLKSTCTRL;
217 OUTREG32(addr, 0x02);
219 /*De-assert RST2 and clear the Reset Status */
220 addr = prmBase + RM_DSP_RSTCTRL;
221 Osal_printf("De-assert DSP RST1\n");
222 OUTREG32(addr, 0x0);
223 Osal_printf("DSP:RST1 released!\n");
224 addr = prmBase + RM_DSP_RSTST;
225 OUTREG32(addr, 0x1);
226 }
227 break;
229 default:
230 {
231 /*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
232 status = PROCESSOR_E_INVALIDARG;
233 GT_setFailureReason(curTrace, GT_4CLASS,
234 "VAYUDSP_halResetCtrl", status,
235 "Unsupported reset ctrl cmd specified");
236 }
237 break;
238 }
240 GT_1trace(curTrace, GT_LEAVE, "VAYUDSP_halResetCtrl", status);
242 /*! @retval PROCESSOR_SUCCESS Operation successful */
243 return status;
244 }
247 #if defined (__cplusplus)
248 }
249 #endif