[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / omap4430 / ipu / omap4430DucatiHalReset.c
1 /*
2 * @file omap4430DucatiHalReset.c
3 *
4 * @brief Reset control module.
5 *
6 * This module is responsible for handling reset-related hardware-
7 * specific operations.
8 * The implementation is specific to OMAP4430DUCATI.
9 *
10 *
11 * @ver 02.00.00.44_pre-alpha3
12 *
13 * ============================================================================
14 *
15 * Copyright (c) 2008-2009, Texas Instruments Incorporated
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 *
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * * Neither the name of Texas Instruments Incorporated nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
34 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
35 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
36 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
37 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
38 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
39 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
40 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
41 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
42 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Contact information for paper mail:
44 * Texas Instruments
45 * Post Office Box 655303
46 * Dallas, Texas 75265
47 * Contact information:
48 * http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
49 * DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
50 * ============================================================================
51 *
52 */
54 /*QNX specific header include */
55 #include <errno.h>
57 /* Standard headers */
58 #include <ti/syslink/Std.h>
60 /* OSAL & Utils headers */
61 #include <ti/syslink/utils/Trace.h>
62 #include <Bitops.h>
64 /* Module level headers */
65 #include <_ProcDefs.h>
66 #include <Processor.h>
67 #include <OsalDrv.h>
69 /* Hardware Abstraction Layer headers */
70 #include <OMAP4430DucatiHal.h>
71 #include <OMAP4430DucatiHalReset.h>
72 #include "OMAP4430DucatiEnabler.h"
73 #include <hw/inout.h>
74 #include <_ipu_pm.h>
75 #include <ipu_pm.h>
77 #if defined (__cplusplus)
78 extern "C" {
79 #endif
82 /* =============================================================================
83 * Macros and types
84 * =============================================================================
85 */
86 #define GPT_IRQSTATUS_OFFSET 0x28
88 /* =============================================================================
89 * APIs called by OMAP4430DUCATIPROC module
90 * =============================================================================
91 */
92 /*!
93 * @brief Function to control reset operations
94 *
95 * @param halObj Pointer to the HAL object
96 * @param cmd Reset control command
97 * @param arg Arguments specific to the reset control command
98 *
99 * @sa
100 */
101 Int
102 OMAP4430DUCATI_halResetCtrl (Ptr halObj, Processor_ResetCtrlCmd cmd,UInt32 entryPt)
103 {
104 Int status = PROCESSOR_SUCCESS;
105 OMAP4430DUCATI_HalObject * halObject = NULL;
106 UINT32 pa;
107 int counter = 10;
108 UINT32 M3RstCtrl;
109 UINT32 M3ClkCtrl;
110 UINT32 M3RstSt;
111 UINT32 M3ClkStCtrl;
112 Int ret;
114 GT_3trace (curTrace, GT_ENTER, "OMAP4430DUCATI_halResetCtrl", halObj, cmd, entryPt);
116 GT_assert (curTrace, (halObj != NULL));
117 GT_assert (curTrace, (cmd < Processor_ResetCtrlCmd_EndValue));
119 ULONG reg = 0;
120 ULONG resets = 0;
121 pa = RM_MPU_M3_RSTCTRL;
122 M3RstCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
124 pa = CM_MPU_M3_MPU_M3_CLKCTRL;
125 M3ClkCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
127 pa = RM_MPU_M3_RSTST;
128 M3RstSt = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
129 pa = CM_MPU_M3_CLKSTCTRL;
130 M3ClkStCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
132 halObject = (OMAP4430DUCATI_HalObject *) halObj ;
134 switch (cmd) {
135 case Processor_ResetCtrlCmd_Reset:
136 {
137 switch (halObject->procId) {
138 case PROCTYPE_SYSM3:
139 /* Put SYSM3 into reset */
140 SETBITREG32(M3RstCtrl, RM_MPU_M3_RST1_BIT);
141 /* Read back the reset control register */
142 reg = INREG32(M3RstCtrl);
143 /* Disable the GPT3 clock, which is used by CORE0 */
144 ret = ipu_pm_gpt_stop(GPTIMER_3);
145 if (ret != EOK) {
146 status = PROCESSOR_E_FAIL;
147 GT_setFailureReason (curTrace, GT_4CLASS,
148 "OMAP4430DUCATI_halResetCtrl",
149 status,
150 "Failed to stop gpt 3");
151 }
152 ret = ipu_pm_gpt_disable(GPTIMER_3);
153 if (ret != EOK) {
154 status = PROCESSOR_E_FAIL;
155 GT_setFailureReason (curTrace, GT_4CLASS,
156 "OMAP4430DUCATI_halResetCtrl",
157 status,
158 "Failed to disable gpt 3");
159 }
160 break;
161 case PROCTYPE_APPM3:
162 /* Put APPM3 into reset */
163 SETBITREG32(M3RstCtrl, RM_MPU_M3_RST2_BIT);
164 #ifndef SYSLINK_SYSBIOS_SMP
165 /* Disable the GPT4 clock, which is used by CORE1 */
166 ret = ipu_pm_gpt_stop(GPTIMER_4);
167 if (ret != EOK) {
168 status = PROCESSOR_E_FAIL;
169 GT_setFailureReason (curTrace, GT_4CLASS,
170 "OMAP4430DUCATI_halResetCtrl",
171 status,
172 "Failed to stop gpt 4");
173 }
174 ret = ipu_pm_gpt_disable(GPTIMER_4);
175 if (ret != EOK) {
176 status = PROCESSOR_E_FAIL;
177 GT_setFailureReason (curTrace, GT_4CLASS,
178 "OMAP4430DUCATI_halResetCtrl",
179 status,
180 "Failed to disable gpt 4");
181 }
182 #endif
183 break;
184 default:
185 break;
186 }
187 }
188 break;
190 case Processor_ResetCtrlCmd_MMU_Reset:
191 {
192 switch (halObject->procId) {
193 case PROCTYPE_SYSM3:
194 /* Put M3 MMU into reset */
195 SETBITREG32(M3RstCtrl, RM_MPU_M3_RST3_BIT);
196 /* Disable the M3 clock */
197 OUTREG32(M3ClkCtrl, 0x01);
198 break;
199 case PROCTYPE_APPM3:
200 break;
201 default:
202 break;
203 }
204 }
205 break;
207 case Processor_ResetCtrlCmd_MMU_Release:
208 {
209 reg = INREG32(M3RstSt);
210 if (reg != 0x0) {
211 Osal_printf("OMAP4430DUCATI_halResetCtrl: clearing reset status!");
212 OUTREG32(M3RstSt,reg);
213 do {
214 if ((reg = INREG32(M3RstSt)) == 0x0)
215 break;
216 } while (--counter);
218 if (reg == 0x0) {
219 Osal_printf("OMAP4430DUCATI_halResetCtrl: reset state reset!");
220 }
221 else {
222 status = PROCESSOR_E_FAIL;
223 GT_setFailureReason (curTrace, GT_4CLASS,
224 "OMAP4430DUCATI_halResetCtrl", status,
225 "Failed to clear reset status");
226 }
227 }
228 if (status >= 0) {
229 reg = INREG32(M3RstCtrl);
230 Osal_printf("OMAP4430DUCATI_halResetCtrl: Reset Control [0x%x]",
231 reg);
233 switch (halObject->procId) {
234 case PROCTYPE_SYSM3:
235 /* Module is managed automatically by HW */
236 OUTREG32(M3ClkCtrl,
237 CM_MPU_M3_MPU_M3_CLKCTRL_MODULEMODE_HWAUTO);
238 /* Enable the M3 clock */
239 OUTREG32(M3ClkStCtrl, CM_MPU_M3_CLKSTCTRL_CTRL_SW_WKUP);
241 counter = 10;
242 do {
243 if (TESTBITREG32(M3ClkStCtrl,
244 CM_MPU_M3_CLKSTCTRL_CLKACTIVITY_BIT)) {
245 Osal_printf("M3 clock enabled:"
246 "CORE_CM2_DUCATI_CLKSTCTRL = 0x%x",
247 INREG32(M3ClkStCtrl));
248 break;
249 }
250 } while (--counter);
252 if (counter == 0) {
253 Osal_printf("FAILED TO ENABLE DUCATI M3 CLOCK !");
254 return PROCESSOR_E_OSFAILURE;
255 }
257 /* Check that releasing resets would indeed be
258 * effective */
259 reg = INREG32(M3RstCtrl);
260 resets = RM_MPU_M3_RST3 | RM_MPU_M3_RST2 | RM_MPU_M3_RST1;
261 if (reg != resets) {
262 Osal_printf("OMAP4430DUCATI_halResetCtrl: "
263 "Resets in not proper state! [0x%x]",
264 reg);
265 OUTREG32(M3RstCtrl,resets);
266 counter = 10;
267 do {
268 if ((INREG32(M3RstCtrl) & resets) == resets)
269 break;
270 } while (--counter);
272 if (counter == 0) {
273 status = PROCESSOR_E_FAIL;
274 GT_setFailureReason (curTrace, GT_4CLASS,
275 "OMAP4430DUCATI_halResetCtrl",
276 status,
277 "Failed to put resets in proper state");
278 }
279 }
281 if (status >= 0) {
282 /* De-assert RST3, and clear the Reset status */
283 Osal_printf("De-assert RST3");
284 CLRBITREG32(M3RstCtrl, RM_MPU_M3_RST3_BIT);
286 counter = 10;
287 do {
288 if (INREG32(M3RstSt) & RM_MPU_M3_RST3ST)
289 break;
290 } while (--counter);
291 if (counter == 0) {
292 status = PROCESSOR_E_FAIL;
293 GT_setFailureReason (curTrace, GT_4CLASS,
294 "OMAP4430DUCATI_halResetCtrl",
295 status,
296 "Failed to release RST3");
297 }
298 else {
299 Osal_printf("RST3 released!");
300 SETBITREG32(M3RstSt, RM_MPU_M3_RST3ST_BIT);
301 }
302 }
303 break;
304 case PROCTYPE_APPM3:
305 break;
306 default:
307 Osal_printf("proc4430_start: ERROR input");
308 break;
309 }
310 }
311 }
312 break;
314 case Processor_ResetCtrlCmd_Release:
315 {
316 switch (halObject->procId) {
317 case PROCTYPE_SYSM3:
318 /* Enable the GPT3 clock, which is used by CORE0 */
319 ret = ipu_pm_gpt_enable(GPTIMER_3);
320 if (ret != EOK) {
321 status = PROCESSOR_E_FAIL;
322 GT_setFailureReason (curTrace, GT_4CLASS,
323 "OMAP4430DUCATI_halResetCtrl",
324 status,
325 "Failed to enable gpt 3");
326 }
327 else {
328 restore_gpt_context(GPTIMER_3);
329 ret = ipu_pm_gpt_start(GPTIMER_3);
330 if (ret != EOK) {
331 status = PROCESSOR_E_FAIL;
332 GT_setFailureReason (curTrace, GT_4CLASS,
333 "OMAP4430DUCATI_halResetCtrl",
334 status,
335 "Failed to start gpt 3");
336 }
337 else {
338 /* De-assert RST1, and clear the Reset status */
339 Osal_printf("De-assert RST1");
340 CLRBITREG32(M3RstCtrl, RM_MPU_M3_RST1_BIT);
342 counter = 10;
343 do {
344 if (INREG32(M3RstSt) & RM_MPU_M3_RST1)
345 break;
346 } while (--counter);
347 if (counter == 0) {
348 status = PROCESSOR_E_FAIL;
349 GT_setFailureReason (curTrace, GT_4CLASS,
350 "OMAP4430DUCATI_halResetCtrl",
351 status,
352 "Failed to release RST1");
353 }
354 else {
355 Osal_printf("RST1 released!");
356 SETBITREG32(M3RstSt, RM_MPU_M3_RST1ST_BIT);
358 /* Setting to HW_AUTO Mode */
359 reg = INREG32(M3ClkStCtrl);
360 reg &= ~CM_MPU_M3_CLKSTCTRL_CTRL_BITMASK;
361 reg |= CM_MPU_M3_CLKSTCTRL_CTRL_HW_AUTO;
362 OUTREG32(M3ClkStCtrl, reg);
363 }
364 }
365 }
366 break;
367 case PROCTYPE_APPM3:
368 #ifndef SYSLINK_SYSBIOS_SMP
369 /* Enable the GPT4 clock, which is used by CORE1 */
370 ret = ipu_pm_gpt_enable(GPTIMER_4);
371 if (ret != EOK) {
372 status = PROCESSOR_E_FAIL;
373 GT_setFailureReason (curTrace, GT_4CLASS,
374 "OMAP4430DUCATI_halResetCtrl",
375 status,
376 "Failed to enable gpt 4");
377 }
378 else {
379 restore_gpt_context(GPTIMER_4);
380 ipu_pm_gpt_start(GPTIMER_4);
381 #endif
383 /* De-assert RST2, and clear the Reset status */
384 CLRBITREG32(M3RstCtrl, RM_MPU_M3_RST2_BIT);
386 counter = 10;
387 do {
388 if (INREG32(M3RstSt) & RM_MPU_M3_RST2)
389 break;
390 } while (--counter);
391 if (counter == 0) {
392 status = PROCESSOR_E_FAIL;
393 GT_setFailureReason (curTrace, GT_4CLASS,
394 "OMAP4430DUCATI_halResetCtrl",
395 status,
396 "Failed to release RST2");
397 }
398 else {
399 Osal_printf("RST2 released!");
400 SETBITREG32(M3RstSt, RM_MPU_M3_RST2ST_BIT);
401 /* Wait until ducati is in idle */
402 //while(TESTBITREG32(M3ClkStCtrl,
403 // CM_MPU_M3_CLKSTCTRL_CLKACTIVITY_BIT));
404 }
405 #ifndef SYSLINK_SYSBIOS_SMP
406 }
407 #endif
408 break;
409 default:
410 Osal_printf("OMAP430DUCATI_halResetCtrl: ERROR input");
411 break;
412 }
413 }
414 break;
416 default:
417 {
418 /*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
419 status = PROCESSOR_E_INVALIDARG;
420 GT_setFailureReason (curTrace,
421 GT_4CLASS,
422 "OMAP4430DUCATI_halResetCtrl",
423 status,
424 "Unsupported reset ctrl cmd specified");
425 }
426 break;
427 }
428 OsalDrv_ioUnmap(M3ClkStCtrl, sizeof(ULONG));
429 OsalDrv_ioUnmap(M3ClkCtrl, sizeof(ULONG));
430 OsalDrv_ioUnmap(M3RstCtrl, sizeof(ULONG));
431 OsalDrv_ioUnmap(M3RstSt, sizeof(ULONG));
432 GT_1trace (curTrace, GT_LEAVE, "OMAP4430DUCATI_halResetCtrl", status);
434 /*! @retval PROCESSOR_SUCCESS Operation successful */
436 return status;
437 }
440 #if defined (__cplusplus)
441 }
442 #endif