1 /*
2 * @file hw_mbox.h
3 *
4 * @brief Functions required to program MMU
5 *
6 *
7 * ============================================================================
8 *
9 * Copyright (c) 2010-2011, Texas Instruments Incorporated
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
33 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
34 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
35 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
36 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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45 *
46 */
48 #ifndef __HW_MMU_H
49 #define __HW_MMU_H
52 /* Bitmasks for interrupt sources */
53 #define HW_MMU_TRANSLATION_FAULT 0x2
54 #define HW_MMU_ALL_INTERRUPTS 0x1F
56 #define HW_MMU_COARSE_PAGE_SIZE 0x400
58 /* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow
59 CPU/TLB Element size */
60 enum hw_mmu_mixed_size_t {
61 HW_MMU_TLBES,
62 HW_MMU_CPUES
64 } ;
66 /* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */
67 struct hw_mmu_map_attrs_t {
68 enum hw_endianism_t endianism;
69 enum hw_elemnt_siz_t element_size;
70 enum hw_mmu_mixed_size_t mixedSize;
71 } ;
73 extern hw_status hw_mmu_enable(const UInt32 base_address);
75 extern hw_status hw_mmu_disable(const UInt32 base_address);
77 extern hw_status hw_mmu_numlocked_set(const UInt32 base_address,
78 UInt32 num_lcked_entries);
80 extern hw_status hw_mmu_victim_numset(const UInt32 base_address,
81 UInt32 vctm_entry_num);
83 /* For MMU faults */
84 extern hw_status hw_mmu_eventack(const UInt32 base_address,
85 UInt32 irq_mask);
87 extern hw_status hw_mmu_event_disable(const UInt32 base_address,
88 UInt32 irq_mask);
90 extern hw_status hw_mmu_event_enable(const UInt32 base_address,
91 UInt32 irq_mask);
93 extern hw_status hw_mmu_event_status(const UInt32 base_address,
94 UInt32 *irq_mask);
96 extern hw_status hw_mmu_flt_adr_rd(const UInt32 base_address,
97 UInt32 *addr);
99 /* Set the TT base address */
100 extern hw_status hw_mmu_ttbset(const UInt32 base_address,
101 UInt32 ttb_phys_addr);
103 extern hw_status hw_mmu_twl_enable(const UInt32 base_address);
105 extern hw_status hw_mmu_twl_disable(const UInt32 base_address);
107 extern hw_status hw_mmu_tlb_flush(const UInt32 base_address,
108 UInt32 virtual_addr,
109 UInt32 page_size);
111 extern hw_status hw_mmu_tlb_flushAll(const UInt32 base_address);
113 extern hw_status hw_mmu_tlb_add(const UInt32 base_address,
114 UInt32 physical_addr,
115 UInt32 virtual_addr,
116 UInt32 page_size,
117 UInt32 entryNum,
118 struct hw_mmu_map_attrs_t *map_attrs,
119 enum hw_set_clear_t preserve_bit,
120 enum hw_set_clear_t valid_bit);
123 /* For PTEs */
124 extern hw_status hw_mmu_pte_set(const UInt32 pg_tbl_va,
125 UInt32 physical_addr,
126 UInt32 virtual_addr,
127 UInt32 page_size,
128 struct hw_mmu_map_attrs_t *map_attrs);
130 extern hw_status hw_mmu_pte_clear(const UInt32 pg_tbl_va,
131 UInt32 pg_size,
132 UInt32 virtual_addr);
134 static inline UInt32 hw_mmu_pte_addr_l1(UInt32 l1_base, UInt32 va)
135 {
136 UInt32 pte_addr;
137 UInt32 VA_31_to_20;
139 VA_31_to_20 = va >> (20 - 2); /* Left-shift by 2 here itself */
140 VA_31_to_20 &= 0xFFFFFFFCUL;
141 pte_addr = l1_base + VA_31_to_20;
143 return pte_addr;
144 }
146 static inline UInt32 hw_mmu_pte_addr_l2(UInt32 l2_base, UInt32 va)
147 {
148 UInt32 pte_addr;
150 pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
152 return pte_addr;
153 }
155 static inline UInt32 hw_mmu_pte_coarsel1(UInt32 pte_val)
156 {
157 UInt32 pteCoarse;
159 pteCoarse = pte_val & 0xFFFFFC00;
161 return pteCoarse;
162 }
164 static inline UInt32 hw_mmu_pte_sizel1(UInt32 pte_val)
165 {
166 UInt32 pte_size = 0;
168 if ((pte_val & 0x3) == 0x1) {
169 /* Points to L2 PT */
170 pte_size = HW_MMU_COARSE_PAGE_SIZE;
171 }
173 if ((pte_val & 0x3) == 0x2) {
174 if (pte_val & (1 << 18))
175 pte_size = HW_PAGE_SIZE_16MB;
176 else
177 pte_size = HW_PAGE_SIZE_1MB;
178 }
180 return pte_size;
181 }
183 static inline UInt32 hw_mmu_pte_sizel2(UInt32 pte_val)
184 {
185 UInt32 pte_size = 0;
187 if (pte_val & 0x2)
188 pte_size = HW_PAGE_SIZE_4KB;
189 else if (pte_val & 0x1)
190 pte_size = HW_PAGE_SIZE_64KB;
192 return pte_size;
193 }
194 extern hw_status hw_mmu_tlb_dump(UInt32 base_address, BOOL shw_inv_entries);
196 extern UInt32 hw_mmu_pte_phyaddr(UInt32 pte_val, UInt32 pte_size);
198 #endif /* __HW_MMU_H */