QNX: Remove dead virtio-related macros
[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / omap5430 / ipu / omap5430BenelliHalReset.c
1 /*
2  * Copyright (c) 2010-2014, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * *  Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  *
12  * *  Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * *  Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
33 /*
34  *  @file   omap5430BenelliHalReset.c
35  *
36  *  @brief      Reset control module.
37  *
38  *              This module is responsible for handling reset-related hardware-
39  *              specific operations.
40  *              The implementation is specific to OMAP5430BENELLI.
41  *
42  */
44 /*QNX specific header include */
45 #include <errno.h>
47 /* Standard headers */
48 #include <ti/syslink/Std.h>
50 /* OSAL & Utils headers */
51 #include <ti/syslink/utils/Trace.h>
52 #include <Bitops.h>
54 /* Module level headers */
55 #include <_ProcDefs.h>
56 #include <Processor.h>
57 #include <OsalDrv.h>
59 /* Hardware Abstraction Layer headers */
60 #include <OMAP5430BenelliHal.h>
61 #include <OMAP5430BenelliHalReset.h>
62 #include "OMAP5430BenelliEnabler.h"
63 #include <hw/inout.h>
64 #include <_ipu_pm.h>
65 #include <ipu_pm.h>
67 #if defined (__cplusplus)
68 extern "C" {
69 #endif
72 /* =============================================================================
73  *  Macros and types
74  * =============================================================================
75  */
76 #define GPT_IRQSTATUS_OFFSET 0x28
78 /* =============================================================================
79  * APIs called by OMAP5430BENELLIPROC module
80  * =============================================================================
81  */
82 /*!
83  *  @brief      Function to control reset operations
84  *
85  *  @param      halObj  Pointer to the HAL object
86  *  @param      cmd     Reset control command
87  *  @param      arg     Arguments specific to the reset control command
88  *
89  *  @sa
90  */
91 Int
92 OMAP5430BENELLI_halResetCtrl (Ptr halObj, Processor_ResetCtrlCmd cmd)
93 {
94     Int                  status    = PROCESSOR_SUCCESS;
95     OMAP5430BENELLI_HalObject * halObject = NULL;
96     UINT32 pa;
97     int counter = 10;
98     UINT32 IPURstCtrl;
99     UINT32 IPUClkCtrl;
100     UINT32 IPURstSt;
101     UINT32 IPUClkStCtrl;
102     UINT32 DSPRstCtrl;
103     UINT32 DSPClkCtrl;
104     UINT32 DSPPwrStCtrl;
105     UINT32 DSPPwrSt;
106     UINT32 DSPRstSt;
107     UINT32 DSPClkStCtrl;
108     Int ret;
110     GT_2trace (curTrace, GT_ENTER, "OMAP5430BENELLI_halResetCtrl", halObj, cmd);
112     GT_assert (curTrace, (halObj != NULL));
113     GT_assert (curTrace, (cmd < Processor_ResetCtrlCmd_EndValue));
115     ULONG reg = 0;
116     ULONG resets = 0;
117     pa = RM_IPU_RSTCTRL;
118     IPURstCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
120     pa = CM_IPU_IPU_CLKCTRL;
121     IPUClkCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
123     pa = RM_IPU_RSTST;
124     IPURstSt = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
125     pa = CM_IPU_CLKSTCTRL;
126     IPUClkStCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
128     pa = PM_DSP_PWRSTCTRL;
129     DSPPwrStCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
131     pa = PM_DSP_PWRSTST;
132     DSPPwrSt = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
134     pa = RM_DSP_RSTCTRL;
135     DSPRstCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
137     pa = RM_DSP_RSTST;
138     DSPRstSt = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
140     pa = CM_DSP_DSP_CLKCTRL;
141     DSPClkCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
143     pa = CM_DSP_CLKSTCTRL;
144     DSPClkStCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
146     halObject = (OMAP5430BENELLI_HalObject *) halObj ;
148     switch (cmd) {
149         case Processor_ResetCtrlCmd_Reset:
150         {
151             switch (halObject->procId) {
152                 case PROCTYPE_IPU0:
153 #ifdef SYSLINK_SYSBIOS_SMP
154                     /* Put IPU core 1 into reset */
155                     SETBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
156 #endif
157                     /* Put IPU core 0 into reset */
158                     SETBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
159                     /* Read back the reset control register */
160                     reg = INREG32(IPURstCtrl);
162                     /* Disable the GPT3 clock, which is used by CORE0 */
163                     ret = ipu_pm_gpt_stop(GPTIMER_3);
164                     if (ret != EOK) {
165                         status = PROCESSOR_E_FAIL;
166                         GT_setFailureReason (curTrace, GT_4CLASS,
167                                              "OMAP5430DUCATI_halResetCtrl",
168                                              status,
169                                              "Failed to stop gpt 3");
170                     }
171                     ret = ipu_pm_gpt_disable(GPTIMER_3);
172                     if (ret != EOK) {
173                         status = PROCESSOR_E_FAIL;
174                         GT_setFailureReason (curTrace, GT_4CLASS,
175                                              "OMAP5430DUCATI_halResetCtrl",
176                                              status,
177                                              "Failed to disable gpt 3");
178                     }
179                     break;
180 #ifndef SYSLINK_SYSBIOS_SMP
181                 case PROCTYPE_IPU1:
182                     /* Put IPU core 1 into reset */
183                     SETBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
185                     /* Disable the GPT4 clock, which is used by CORE1 */
186                     ret = ipu_pm_gpt_stop(GPTIMER_4);
187                     if (ret != EOK) {
188                         status = PROCESSOR_E_FAIL;
189                         GT_setFailureReason (curTrace, GT_4CLASS,
190                                              "OMAP5430DUCATI_halResetCtrl",
191                                              status,
192                                              "Failed to stop gpt 4");
193                     }
194                     ret = ipu_pm_gpt_disable(GPTIMER_4);
195                     if (ret != EOK) {
196                         status = PROCESSOR_E_FAIL;
197                         GT_setFailureReason (curTrace, GT_4CLASS,
198                                              "OMAP5430DUCATI_halResetCtrl",
199                                              status,
200                                              "Failed to disable gpt 4");
201                     }
202                     break;
203 #endif
204                 case PROCTYPE_DSP:
205                     SETBITREG32(DSPRstCtrl, RM_DSP_RSTCTRL_BIT);
206                     ret = ipu_pm_gpt_stop(GPTIMER_5);
207                     if (ret != EOK) {
208                         status = PROCESSOR_E_FAIL;
209                         GT_setFailureReason (curTrace, GT_4CLASS,
210                                              "OMAP5430DUCATI_halResetCtrl",
211                                              status,
212                                              "Failed to stop gpt 5");
213                     }
214                     ret = ipu_pm_gpt_disable(GPTIMER_5);
215                     if (ret != EOK) {
216                         status = PROCESSOR_E_FAIL;
217                         GT_setFailureReason (curTrace, GT_4CLASS,
218                                              "OMAP5430DUCATI_halResetCtrl",
219                                              status,
220                                              "Failed to disable gpt 5");
221                     }
222                     break;
223                 default:
224                     break;
225             }
226         }
227         break;
229         case Processor_ResetCtrlCmd_MMU_Reset:
230         {
231             switch (halObject->procId) {
232                 case PROCTYPE_IPU0:
233                     /* Put IPU MMU into reset */
234                     SETBITREG32(IPURstCtrl, RM_IPU_RST3_BIT);
235                     /* Disable the IPU clock */
236                     OUTREG32(IPUClkCtrl, 0x01);
237                     break;
238 #ifndef SYSLINK_SYSBIOS_SMP
239                 case PROCTYPE_IPU1:
240                     break;
241 #endif
242                 case PROCTYPE_DSP:
243                     SETBITREG32(DSPRstCtrl, RM_DSP_MMU_RSTCTRL_BIT);
244                     break;
245                 default:
246                     break;
247             }
248         }
249         break;
251         case Processor_ResetCtrlCmd_MMU_Release:
252         {
253             if(halObject->procId != PROCTYPE_DSP) {
254                 reg = INREG32(IPURstSt);
255                 if (reg != 0x0) {
256                     Osal_printf("OMAP5430BENELLI_halResetCtrl: clearing reset status!");
257                     OUTREG32(IPURstSt, reg);
258                     do {
259                         if ((reg = INREG32(IPURstSt)) == 0x0)
260                         break;
261                     } while (--counter);
263                     if (reg == 0x0) {
264                         Osal_printf("OMAP5430BENELLI_halResetCtrl: reset state reset!");
265                     }
266                     else {
267                         status = PROCESSOR_E_FAIL;
268                         GT_setFailureReason (curTrace, GT_4CLASS,
269                                              "OMAP5430BENELLI_halResetCtrl", status,
270                                              "Failed to clear reset status");
271                     }
272                 }
273             }
274             if (status >= 0) {
276                 switch (halObject->procId) {
277                     case PROCTYPE_IPU0:
278                         /* Module is managed automatically by HW */
279                         OUTREG32(IPUClkCtrl,
280                                   CM_IPU_IPU_CLKCTRL_MODULEMODE_HWAUTO);
281                         /* Enable the IPU clock */
282                         OUTREG32(IPUClkStCtrl, CM_IPU_CLKSTCTRL_CTRL_SW_WKUP);
284                         counter = 10;
285                         do {
286                             if (TESTBITREG32(IPUClkStCtrl,
287                                              CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT)) {
288                                 Osal_printf("IPU clock enabled:"
289                                             "CORE_CM_IPU_CLKSTCTRL = 0x%x",
290                                             INREG32(IPUClkStCtrl));
291                                 break;
292                             }
293                         } while (--counter);
295                         if (counter == 0) {
296                             Osal_printf("FAILED TO ENABLE IPU CLOCK !");
297                             return PROCESSOR_E_OSFAILURE;
298                         }
300                         /* Check that releasing resets would indeed be
301                          * effective */
302                         reg =  INREG32(IPURstCtrl);
303                         resets = RM_IPU_RST3 | RM_IPU_RST2 | RM_IPU_RST1;
304                         if (reg != resets) {
305                             Osal_printf("OMAP5430BENELLI_halResetCtrl: "
306                                         "Resets in not proper state! [0x%x]",
307                                         reg);
308                             OUTREG32(IPURstCtrl,resets);
309                             counter = 10;
310                             do {
311                                 if ((INREG32(IPURstCtrl) & resets) == resets)
312                                     break;
313                             } while (--counter);
315                             if (counter == 0) {
316                                 status = PROCESSOR_E_FAIL;
317                                 GT_setFailureReason (curTrace, GT_4CLASS,
318                                         "OMAP5430BENELLI_halResetCtrl",
319                                         status,
320                                         "Failed to put resets in proper state");
321                             }
322                         }
324                         if (status >= 0) {
325                             /* De-assert RST3, and clear the Reset status */
326                             Osal_printf("De-assert RST3");
327                             CLRBITREG32(IPURstCtrl, RM_IPU_RST3_BIT);
329                             counter = 10;
330                             do {
331                                 if (INREG32(IPURstSt) & RM_IPU_RST3ST)
332                                     break;
333                             } while (--counter);
334                             if (counter == 0) {
335                                 status = PROCESSOR_E_FAIL;
336                                 GT_setFailureReason (curTrace, GT_4CLASS,
337                                                   "OMAP5430BENELLI_halResetCtrl",
338                                                   status,
339                                                   "Failed to release RST3");
340                             }
341                             else {
342                                 Osal_printf("RST3 released!");
343                                 SETBITREG32(IPURstSt, RM_IPU_RST3ST_BIT);
344                             }
345                         }
346                         break;
347 #ifndef SYSLINK_SYSBIOS_SMP
348                     case PROCTYPE_IPU1:
349                         break;
350 #endif
351                     case PROCTYPE_DSP:
352                          /* Enable the GPT5 clock, which is used by DSP */
353                         ret = ipu_pm_gpt_enable(GPTIMER_5);
354                         if (ret != EOK) {
355                             status = PROCESSOR_E_FAIL;
356                             GT_setFailureReason (curTrace, GT_4CLASS,
357                                                  "OMAP5430BENELLI_halResetCtrl",
358                                                  status,
359                                                  "Failed to enable gpt 5");
360                         }
361                         else {
362                             restore_gpt_context(GPTIMER_5);
363                             ipu_pm_gpt_start(GPTIMER_5);
364                             reg = INREG32(DSPRstSt);
365                             if (reg != 0x0) {
366                                 Osal_printf("OMAP5430BENELLI_halResetCtrl: clearing DSP reset status!");
367                                 OUTREG32(DSPRstSt, reg);
368                                 counter = 10;
369                                 do {
370                                     if (INREG32(DSPRstSt) == 0x0)
371                                         break;
372                                 } while (--counter);
373                                 if (counter == 0) {
374                                     status = PROCESSOR_E_FAIL;
375                                     GT_setFailureReason (curTrace, GT_4CLASS,
376                                                       "OMAP5430BENELLI_halResetCtrl",
377                                                       status,
378                                                       "Failed to release RST3");
379                                 }
380                                 else {
381                                     Osal_printf("OMAP5430BENELLI_halResetCtrl: DSP reset state reset!");
382                                 }
383                             }
384                         }
386                         if (status >= 0) {
387                             reg = INREG32(DSPPwrStCtrl);
388                             reg |= 0x7;
389                             OUTREG32(DSPPwrStCtrl, reg);
390                             reg = INREG32(DSPPwrSt);
391                             /* Module is managed automatically by HW */
392                             OUTREG32(DSPClkCtrl, 0x01);
393                             /* Enable the DSP clock */
394                             OUTREG32(DSPClkStCtrl, 0x03);
395                             counter = 10;
396                             do {
397                                 reg = INREG32(DSPClkStCtrl);
398                                 if (reg & 0x100) {
399                                     Osal_printf("DSP clock enabled:DSP_CLKSTCTRL = 0x%x", reg);
400                                     break;
401                                 }
402                             } while (--counter);
403                             if (counter == 0) {
404                                 status = PROCESSOR_E_FAIL;
405                                 GT_setFailureReason (curTrace, GT_4CLASS,
406                                                      "OMAP5430BENELLI_halResetCtrl",
407                                                      status,
408                                                      "FAILED TO ENABLE DSP CLOCK");
409                             }
410                         }
412                         if (status >= 0) {
413                             /* Check that releasing resets would indeed be effective */
414                             reg =  INREG32(DSPRstCtrl);
415                             if (reg != 3) {
416                                 Osal_printf("proc5430_start: DSP Resets in not proper state! [0x%x]", reg);
417                                 OUTREG32(DSPRstCtrl,0x3);
418                                 counter = 1000;
419                                 while ((--counter)&&((INREG32(DSPRstCtrl) & 0x3) != 0x3));
420                                 if (counter == 0) {
421                                     status = PROCESSOR_E_FAIL;
422                                     GT_setFailureReason (curTrace, GT_4CLASS,
423                                                          "OMAP5430BENELLI_halResetCtrl",
424                                                          status,
425                                                          "RESET bits not set in DSP reset Ctrl");
426                                 }
427                             }
428                             if (status >= 0) {
429                                 /* De-assert RST3, and clear the Reset status */
430                                 OUTREG32(DSPRstCtrl,0x1);
431                                 counter = 10;
432                                 do {
433                                     if (INREG32(DSPRstSt) & 0x2)
434                                         break;
435                                 } while (--counter);
436                                 if (counter == 0) {
437                                     status = PROCESSOR_E_FAIL;
438                                     GT_setFailureReason (curTrace, GT_4CLASS,
439                                                          "OMAP5430BENELLI_halResetCtrl",
440                                                          status,
441                                                          "Failed to deassert reset 3");
442                                 }
443                                 else {
444                                     /* De-assert RST3, and clear the Reset status */
445                                     OUTREG32(DSPRstCtrl,0x1);
446                                     counter = 10;
447                                     do {
448                                         if (INREG32(DSPRstSt) & 0x2)
449                                             break;
450                                     } while (--counter);
451                                     if (counter == 0) {
452                                         status = PROCESSOR_E_FAIL;
453                                         GT_setFailureReason (curTrace, GT_4CLASS,
454                                                              "OMAP5430BENELLI_halResetCtrl",
455                                                              status,
456                                                              "Failed to deassert reset 3");
457                                     }
458                                     else {
459                                         Osal_printf("DSP:RST2 released!");
460                                         OUTREG32(DSPRstSt,0x2);
461                                     }
462                                 }
463                             }
464                         }
465                         break;
466                     default:
467                         Osal_printf("proc5430_start: ERROR input");
468                         break;
469                 }
470             }
471         }
472         break;
474         case Processor_ResetCtrlCmd_Release:
475         {
476             switch (halObject->procId) {
477                 case PROCTYPE_IPU0:
478                     /* Enable the GPT3 clock, which is used by CORE0 */
479                     ret = ipu_pm_gpt_enable(GPTIMER_3);
480                     if (ret != EOK) {
481                         status = PROCESSOR_E_FAIL;
482                         GT_setFailureReason (curTrace, GT_4CLASS,
483                                              "OMAP5430BENELLI_halResetCtrl",
484                                              status,
485                                              "Failed to enable gpt 3");
486                     }
487                     else {
488                         restore_gpt_context(GPTIMER_3);
489                         ret = ipu_pm_gpt_start(GPTIMER_3);
490                         if (ret != EOK) {
491                             status = PROCESSOR_E_FAIL;
492                             GT_setFailureReason (curTrace, GT_4CLASS,
493                                                  "OMAP5430BENELLI_halResetCtrl",
494                                                  status,
495                                                  "Failed to start gpt 3");
496                         }
497                         else {
498                             /* De-assert RST1, and clear the Reset status */
499                             Osal_printf("De-assert RST1");
500                             CLRBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
502                             counter = 10;
503                             do {
504                                 if (INREG32(IPURstSt) & RM_IPU_RST1)
505                                     break;
506                             } while (--counter);
507                             if (counter == 0) {
508                                 status = PROCESSOR_E_FAIL;
509                                 GT_setFailureReason (curTrace, GT_4CLASS,
510                                                   "OMAP5430BENNELI_halResetCtrl",
511                                                   status,
512                                                   "Failed to release RST1");
513                             }
514                             else {
515                                 Osal_printf("RST1 released!");
516                                 SETBITREG32(IPURstSt, RM_IPU_RST1ST_BIT);
518                                 /* Setting to HW_AUTO Mode */
519                                 reg = INREG32(IPUClkStCtrl);
520                                 reg &= ~CM_IPU_CLKSTCTRL_CTRL_BITMASK;
521                                 reg |= CM_IPU_CLKSTCTRL_CTRL_HW_AUTO;
522                                 OUTREG32(IPUClkStCtrl, reg);
523 #ifdef SYSLINK_SYSBIOS_SMP
524                                 /* De-assert RST2, and clear the Reset status */
525                                 CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
527                                 counter = 10;
528                                 do {
529                                     if (INREG32(IPURstSt) & RM_IPU_RST2)
530                                         break;
531                                 } while (--counter);
532                                 if (counter == 0) {
533                                     status = PROCESSOR_E_FAIL;
534                                     GT_setFailureReason (curTrace, GT_4CLASS,
535                                                          "OMAP5430BENELLI_halResetCtrl",
536                                                          status,
537                                                          "Failed to release RST2");
538                                 }
539                                 else {
540                                     Osal_printf("RST2 released!");
541                                     SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
542                                 }
543 #endif // ifdef SYSLINK_SYSBIOS_SMP
544                             }
545                         }
546                     }
547                     break;
548 #ifndef SYSLINK_SYSBIOS_SMP
549                 case PROCTYPE_IPU1:
550                     /* Enable the GPT4 clock, which is used by CORE1 */
551                     ret = ipu_pm_gpt_enable(GPTIMER_4);
552                     if (ret != EOK) {
553                         status = PROCESSOR_E_FAIL;
554                         GT_setFailureReason (curTrace, GT_4CLASS,
555                                              "OMAP5430BENELLI_halResetCtrl",
556                                              status,
557                                              "Failed to enable gpt 4");
558                     }
559                     else {
560                         restore_gpt_context(GPTIMER_4);
561                         ipu_pm_gpt_start(GPTIMER_4);
563                         /* De-assert RST2, and clear the Reset status */
564                         CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
566                         counter = 10;
567                         do {
568                             if (INREG32(IPURstSt) & RM_IPU_RST2)
569                                 break;
570                         } while (--counter);
571                         if (counter == 0) {
572                             status = PROCESSOR_E_FAIL;
573                             GT_setFailureReason (curTrace, GT_4CLASS,
574                                                  "OMAP5430BENELLI_halResetCtrl",
575                                                  status,
576                                                  "Failed to release RST2");
577                         }
578                         else {
579                             Osal_printf("RST2 released!");
580                             SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
582                             /* Wait until benelli is in idle */
583                             //while(TESTBITREG32(IPUClkStCtrl,
584                             //               CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT));
585                         }
586                     }
587                     break;
588 #endif
589                 case PROCTYPE_DSP:
590                     /*De-assert RST2 and clear the Reset Status */
591                     Osal_printf("De-assert DSP RST1");
592                     OUTREG32(DSPRstCtrl, 0x0);
593                     Osal_printf("DSP:RST2 released!");
594                     OUTREG32(DSPRstSt,0x1);
595                     break;
596                 default:
597                     Osal_printf("OMAP5430BENELLI_halResetCtrl: ERROR input");
598                     break;
599             }
600         }
601         break;
603         default:
604         {
605             /*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
606             status = PROCESSOR_E_INVALIDARG;
607             GT_setFailureReason (curTrace,
608                                  GT_4CLASS,
609                                  "OMAP5430BENELLI_halResetCtrl",
610                                  status,
611                                  "Unsupported reset ctrl cmd specified");
612         }
613         break;
614     }
615     OsalDrv_ioUnmap(IPUClkStCtrl, sizeof(ULONG));
616     OsalDrv_ioUnmap(IPUClkCtrl, sizeof(ULONG));
617     OsalDrv_ioUnmap(IPURstCtrl, sizeof(ULONG));
618     OsalDrv_ioUnmap(IPURstSt, sizeof(ULONG));
619     OsalDrv_ioUnmap(DSPClkStCtrl, sizeof(ULONG));
620     OsalDrv_ioUnmap(DSPClkCtrl, sizeof(ULONG));
621     OsalDrv_ioUnmap(DSPRstCtrl, sizeof(ULONG));
622     OsalDrv_ioUnmap(DSPRstSt, sizeof(ULONG));
623     OsalDrv_ioUnmap(DSPPwrSt, sizeof(ULONG));
624     OsalDrv_ioUnmap(DSPPwrStCtrl, sizeof(ULONG));
625     GT_1trace (curTrace, GT_LEAVE, "OMAP5430BENELLI_halResetCtrl", status);
627     /*! @retval PROCESSOR_SUCCESS Operation successful */
629     return status;
633 #if defined (__cplusplus)
635 #endif