c7985f33b36c6fcc15576e244b8eb0fdf22934e9
[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / omap5430 / ipu / omap5430BenelliHalReset.c
1 /*
2  * Copyright (c) 2010-2013, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * *  Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  *
12  * *  Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * *  Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
33 /*
34  *  @file   omap5430BenelliHalReset.c
35  *
36  *  @brief      Reset control module.
37  *
38  *              This module is responsible for handling reset-related hardware-
39  *              specific operations.
40  *              The implementation is specific to OMAP5430BENELLI.
41  *
42  */
44 /*QNX specific header include */
45 #include <errno.h>
47 /* Standard headers */
48 #include <ti/syslink/Std.h>
50 /* OSAL & Utils headers */
51 #include <ti/syslink/utils/Trace.h>
52 #include <Bitops.h>
54 /* Module level headers */
55 #include <_ProcDefs.h>
56 #include <Processor.h>
57 #include <OsalDrv.h>
59 /* Hardware Abstraction Layer headers */
60 #include <OMAP5430BenelliHal.h>
61 #include <OMAP5430BenelliHalReset.h>
62 #include "OMAP5430BenelliEnabler.h"
63 #include <hw/inout.h>
64 #include <_ipu_pm.h>
65 #include <ipu_pm.h>
67 #if defined (__cplusplus)
68 extern "C" {
69 #endif
72 /* =============================================================================
73  *  Macros and types
74  * =============================================================================
75  */
76 #define GPT_IRQSTATUS_OFFSET 0x28
78 /* =============================================================================
79  * APIs called by OMAP5430BENELLIPROC module
80  * =============================================================================
81  */
82 /*!
83  *  @brief      Function to control reset operations
84  *
85  *  @param      halObj  Pointer to the HAL object
86  *  @param      cmd     Reset control command
87  *  @param      arg     Arguments specific to the reset control command
88  *
89  *  @sa
90  */
91 Int
92 OMAP5430BENELLI_halResetCtrl (Ptr halObj, Processor_ResetCtrlCmd cmd)
93 {
94     Int                  status    = PROCESSOR_SUCCESS;
95     OMAP5430BENELLI_HalObject * halObject = NULL;
96     UINT32 pa;
97     int counter = 10;
98     UINT32 IPURstCtrl;
99     UINT32 IPUClkCtrl;
100     UINT32 IPURstSt;
101     UINT32 IPUClkStCtrl;
102     UINT32 DSPRstCtrl;
103     UINT32 DSPClkCtrl;
104     UINT32 DSPPwrStCtrl;
105     UINT32 DSPPwrSt;
106     UINT32 DSPRstSt;
107     UINT32 DSPClkStCtrl;
108     Int ret;
110     GT_2trace (curTrace, GT_ENTER, "OMAP5430BENELLI_halResetCtrl", halObj, cmd);
112     GT_assert (curTrace, (halObj != NULL));
113     GT_assert (curTrace, (cmd < Processor_ResetCtrlCmd_EndValue));
115     ULONG reg = 0;
116     ULONG resets = 0;
117     pa = RM_IPU_RSTCTRL;
118     IPURstCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
120     pa = CM_IPU_IPU_CLKCTRL;
121     IPUClkCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
123     pa = RM_IPU_RSTST;
124     IPURstSt = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
125     pa = CM_IPU_CLKSTCTRL;
126     IPUClkStCtrl = (UINT32)OsalDrv_ioMap(pa, sizeof(ULONG));
128     pa = PM_DSP_PWRSTCTRL;
129     DSPPwrStCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
131     pa = PM_DSP_PWRSTST;
132     DSPPwrSt = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
134     pa = RM_DSP_RSTCTRL;
135     DSPRstCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
137     pa = RM_DSP_RSTST;
138     DSPRstSt = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
140     pa = CM_DSP_DSP_CLKCTRL;
141     DSPClkCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
143     pa = CM_DSP_CLKSTCTRL;
144     DSPClkStCtrl = (UINT32)OsalDrv_ioMap(pa,sizeof(ULONG));
146     halObject = (OMAP5430BENELLI_HalObject *) halObj ;
148     switch (cmd) {
149         case Processor_ResetCtrlCmd_Reset:
150         {
151             switch (halObject->procId) {
152                 case PROCTYPE_IPU0:
153 #ifdef SYSLINK_SYSBIOS_SMP
154                     /* Put IPU core 1 into reset */
155                     SETBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
156 #endif
157                     /* Put IPU core 0 into reset */
158                     SETBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
159                     /* Read back the reset control register */
160                     reg = INREG32(IPURstCtrl);
161 #ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
162                     /* Disable the GPT3 clock, which is used by CORE0 */
163                     ret = ipu_pm_gpt_stop(GPTIMER_3);
164                     if (ret != EOK) {
165                         status = PROCESSOR_E_FAIL;
166                         GT_setFailureReason (curTrace, GT_4CLASS,
167                                              "OMAP5430DUCATI_halResetCtrl",
168                                              status,
169                                              "Failed to stop gpt 3");
170                     }
171                     ret = ipu_pm_gpt_disable(GPTIMER_3);
172                     if (ret != EOK) {
173                         status = PROCESSOR_E_FAIL;
174                         GT_setFailureReason (curTrace, GT_4CLASS,
175                                              "OMAP5430DUCATI_halResetCtrl",
176                                              status,
177                                              "Failed to disable gpt 3");
178                     }
179 #endif
180                     break;
181 #ifndef SYSLINK_SYSBIOS_SMP
182                 case PROCTYPE_IPU1:
183                     /* Put IPU core 1 into reset */
184                     SETBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
185 #ifndef OMAP5430_VIRTIO // skip this check, reset status not modeled properly
186                     /* Disable the GPT4 clock, which is used by CORE1 */
187                     ret = ipu_pm_gpt_stop(GPTIMER_4);
188                     if (ret != EOK) {
189                         status = PROCESSOR_E_FAIL;
190                         GT_setFailureReason (curTrace, GT_4CLASS,
191                                              "OMAP5430DUCATI_halResetCtrl",
192                                              status,
193                                              "Failed to stop gpt 4");
194                     }
195                     ret = ipu_pm_gpt_disable(GPTIMER_4);
196                     if (ret != EOK) {
197                         status = PROCESSOR_E_FAIL;
198                         GT_setFailureReason (curTrace, GT_4CLASS,
199                                              "OMAP5430DUCATI_halResetCtrl",
200                                              status,
201                                              "Failed to disable gpt 4");
202                     }
203 #endif
204                     break;
205 #endif
206                 case PROCTYPE_DSP:
207                     SETBITREG32(DSPRstCtrl, RM_DSP_RSTCTRL_BIT);
208                     ret = ipu_pm_gpt_stop(GPTIMER_5);
209                     if (ret != EOK) {
210                         status = PROCESSOR_E_FAIL;
211                         GT_setFailureReason (curTrace, GT_4CLASS,
212                                              "OMAP5430DUCATI_halResetCtrl",
213                                              status,
214                                              "Failed to stop gpt 5");
215                     }
216                     ret = ipu_pm_gpt_disable(GPTIMER_5);
217                     if (ret != EOK) {
218                         status = PROCESSOR_E_FAIL;
219                         GT_setFailureReason (curTrace, GT_4CLASS,
220                                              "OMAP5430DUCATI_halResetCtrl",
221                                              status,
222                                              "Failed to disable gpt 5");
223                     }
224                     break;
225                 default:
226                     break;
227             }
228         }
229         break;
231         case Processor_ResetCtrlCmd_MMU_Reset:
232         {
233             switch (halObject->procId) {
234                 case PROCTYPE_IPU0:
235                     /* Put IPU MMU into reset */
236                     SETBITREG32(IPURstCtrl, RM_IPU_RST3_BIT);
237                     /* Disable the IPU clock */
238                     OUTREG32(IPUClkCtrl, 0x01);
239                     break;
240 #ifndef SYSLINK_SYSBIOS_SMP
241                 case PROCTYPE_IPU1:
242                     break;
243 #endif
244                 case PROCTYPE_DSP:
245                     SETBITREG32(DSPRstCtrl, RM_DSP_MMU_RSTCTRL_BIT);
246                     break;
247                 default:
248                     break;
249             }
250         }
251         break;
253         case Processor_ResetCtrlCmd_MMU_Release:
254         {
255             if(halObject->procId != PROCTYPE_DSP) {
256                 reg = INREG32(IPURstSt);
257                 if (reg != 0x0) {
258                     Osal_printf("OMAP5430BENELLI_halResetCtrl: clearing reset status!");
259                     OUTREG32(IPURstSt, reg);
260                     do {
261                         if ((reg = INREG32(IPURstSt)) == 0x0)
262                         break;
263                     } while (--counter);
265                     if (reg == 0x0) {
266                         Osal_printf("OMAP5430BENELLI_halResetCtrl: reset state reset!");
267                     }
268                     else {
269                         status = PROCESSOR_E_FAIL;
270                         GT_setFailureReason (curTrace, GT_4CLASS,
271                                              "OMAP5430BENELLI_halResetCtrl", status,
272                                              "Failed to clear reset status");
273                     }
274                 }
275             }
276             if (status >= 0) {
278                 switch (halObject->procId) {
279                     case PROCTYPE_IPU0:
280                         /* Module is managed automatically by HW */
281                         OUTREG32(IPUClkCtrl,
282                                   CM_IPU_IPU_CLKCTRL_MODULEMODE_HWAUTO);
283                         /* Enable the IPU clock */
284                         OUTREG32(IPUClkStCtrl, CM_IPU_CLKSTCTRL_CTRL_SW_WKUP);
286                         counter = 10;
287                         do {
288                             if (TESTBITREG32(IPUClkStCtrl,
289                                              CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT)) {
290                                 Osal_printf("IPU clock enabled:"
291                                             "CORE_CM_IPU_CLKSTCTRL = 0x%x",
292                                             INREG32(IPUClkStCtrl));
293                                 break;
294                             }
295                         } while (--counter);
297 #ifndef OMAP5430_VIRTIO // skip this check
298                         if (counter == 0) {
299                             Osal_printf("FAILED TO ENABLE IPU CLOCK !");
300                             return PROCESSOR_E_OSFAILURE;
301                         }
302 #endif
304                         /* Check that releasing resets would indeed be
305                          * effective */
306                         reg =  INREG32(IPURstCtrl);
307                         resets = RM_IPU_RST3 | RM_IPU_RST2 | RM_IPU_RST1;
308                         if (reg != resets) {
309                             Osal_printf("OMAP5430BENELLI_halResetCtrl: "
310                                         "Resets in not proper state! [0x%x]",
311                                         reg);
312                             OUTREG32(IPURstCtrl,resets);
313                             counter = 10;
314                             do {
315                                 if ((INREG32(IPURstCtrl) & resets) == resets)
316                                     break;
317                             } while (--counter);
319                             if (counter == 0) {
320                                 status = PROCESSOR_E_FAIL;
321                                 GT_setFailureReason (curTrace, GT_4CLASS,
322                                         "OMAP5430BENELLI_halResetCtrl",
323                                         status,
324                                         "Failed to put resets in proper state");
325                             }
326                         }
328                         if (status >= 0) {
329                             /* De-assert RST3, and clear the Reset status */
330                             Osal_printf("De-assert RST3");
331                             CLRBITREG32(IPURstCtrl, RM_IPU_RST3_BIT);
333 #ifndef OMAP5430_VIRTIO // skip this check, reset status not modeled properly
334                             counter = 10;
335                             do {
336                                 if (INREG32(IPURstSt) & RM_IPU_RST3ST)
337                                     break;
338                             } while (--counter);
339                             if (counter == 0) {
340                                 status = PROCESSOR_E_FAIL;
341                                 GT_setFailureReason (curTrace, GT_4CLASS,
342                                                   "OMAP5430BENELLI_halResetCtrl",
343                                                   status,
344                                                   "Failed to release RST3");
345                             }
346                             else {
347                                 Osal_printf("RST3 released!");
348                                 SETBITREG32(IPURstSt, RM_IPU_RST3ST_BIT);
349                             }
350                         }
351 #endif
352                         break;
353 #ifndef SYSLINK_SYSBIOS_SMP
354                     case PROCTYPE_IPU1:
355                         break;
356 #endif
357                     case PROCTYPE_DSP:
358                          /* Enable the GPT5 clock, which is used by DSP */
359                         ret = ipu_pm_gpt_enable(GPTIMER_5);
360                         if (ret != EOK) {
361                             status = PROCESSOR_E_FAIL;
362                             GT_setFailureReason (curTrace, GT_4CLASS,
363                                                  "OMAP5430BENELLI_halResetCtrl",
364                                                  status,
365                                                  "Failed to enable gpt 5");
366                         }
367                         else {
368                             restore_gpt_context(GPTIMER_5);
369                             ipu_pm_gpt_start(GPTIMER_5);
370                             reg = INREG32(DSPRstSt);
371                             if (reg != 0x0) {
372                                 Osal_printf("OMAP5430BENELLI_halResetCtrl: clearing DSP reset status!");
373                                 OUTREG32(DSPRstSt, reg);
374                                 counter = 10;
375                                 do {
376                                     if (INREG32(DSPRstSt) == 0x0)
377                                         break;
378                                 } while (--counter);
379                                 if (counter == 0) {
380                                     status = PROCESSOR_E_FAIL;
381                                     GT_setFailureReason (curTrace, GT_4CLASS,
382                                                       "OMAP5430BENELLI_halResetCtrl",
383                                                       status,
384                                                       "Failed to release RST3");
385                                 }
386                                 else {
387                                     Osal_printf("OMAP5430BENELLI_halResetCtrl: DSP reset state reset!");
388                                 }
389                             }
390                         }
392                         if (status >= 0) {
393                             reg = INREG32(DSPPwrStCtrl);
394                             reg |= 0x7;
395                             OUTREG32(DSPPwrStCtrl, reg);
396                             reg = INREG32(DSPPwrSt);
397                             /* Module is managed automatically by HW */
398                             OUTREG32(DSPClkCtrl, 0x01);
399                             /* Enable the DSP clock */
400                             OUTREG32(DSPClkStCtrl, 0x03);
401                             counter = 10;
402                             do {
403                                 reg = INREG32(DSPClkStCtrl);
404                                 if (reg & 0x100) {
405                                     Osal_printf("DSP clock enabled:DSP_CLKSTCTRL = 0x%x", reg);
406                                     break;
407                                 }
408                             } while (--counter);
409                             if (counter == 0) {
410                                 status = PROCESSOR_E_FAIL;
411                                 GT_setFailureReason (curTrace, GT_4CLASS,
412                                                      "OMAP5430BENELLI_halResetCtrl",
413                                                      status,
414                                                      "FAILED TO ENABLE DSP CLOCK");
415                             }
416                         }
418                         if (status >= 0) {
419                             /* Check that releasing resets would indeed be effective */
420                             reg =  INREG32(DSPRstCtrl);
421                             if (reg != 3) {
422                                 Osal_printf("proc5430_start: DSP Resets in not proper state! [0x%x]", reg);
423                                 OUTREG32(DSPRstCtrl,0x3);
424                                 counter = 1000;
425                                 while ((--counter)&&((INREG32(DSPRstCtrl) & 0x3) != 0x3));
426                                 if (counter == 0) {
427                                     status = PROCESSOR_E_FAIL;
428                                     GT_setFailureReason (curTrace, GT_4CLASS,
429                                                          "OMAP5430BENELLI_halResetCtrl",
430                                                          status,
431                                                          "RESET bits not set in DSP reset Ctrl");
432                                 }
433                             }
434                             if (status >= 0) {
435                                 /* De-assert RST3, and clear the Reset status */
436                                 OUTREG32(DSPRstCtrl,0x1);
437                                 counter = 10;
438                                 do {
439                                     if (INREG32(DSPRstSt) & 0x2)
440                                         break;
441                                 } while (--counter);
442                                 if (counter == 0) {
443                                     status = PROCESSOR_E_FAIL;
444                                     GT_setFailureReason (curTrace, GT_4CLASS,
445                                                          "OMAP5430BENELLI_halResetCtrl",
446                                                          status,
447                                                          "Failed to deassert reset 3");
448                                 }
449                                 else {
450                                     /* De-assert RST3, and clear the Reset status */
451                                     OUTREG32(DSPRstCtrl,0x1);
452                                     counter = 10;
453                                     do {
454                                         if (INREG32(DSPRstSt) & 0x2)
455                                             break;
456                                     } while (--counter);
457                                     if (counter == 0) {
458                                         status = PROCESSOR_E_FAIL;
459                                         GT_setFailureReason (curTrace, GT_4CLASS,
460                                                              "OMAP5430BENELLI_halResetCtrl",
461                                                              status,
462                                                              "Failed to deassert reset 3");
463                                     }
464                                     else {
465                                         Osal_printf("DSP:RST2 released!");
466                                         OUTREG32(DSPRstSt,0x2);
467                                     }
468                                 }
469                             }
470                         }
471                         break;
472                     default:
473                         Osal_printf("proc5430_start: ERROR input");
474                         break;
475                 }
476             }
477         }
478         break;
480         case Processor_ResetCtrlCmd_Release:
481         {
482             switch (halObject->procId) {
483                 case PROCTYPE_IPU0:
484 #ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
485                     /* Enable the GPT3 clock, which is used by CORE0 */
486                     ret = ipu_pm_gpt_enable(GPTIMER_3);
487                     if (ret != EOK) {
488                         status = PROCESSOR_E_FAIL;
489                         GT_setFailureReason (curTrace, GT_4CLASS,
490                                              "OMAP5430BENELLI_halResetCtrl",
491                                              status,
492                                              "Failed to enable gpt 3");
493                     }
494                     else {
495                         restore_gpt_context(GPTIMER_3);
496                         ret = ipu_pm_gpt_start(GPTIMER_3);
497                         if (ret != EOK) {
498                             status = PROCESSOR_E_FAIL;
499                             GT_setFailureReason (curTrace, GT_4CLASS,
500                                                  "OMAP5430BENELLI_halResetCtrl",
501                                                  status,
502                                                  "Failed to start gpt 3");
503                         }
504                         else {
505 #endif // ifndef OMAP5430_VIRTIO
506                             /* De-assert RST1, and clear the Reset status */
507                             Osal_printf("De-assert RST1");
508                             CLRBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
510 #ifndef OMAP5430_VIRTIO // skip this check for now
511                             counter = 10;
512                             do {
513                                 if (INREG32(IPURstSt) & RM_IPU_RST1)
514                                     break;
515                             } while (--counter);
516                             if (counter == 0) {
517                                 status = PROCESSOR_E_FAIL;
518                                 GT_setFailureReason (curTrace, GT_4CLASS,
519                                                   "OMAP5430BENNELI_halResetCtrl",
520                                                   status,
521                                                   "Failed to release RST1");
522                             }
523                             else {
524 #endif // ifndef OMAP5430_VIRTIO
525                                 Osal_printf("RST1 released!");
526                                 SETBITREG32(IPURstSt, RM_IPU_RST1ST_BIT);
528                                 /* Setting to HW_AUTO Mode */
529                                 reg = INREG32(IPUClkStCtrl);
530                                 reg &= ~CM_IPU_CLKSTCTRL_CTRL_BITMASK;
531                                 reg |= CM_IPU_CLKSTCTRL_CTRL_HW_AUTO;
532                                 OUTREG32(IPUClkStCtrl, reg);
533 #ifdef SYSLINK_SYSBIOS_SMP
534                                 /* De-assert RST2, and clear the Reset status */
535                                 CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
536 #ifndef OMAP5430_VIRTIO // skip this check for now
537                                 counter = 10;
538                                 do {
539                                     if (INREG32(IPURstSt) & RM_IPU_RST2)
540                                         break;
541                                 } while (--counter);
542                                 if (counter == 0) {
543                                     status = PROCESSOR_E_FAIL;
544                                     GT_setFailureReason (curTrace, GT_4CLASS,
545                                                          "OMAP5430BENELLI_halResetCtrl",
546                                                          status,
547                                                          "Failed to release RST2");
548                                 }
549                                 else {
550 #endif // ifndef OMAP5430_VIRTIO
551                                     Osal_printf("RST2 released!");
552                                     SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
553 #ifndef OMAP5430_VIRTIO // skip this check for now
554                                 }
555 #endif // ifndef OMAP5430_VIRTIO
556 #endif // ifdef SYSLINK_SYSBIOS_SMP
557 #ifndef OMAP5430_VIRTIO // skip this check for now
558                             }
559                         }
560                     }
561 #endif // ifndef OMAP5430_VIRTIO
562                     break;
563 #ifndef SYSLINK_SYSBIOS_SMP
564                 case PROCTYPE_IPU1:
565 #ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
566                     /* Enable the GPT4 clock, which is used by CORE1 */
567                     ret = ipu_pm_gpt_enable(GPTIMER_4);
568                     if (ret != EOK) {
569                         status = PROCESSOR_E_FAIL;
570                         GT_setFailureReason (curTrace, GT_4CLASS,
571                                              "OMAP5430BENELLI_halResetCtrl",
572                                              status,
573                                              "Failed to enable gpt 4");
574                     }
575                     else {
576                         restore_gpt_context(GPTIMER_4);
577                         ipu_pm_gpt_start(GPTIMER_4);
578 #endif
580                         /* De-assert RST2, and clear the Reset status */
581                         CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
583 #ifndef OMAP5430_VIRTIO // skip this check for now
584                         counter = 10;
585                         do {
586                             if (INREG32(IPURstSt) & RM_IPU_RST2)
587                                 break;
588                         } while (--counter);
589                         if (counter == 0) {
590                             status = PROCESSOR_E_FAIL;
591                             GT_setFailureReason (curTrace, GT_4CLASS,
592                                                  "OMAP5430BENELLI_halResetCtrl",
593                                                  status,
594                                                  "Failed to release RST2");
595                         }
596                         else {
597                             Osal_printf("RST2 released!");
598                             SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
599 #endif
600                             /* Wait until benelli is in idle */
601                             //while(TESTBITREG32(IPUClkStCtrl,
602                             //               CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT));
603 #ifndef OMAP5430_VIRTIO // skip this check for now
604                         }
605 #endif
606                     }
607                     break;
608 #endif
609                 case PROCTYPE_DSP:
610                     /*De-assert RST2 and clear the Reset Status */
611                     Osal_printf("De-assert DSP RST1");
612                     OUTREG32(DSPRstCtrl, 0x0);
613                     Osal_printf("DSP:RST2 released!");
614                     OUTREG32(DSPRstSt,0x1);
615                     break;
616                 default:
617                     Osal_printf("OMAP5430BENELLI_halResetCtrl: ERROR input");
618                     break;
619             }
620         }
621         break;
623         default:
624         {
625             /*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
626             status = PROCESSOR_E_INVALIDARG;
627             GT_setFailureReason (curTrace,
628                                  GT_4CLASS,
629                                  "OMAP5430BENELLI_halResetCtrl",
630                                  status,
631                                  "Unsupported reset ctrl cmd specified");
632         }
633         break;
634     }
635     OsalDrv_ioUnmap(IPUClkStCtrl, sizeof(ULONG));
636     OsalDrv_ioUnmap(IPUClkCtrl, sizeof(ULONG));
637     OsalDrv_ioUnmap(IPURstCtrl, sizeof(ULONG));
638     OsalDrv_ioUnmap(IPURstSt, sizeof(ULONG));
639     OsalDrv_ioUnmap(DSPClkStCtrl, sizeof(ULONG));
640     OsalDrv_ioUnmap(DSPClkCtrl, sizeof(ULONG));
641     OsalDrv_ioUnmap(DSPRstCtrl, sizeof(ULONG));
642     OsalDrv_ioUnmap(DSPRstSt, sizeof(ULONG));
643     OsalDrv_ioUnmap(DSPPwrSt, sizeof(ULONG));
644     OsalDrv_ioUnmap(DSPPwrStCtrl, sizeof(ULONG));
645     GT_1trace (curTrace, GT_LEAVE, "OMAP5430BENELLI_halResetCtrl", status);
647     /*! @retval PROCESSOR_SUCCESS Operation successful */
649     return status;
653 #if defined (__cplusplus)
655 #endif